@inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{2352, author = {{Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and Yuecel, Mustafa}}, booktitle = {{Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}}, isbn = {{978-1-4244-5108-1}}, keywords = {{WSN, PermaSense}}, pages = {{265--276}}, publisher = {{IEEE Computer Society}}, title = {{{PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}}}, year = {{2009}}, } @inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2263, abstract = {{In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. }}, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-101-5}}, pages = {{319--322}}, publisher = {{CSREA Press}}, title = {{{Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}}}, year = {{2009}}, } @inproceedings{1974, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Risks and Security of Internet and Systems}}, title = {{{Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures}}}, year = {{2008}}, } @inproceedings{1975, abstract = {{Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies}}, title = {{{Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems}}}, doi = {{10.1007/978-3-540-88708-9_1}}, year = {{2008}}, } @inproceedings{1976, abstract = {{Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems}}, title = {{{Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids}}}, doi = {{10.1109/ICPP-W.2008.40}}, year = {{2008}}, } @inproceedings{1978, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Grid Computing and Applications (GCA)}}, title = {{{Germany, Belgium, France, and Back Again: Job Migration using Globus}}}, year = {{2008}}, } @inproceedings{1980, abstract = {{OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Services Computing (SCC)}}, title = {{{Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids}}}, doi = {{10.1109/SCC.2008.106}}, year = {{2008}}, } @inproceedings{1981, abstract = {{Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Grid and Pervasive Computing (GPC)}}, isbn = {{978-0-7695-3177-9}}, pages = {{43--48}}, title = {{{Job Migration and Fault Tolerance in SLA-aware Resource Management Systems}}}, doi = {{10.1109/GPC.WORKSHOPS.2008.71}}, year = {{2008}}, } @inproceedings{1983, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS)}}, editor = {{Gonzalez, T. F.}}, isbn = {{978-0-88986-773-4}}, pages = {{212--218}}, title = {{{Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance}}}, year = {{2008}}, } @inproceedings{2355, author = {{Brinkmann, André and Effert, Sascha}}, booktitle = {{Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS)}}, pages = {{551--554}}, publisher = {{Springer}}, title = {{{Redundant Data Placement Strategies for Cluster Storage Environments}}}, doi = {{10.1007/978-3-540-92221-6_38}}, year = {{2008}}, } @inproceedings{2356, author = {{Brinkmann, André and Gudenkauf, Stefan and Hasselbring, Wilhelm and Höing, André and Karl, Holger and Kao, Odej and Nitsche, Holger and Scherp, Guido}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, pages = {{103--110}}, title = {{{Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware}}}, year = {{2008}}, } @inproceedings{2357, author = {{Birkenheuer, Georg and Brinkmann, André and Dömer, Hubert and Effert, Sascha and Konersmann, Christoph and Niehörster, Oliver and Simon, Jens}}, booktitle = {{Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management}}, pages = {{37--49}}, publisher = {{Leibniz-Rechenzentrum}}, title = {{{Virtual Supercomputer for HPC and HTC}}}, year = {{2008}}, } @inproceedings{2358, author = {{Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}}, booktitle = {{IEEE Nuclear Science Symposium Conference Record (NSS)}}, pages = {{4161--4168}}, publisher = {{IEEE}}, title = {{{A method for OSEM PET reconstruction on parallel architectures using STIR}}}, doi = {{10.1109/NSSMIC.2008.4774198}}, year = {{2008}}, } @inproceedings{2359, author = {{Battré, Dominic and Birkenheuer, Georg and Deora, Vikas and Hovestadt, Matthias and Rana, Omer and Wäldrich, Oliver}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, pages = {{213--220}}, title = {{{Guarantee and Penalty Clauses for Service Level Agreements}}}, year = {{2008}}, } @inproceedings{2360, author = {{Richert, Willi and Niehörster, Oliver and Koch, Markus}}, booktitle = {{Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS)}}, publisher = {{IEEE}}, title = {{{Layered understanding for sporadic imitation in a multi-robot scenario}}}, doi = {{10.1109/IROS.2008.4650817}}, year = {{2008}}, } @inproceedings{2363, author = {{Lietsch, Stefan and Zabel, Henning and Laroque, Christoph}}, booktitle = {{Proc. ASME Computers and Information in Engineering Conference (CIE)}}, pages = {{1493--1502}}, publisher = {{ASME}}, title = {{{Computational Steering Of Interactive Material Flow Simulations}}}, doi = {{10.1115/DETC2008-49405}}, year = {{2008}}, } @inproceedings{2365, author = {{Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{The GOmputer: Accelerating GO with FPGAs}}}, year = {{2008}}, }