[{"author":[{"first_name":"Robert","full_name":"Schade, Robert","last_name":"Schade"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter"},{"full_name":"Elgabarty, Hossam","first_name":"Hossam","last_name":"Elgabarty"},{"last_name":"Lass","first_name":"Michael","full_name":"Lass, Michael"},{"last_name":"Schütt","full_name":"Schütt, Ole","first_name":"Ole"},{"full_name":"Lazzaro, Alfio","first_name":"Alfio","last_name":"Lazzaro"},{"first_name":"Hans","full_name":"Pabst, Hans","last_name":"Pabst"},{"full_name":"Mohr, Stephan","first_name":"Stephan","last_name":"Mohr"},{"last_name":"Hutter","full_name":"Hutter, Jürg","first_name":"Jürg"},{"full_name":"Kühne, Thomas D.","first_name":"Thomas D.","last_name":"Kühne"},{"last_name":"Plessl","full_name":"Plessl, Christian","first_name":"Christian"}],"department":[{"_id":"27"}],"publication":"arXiv:2104.08245","status":"public","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2022-06-28T07:48:31Z","abstract":[{"lang":"eng","text":"We push the boundaries of electronic structure-based \\textit{ab-initio}\r\nmolecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise\r\nbarely reachable with classical force-field methods or novel neural network and\r\nmachine learning potentials. We achieve this breakthrough by combining\r\ninnovations in linear-scaling AIMD, efficient and approximate sparse linear\r\nalgebra, low and mixed-precision floating-point computation on GPUs, and a\r\ncompensation scheme for the errors introduced by numerical approximations. The\r\ncore of our work is the non-orthogonalized local submatrix method (NOLSM),\r\nwhich scales very favorably to massively parallel computing systems and\r\ntranslates large sparse matrix operations into highly parallel, dense matrix\r\noperations that are ideally suited to hardware accelerators. We demonstrate\r\nthat the NOLSM method, which is at the center point of each AIMD step, is able\r\nto achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision\r\ncorresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs."}],"external_id":{"arxiv":["2104.08245"]},"user_id":"15278","title":"Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms","language":[{"iso":"eng"}],"citation":{"mla":"Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021.","bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et al._2021, title={Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms}, journal={arXiv:2104.08245}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas D. and et al.}, year={2021} }","chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt, Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021.","ama":"Schade R, Kenter T, Elgabarty H, et al. Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms. arXiv:210408245. Published online 2021.","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T. D., & Plessl, C. (2021). Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms. In arXiv:2104.08245.","ieee":"R. Schade et al., “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms,” arXiv:2104.08245. 2021.","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T.D. Kühne, C. Plessl, ArXiv:2104.08245 (2021)."},"type":"preprint","year":"2021","date_updated":"2022-06-28T07:49:31Z","_id":"32244"},{"language":[{"iso":"eng"}],"year":"2021","citation":{"ieee":"M. Meyer, “Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks,” 2021, doi: 10.1145/3468044.3468058.","short":"M. Meyer, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021.","mla":"Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021, doi:10.1145/3468044.3468058.","bibtex":"@inproceedings{Meyer_2021, title={Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks}, DOI={10.1145/3468044.3468058}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Meyer, Marius}, year={2021} }","chicago":"Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” In Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021. https://doi.org/10.1145/3468044.3468058.","apa":"Meyer, M. (2021). Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3468044.3468058","ama":"Meyer M. Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ; 2021. doi:10.1145/3468044.3468058"},"type":"conference","_id":"27365","date_updated":"2022-01-06T06:57:38Z","doi":"10.1145/3468044.3468058","author":[{"full_name":"Meyer, Marius","first_name":"Marius","id":"40778","last_name":"Meyer"}],"publication":"Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","department":[{"_id":"27"}],"status":"public","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2021-11-10T14:42:17Z","publication_status":"published","user_id":"40778","title":"Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks"},{"quality_controlled":"1","author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"last_name":"Schade","id":"75963","first_name":"Robert","orcid":"0000-0002-6268-539","full_name":"Schade, Robert"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE Computer Society","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","status":"public","date_created":"2020-04-28T14:44:21Z","abstract":[{"text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs.","lang":"eng"}],"user_id":"75963","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"type":"conference","citation":{"mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140."},"year":"2020","page":"1127-1140","_id":"16898","conference":{"name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","location":"Atlanta, GA, US"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"_id":"32","name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"place":"Los Alamitos, CA, USA","external_id":{"arxiv":["2004.10811"]},"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","language":[{"iso":"eng"}],"date_updated":"2023-08-02T14:55:59Z","doi":"10.1109/SC41405.2020.00084"},{"date_updated":"2023-09-26T11:42:53Z","doi":"10.1109/h2rc51942.2020.00007","language":[{"iso":"eng"}],"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","related_material":{"link":[{"description":"Official repository of the benchmark suite on GitHub","relation":"supplementary_material","url":"https://github.com/pc2/HPCC_FPGA"}]},"department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"21632","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"year":"2020","type":"conference","citation":{"short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007."},"abstract":[{"text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.","lang":"eng"}],"user_id":"15278","publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"quality_controlled":"1","author":[{"first_name":"Marius","full_name":"Meyer, Marius","last_name":"Meyer","id":"40778"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"date_created":"2021-04-16T10:17:22Z","status":"public"},{"language":[{"iso":"eng"}],"type":"preprint","year":"2020","citation":{"mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020.","short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020)."},"date_updated":"2022-06-28T07:27:19Z","_id":"32242","department":[{"_id":"27"}],"publication":"arXiv:2011.00813","author":[{"last_name":"Bengs","full_name":"Bengs, Viktor","first_name":"Viktor"},{"full_name":"Hüllermeier, Eyke","first_name":"Eyke","last_name":"Hüllermeier"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2022-06-28T07:26:54Z","status":"public","abstract":[{"lang":"eng","text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms."}],"external_id":{"arxiv":["2011.00813"]},"user_id":"15278","title":"Multi-Armed Bandits with Censored Consumption of Resources"},{"project":[{"name":"HighPerMeshes","grant_number":"01|H16005","_id":"33"},{"_id":"32","grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","language":[{"iso":"eng"}],"doi":"10.1109/ICFPT47387.2019.00020","date_updated":"2022-01-06T06:52:26Z","status":"public","has_accepted_license":"1","date_created":"2020-01-09T12:54:48Z","file":[{"date_updated":"2020-01-09T12:53:57Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":250559,"file_id":"15479","creator":"plessl","access_level":"closed","file_name":"gorlani19_fpt.pdf","date_created":"2020-01-09T12:53:57Z"}],"publisher":"IEEE","author":[{"last_name":"Gorlani","id":"72045","first_name":"Paolo","full_name":"Gorlani, Paolo"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","file_date_updated":"2020-01-09T12:53:57Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","user_id":"3145","ddc":["004"],"abstract":[{"text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.","lang":"eng"}],"citation":{"bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.","short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019."},"type":"conference","year":"2019","_id":"15478","conference":{"name":"International Conference on Field-Programmable Technology (FPT)"}},{"language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-77398-8_8","date_updated":"2022-01-06T06:55:22Z","publication_status":"published","publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"editor":[{"first_name":"D.","full_name":"Klusáček, D.","last_name":"Klusáček"},{"last_name":"Cirne","first_name":"W.","full_name":"Cirne, W."},{"first_name":"N.","full_name":"Desai, N.","last_name":"Desai"}],"department":[{"_id":"27"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","page":"132-151","citation":{"bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }","mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8.","ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151."},"year":"2018","type":"conference","conference":{"location":"Orlando, FL, USA","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","start_date":"2017-06-02","end_date":"2017-06-02"},"_id":"22","intvolume":" 10773","volume":10773,"date_created":"2017-07-25T14:54:08Z","status":"public","keyword":["Scheduling Planning Mapping Workload management"],"publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","publisher":"Springer","author":[{"first_name":"Axel","full_name":"Keller, Axel","last_name":"Keller","id":"15274"}],"user_id":"15274","abstract":[{"text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation.","lang":"eng"}]},{"abstract":[{"lang":"eng","text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution."}],"user_id":"15278","publisher":"ACM","quality_controlled":"1","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"full_name":"Mohr, Stephan","first_name":"Stephan","last_name":"Mohr"},{"last_name":"Wiebeler","first_name":"Hendrik","full_name":"Wiebeler, Hendrik"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","status":"public","date_created":"2018-03-22T10:53:01Z","_id":"1590","conference":{"start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)","location":"Basel, Switzerland","end_date":"2018-07-04"},"year":"2018","citation":{"ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231"},"type":"conference","place":"New York, NY, USA","external_id":{"arxiv":["1710.10899"]},"title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"project":[{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_updated":"2023-09-26T11:48:12Z","doi":"10.1145/3218176.3218231","language":[{"iso":"eng"}]},{"_id":"1204","type":"conference","citation":{"ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534."},"year":"2018","user_id":"15278","ddc":["000"],"date_created":"2018-03-08T14:45:18Z","has_accepted_license":"1","status":"public","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-02T14:43:37Z","file_id":"5281","creator":"ups","file_size":447769,"access_level":"closed","date_created":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf"}],"file_date_updated":"2018-11-02T14:43:37Z","publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","keyword":["htrop"],"quality_controlled":"1","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"ACM","doi":"10.1145/3178487.3178534","date_updated":"2023-09-26T11:47:23Z","language":[{"iso":"eng"}],"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"publication_identifier":{"isbn":["9781450349826"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}]},{"conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"_id":"1588","type":"conference","year":"2018","citation":{"apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037."},"user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x."}],"date_created":"2018-03-22T10:48:01Z","status":"public","has_accepted_license":"1","file":[{"file_size":269130,"file_id":"5282","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T14:45:05Z","relation":"main_file","success":1,"date_created":"2018-11-02T14:45:05Z","file_name":"08457652.pdf","access_level":"closed"}],"file_date_updated":"2018-11-02T14:45:05Z","keyword":["tet_topic_hpc"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Mahale","full_name":"Mahale, Gopinath","first_name":"Gopinath"},{"first_name":"Samer","full_name":"Alhaddad, Samer","last_name":"Alhaddad","id":"42456"},{"full_name":"Grynko, Yevgen","first_name":"Yevgen","id":"26059","last_name":"Grynko"},{"last_name":"Schmitt","full_name":"Schmitt, Christian","first_name":"Christian"},{"first_name":"Ayesha","full_name":"Afzal, Ayesha","last_name":"Afzal"},{"first_name":"Frank","full_name":"Hannig, Frank","last_name":"Hannig"},{"first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","doi":"10.1109/FCCM.2018.00037","date_updated":"2023-09-26T11:47:52Z","language":[{"iso":"eng"}],"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","project":[{"name":"HighPerMeshes","grant_number":"01|H16005A","_id":"33"},{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}]},{"doi":"10.23919/FPL.2017.8056844","date_updated":"2023-09-26T13:24:38Z","language":[{"iso":"eng"}],"title":"Flexible FPGA design for FDTD using OpenCL","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"},{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005A"},{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"_id":"1592","citation":{"ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844","apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844"},"type":"conference","year":"2017","ddc":["000"],"user_id":"15278","abstract":[{"text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2018-03-22T11:10:23Z","publisher":"IEEE","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","first_name":"Jens","id":"158","last_name":"Förstner"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","file_date_updated":"2018-11-02T15:02:28Z","keyword":["tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"file_name":"08056844.pdf","date_created":"2018-11-02T15:02:28Z","access_level":"closed","file_size":230235,"creator":"ups","file_id":"5291","date_updated":"2018-11-02T15:02:28Z","content_type":"application/pdf","relation":"main_file","success":1}]},{"abstract":[{"lang":"eng","text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments."}],"title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","user_id":"24135","publication":"Proc. 41st Conference on Local Computer Networks (LCN)","department":[{"_id":"27"},{"_id":"518"}],"keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"author":[{"last_name":"Lass","id":"24135","first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael"},{"first_name":"Dominik","full_name":"Leibenger, Dominik","last_name":"Leibenger"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"publisher":"IEEE","publication_status":"published","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"date_created":"2017-07-25T14:36:16Z","status":"public","date_updated":"2022-01-06T06:53:56Z","_id":"19","doi":"10.1109/lcn.2016.11","type":"conference","year":"2016","citation":{"ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016.","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11."},"language":[{"iso":"eng"}]},{"_id":"24","date_updated":"2023-09-26T13:26:17Z","language":[{"iso":"eng"}],"year":"2016","type":"conference","citation":{"ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016."},"user_id":"15278","title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","ddc":["004"],"file":[{"access_level":"closed","date_created":"2018-11-14T12:38:45Z","file_name":"paper_26.pdf","date_updated":"2018-11-14T12:38:45Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":129552,"file_id":"5602","creator":"kenter"}],"author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","publication":"Proc. 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Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87","apa":"Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87","chicago":"Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.","ieee":"M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641.","short":"M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641."},"type":"conference","year":"2016"},{"file":[{"access_level":"closed","date_created":"2018-03-21T12:39:46Z","file_name":"171-plessl16_fpl_wrc.pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T12:39:46Z","content_type":"application/pdf","creator":"florida","file_id":"1538","file_size":54421}],"publication":"Workshop on Reconfigurable Computing (WRC)","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2017-10-17T12:41:25Z","status":"public","has_accepted_license":"1","user_id":"15278","title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"],"language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016."},"year":"2016","date_updated":"2023-09-26T13:27:21Z","_id":"171"},{"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:24Z","file":[{"access_level":"closed","file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z","success":1,"relation":"main_file","date_updated":"2018-03-21T12:41:55Z","content_type":"application/pdf","file_id":"1541","creator":"florida","file_size":261356}],"author":[{"full_name":"Lösch, Achim","first_name":"Achim","id":"43646","last_name":"Lösch"},{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","publisher":"EDA Consortium / IEEE","file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","_id":"168","citation":{"ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917."},"type":"conference","year":"2016","page":"912-917","title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}]},{"title":"Using Approximate Computing in Scientific Codes","user_id":"15278","author":[{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"id":"49079","last_name":"Kühne","full_name":"Kühne, Thomas","first_name":"Thomas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","publication":"Workshop on Approximate Computing (AC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"status":"public","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2017-07-26T15:02:20Z","date_updated":"2023-09-26T13:25:17Z","_id":"25","citation":{"mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC).","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.","short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016."},"year":"2016","type":"conference","language":[{"iso":"eng"}]},{"_id":"31","date_updated":"2023-09-26T13:25:59Z","language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }"},"user_id":"15278","ddc":["040"],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","file":[{"success":1,"relation":"main_file","date_updated":"2019-01-11T11:56:55Z","content_type":"application/pdf","creator":"deffel","file_id":"6626","file_size":394563,"access_level":"closed","file_name":"wrc_upb_polimi_final.pdf","date_created":"2019-01-11T11:56:55Z"}],"publication":"Proc. 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G.","last_name":"Trainiti"},{"last_name":"Durelli","full_name":"Durelli, Gianluca C.","first_name":"Gianluca C."},{"full_name":"Bolchini, Cristiana","first_name":"Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2017-07-26T15:16:31Z","has_accepted_license":"1","status":"public"},{"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","language":[{"iso":"eng"}],"doi":"10.1109/RTSI.2016.7740545","date_updated":"2023-09-26T13:28:11Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:18Z","file":[{"access_level":"closed","date_created":"2018-03-21T13:01:09Z","file_name":"138-07740545.pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T13:01:09Z","content_type":"application/pdf","creator":"florida","file_id":"1560","file_size":184334}],"author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Ettore M. G. ","full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti"},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"first_name":"Emanuele","full_name":"Del Sozzo, Emanuele","last_name":"Del Sozzo"},{"first_name":"Marco D. ","full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio"},{"last_name":"Bolchini","first_name":"Christina","full_name":"Bolchini, Christina"}],"publisher":"IEEE","quality_controlled":"1","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","file_date_updated":"2018-03-21T13:01:09Z","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"citation":{"ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545."},"year":"2016","type":"conference","page":"1-5","_id":"138"},{"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement."}],"date_created":"2017-10-17T12:41:51Z","status":"public","has_accepted_license":"1","file":[{"access_level":"open_access","date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","relation":"main_file","content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","creator":"florida","file_id":"1442","file_size":1176620}],"file_date_updated":"2019-08-01T09:10:44Z","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","_id":"303","type":"conference","citation":{"bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015."},"year":"2015","title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]},"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","language":[{"iso":"eng"}]},{"user_id":"15278","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"ACM","author":[{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"first_name":"J.","full_name":"T. Anderson, J.","last_name":"T. Anderson"},{"last_name":"Borga","full_name":"Borga, A.","first_name":"A."},{"last_name":"Boterenbrood","first_name":"H.","full_name":"Boterenbrood, H."},{"last_name":"Chen","first_name":"H.","full_name":"Chen, H."},{"first_name":"K.","full_name":"Chen, K.","last_name":"Chen"},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"full_name":"Francis, D.","first_name":"D.","last_name":"Francis"},{"first_name":"B.","full_name":"Gorini, B.","last_name":"Gorini"},{"last_name":"Lanni","full_name":"Lanni, F.","first_name":"F."},{"last_name":"Lehmann-Miotto","first_name":"Giovanna","full_name":"Lehmann-Miotto, Giovanna"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"first_name":"J.","full_name":"Narevicius, J.","last_name":"Narevicius"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"A.","full_name":"Roich, A.","last_name":"Roich"},{"full_name":"Ryu, S.","first_name":"S.","last_name":"Ryu"},{"last_name":"P. Schreuder","first_name":"F.","full_name":"P. Schreuder, F."},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"first_name":"J.","full_name":"Vermeulen, J.","last_name":"Vermeulen"},{"first_name":"J.","full_name":"Zhang, J.","last_name":"Zhang"}],"date_created":"2018-03-23T14:09:33Z","status":"public","_id":"1773","date_updated":"2023-09-26T13:31:01Z","doi":"10.1145/2675743.2771824","language":[{"iso":"eng"}],"citation":{"ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824."},"year":"2015","type":"conference"},{"page":"1078-1083","type":"conference","year":"2015","citation":{"bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083."},"_id":"238","date_created":"2017-10-17T12:41:38Z","status":"public","has_accepted_license":"1","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","file_date_updated":"2018-03-21T10:29:49Z","quality_controlled":"1","publisher":"EDA Consortium / IEEE","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"file":[{"file_id":"1500","creator":"florida","file_size":380552,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T10:29:49Z","date_created":"2018-03-21T10:29:49Z","file_name":"238-plessl15_date.pdf","access_level":"closed"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.7873/DATE.2015.1124","date_updated":"2023-09-26T13:31:44Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi"},{"file":[{"file_id":"1353","creator":"florida","file_size":557362,"success":1,"relation":"main_file","date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:29:52Z","publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"date_created":"2017-10-17T12:42:17Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"user_id":"15278","ddc":["040"],"page":"1-8","year":"2014","type":"conference","citation":{"bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"_id":"439","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509"},{"_id":"406","page":"1-8","type":"conference","citation":{"bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"year":"2014","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"user_id":"15278","ddc":["040"],"file":[{"file_id":"1366","creator":"florida","file_size":932852,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","date_created":"2018-03-16T11:37:42Z","access_level":"closed"}],"file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","date_created":"2017-10-17T12:42:11Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:36:40Z","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}]},{"page":"233-243","citation":{"bibtex":"@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }","mla":"Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.","chicago":"Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.","ama":"Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19","apa":"Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19","ieee":"T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.","short":"T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243."},"year":"2014","type":"conference","_id":"1781","date_updated":"2022-01-06T06:53:20Z","doi":"10.1007/978-3-319-09063-4_19","publication":"Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)","department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"publisher":"Springer International Publishing","author":[{"last_name":"Steinle","full_name":"Steinle, Tobias","first_name":"Tobias"},{"last_name":"Vrabec","full_name":"Vrabec, Jadran","first_name":"Jadran"},{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"}],"publication_identifier":{"isbn":["978-3-319-09063-4"]},"editor":[{"last_name":"Bock","full_name":"Bock, Hans Georg","first_name":"Hans Georg"},{"full_name":"Hoang, Xuan Phu","first_name":"Xuan Phu","last_name":"Hoang"},{"last_name":"Rannacher","full_name":"Rannacher, Rolf","first_name":"Rolf"},{"last_name":"Schlöder","full_name":"Schlöder, Johannes P.","first_name":"Johannes P."}],"date_created":"2018-03-26T13:47:16Z","status":"public","abstract":[{"text":"In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment.","lang":"eng"}],"title":"Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres","user_id":"24135"},{"year":"2014","citation":{"short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2."},"type":"conference","page":"14-25","series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-09165-5_2","issue":"8427","_id":"1782","date_updated":"2022-01-06T06:53:20Z","status":"public","date_created":"2018-03-26T13:50:37Z","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"last_name":"Schaefers","first_name":"Lars","full_name":"Schaefers, Lars"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer","publication":"Proc. Conf. on Computers and Games (CG)","department":[{"_id":"27"},{"_id":"78"}],"title":"On Semeai Detection in Monte-Carlo Go","user_id":"24135","place":"Switzerland"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","file":[{"date_created":"2018-03-20T07:02:02Z","file_name":"388-plessl14_arc.pdf","access_level":"closed","creator":"florida","file_id":"1387","file_size":330193,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-20T07:02:02Z"}],"publisher":"Springer International Publishing","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","file_date_updated":"2018-03-20T07:02:02Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:07Z","volume":8405,"abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"user_id":"15278","ddc":["040"],"citation":{"short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }"},"type":"conference","year":"2014","page":"144-155","intvolume":" 8405","_id":"388"},{"page":"222-229","citation":{"ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67."},"type":"conference","year":"2014","_id":"377","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z","creator":"florida","file_id":"1397","file_size":1003907,"access_level":"closed","file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z"}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","keyword":["coldboot"],"file_date_updated":"2018-03-20T07:14:20Z","publisher":"IEEE","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:05Z","has_accepted_license":"1","status":"public","abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:33:50Z","doi":"10.1109/FCCM.2014.67","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs"},{"language":[{"iso":"eng"}],"page":"142-149","type":"conference","citation":{"chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27."},"year":"2014","_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"C. Durelli, Gianluca","first_name":"Gianluca","last_name":"C. Durelli"},{"last_name":"Pogliani","full_name":"Pogliani, Marcello","first_name":"Marcello"},{"first_name":"Antonio","full_name":"Miele, Antonio","last_name":"Miele"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"quality_controlled":"1","publisher":"IEEE","project":[{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2018-03-26T13:40:14Z","status":"public","user_id":"15278","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach"},{"doi":"10.1007/978-3-319-05960-0_38","_id":"1780","date_updated":"2023-09-26T13:36:20Z","type":"conference","citation":{"mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014."},"year":"2014","language":[{"iso":"eng"}],"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","status":"public","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2018-03-26T13:45:35Z","quality_controlled":"1","publisher":"Springer","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"first_name":"Marcello","full_name":"Copolla, Marcello","last_name":"Copolla"},{"last_name":"Djafarian","full_name":"Djafarian, Karim","first_name":"Karim"},{"full_name":"Koranaros, George","first_name":"George","last_name":"Koranaros"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"last_name":"Paolino","full_name":"Paolino, Michele","first_name":"Michele"},{"first_name":"Oliver","full_name":"Pell, Oliver","last_name":"Pell"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)"},{"title":"Distributing Storage in Cloud Environments","user_id":"24135","publisher":"IEEE","author":[{"full_name":"Berenbrink, Petra","first_name":"Petra","last_name":"Berenbrink"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Friedetzky","first_name":"Tom","full_name":"Friedetzky, Tom"},{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Nagel","full_name":"Nagel, Lars","first_name":"Lars"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","status":"public","date_created":"2018-03-26T14:52:56Z","_id":"1788","date_updated":"2022-01-06T06:53:22Z","doi":"10.1109/IPDPSW.2013.148","year":"2013","citation":{"ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.","mla":"Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148."},"type":"conference"},{"title":"File Recipe Compression in Data Deduplication Systems","user_id":"24135","status":"public","date_created":"2018-03-26T15:16:03Z","author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"}],"publisher":"USENIX Association","department":[{"_id":"27"}],"publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","_id":"1793","date_updated":"2022-01-06T06:53:23Z","year":"2013","type":"conference","citation":{"short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82."},"page":"175-182"},{"doi":"10.1109/SIU.2013.6531530","_id":"1786","date_updated":"2022-01-06T06:53:20Z","citation":{"ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.","short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530."},"type":"conference","year":"2013","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","user_id":"24135","date_created":"2018-03-26T14:48:53Z","status":"public","publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","department":[{"_id":"27"},{"_id":"78"}],"author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"full_name":"Redif, Soydan","first_name":"Soydan","last_name":"Redif"}],"publisher":"IEEE"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","page":"386-389","year":"2013","type":"conference","citation":{"chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394."},"_id":"528","keyword":["coldboot"],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2018-03-15T10:36:08Z","author":[{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Sorge, Christoph","first_name":"Christoph","last_name":"Sorge"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","file":[{"file_size":822680,"creator":"florida","file_id":"1294","content_type":"application/pdf","date_updated":"2018-03-15T10:36:08Z","success":1,"relation":"main_file","file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z","access_level":"closed"}],"date_created":"2017-10-17T12:42:35Z","has_accepted_license":"1","status":"public","abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"ddc":["040"],"user_id":"15278"},{"place":"Washington DC, USA","user_id":"24135","title":"MCD: Overcoming the Data Download Bottleneck in Data Centers","author":[{"last_name":"Kaiser","first_name":"Jürgen","full_name":"Kaiser, Jürgen"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"last_name":"Gottfried","first_name":"Viktor","full_name":"Gottfried, Viktor"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publisher":"IEEE Computer Society","publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-26T14:43:38Z","_id":"1784","date_updated":"2022-01-06T06:53:20Z","doi":"10.1109/NAS.2013.18","year":"2013","type":"conference","citation":{"ieee":"J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2013, pp. 88–97.","short":"J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97.","mla":"Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.","bibtex":"@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers}, DOI={10.1109/NAS.2013.18}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }","chicago":"Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.","ama":"Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97. doi:10.1109/NAS.2013.18","apa":"Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/NAS.2013.18"},"page":"88-97"},{"file_date_updated":"2018-03-15T13:38:56Z","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Kling","full_name":"Kling, Peter","first_name":"Peter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","id":"15523"}],"quality_controlled":"1","publisher":"IEEE","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","success":1,"relation":"main_file","file_size":1040834,"file_id":"1308","creator":"florida","access_level":"closed","date_created":"2018-03-15T13:38:56Z","file_name":"505-Plessl13_seus.pdf"}],"date_created":"2017-10-17T12:42:30Z","status":"public","has_accepted_license":"1","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"ddc":["040"],"user_id":"15278","citation":{"short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232."},"type":"conference","year":"2013","_id":"505","department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:38:20Z","doi":"10.1109/ISORC.2013.6913232"},{"title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"date_created":"2018-03-26T14:51:05Z","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"status":"public","publication":"Proc. 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IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136."},"type":"conference","language":[{"iso":"eng"}]},{"date_created":"2018-03-29T15:06:46Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. UNICORE Summit","author":[{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"first_name":"Sebastian","full_name":"Breuers, Sebastian","last_name":"Breuers"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"first_name":"Sandra","full_name":"Gesing, Sandra","last_name":"Gesing"},{"first_name":"Sonja","full_name":"Herres-Pawlis, Sonja","last_name":"Herres-Pawlis"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"full_name":"Kruse, Martin","first_name":"Martin","last_name":"Kruse"},{"first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph","last_name":"Müller-Pfefferkorn"},{"last_name":"Schäfer","first_name":"Patrick","full_name":"Schäfer, Patrick"},{"first_name":"Bernd","full_name":"Schuller, Bernd","last_name":"Schuller"},{"last_name":"Steinke","full_name":"Steinke, Thomas","first_name":"Thomas"},{"last_name":"Zink","full_name":"Zink, Andreas","first_name":"Andreas"}],"user_id":"24135","title":"A Data Driven Science Gateway for Computational Workflows","year":"2012","citation":{"ieee":"R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.","short":"R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.","bibtex":"@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }","mla":"Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012.","chicago":"Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012.","ama":"Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.","apa":"Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit."},"type":"conference","date_updated":"2022-01-06T06:54:44Z","_id":"2107"},{"volume":"PoS(EGICF12-EMITC2)050","date_created":"2018-04-03T09:15:35Z","status":"public","department":[{"_id":"27"}],"publication":"Proceedings of Science","author":[{"last_name":"Gesing","full_name":"Gesing, Sandra","first_name":"Sandra"},{"last_name":"Herres-Pawlis","full_name":"Herres-Pawlis, Sonja","first_name":"Sonja"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"first_name":"Peter","full_name":"Kacsuk, Peter","last_name":"Kacsuk"},{"first_name":"Oliver","full_name":"Kohlbacher, Oliver","last_name":"Kohlbacher"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"first_name":"Patrick","full_name":"Schäfer, Patrick","last_name":"Schäfer"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"}],"title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","user_id":"24135","citation":{"chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050).","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.","ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050."},"type":"conference","year":"2012","date_updated":"2022-01-06T06:55:13Z","_id":"2178"},{"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Supercomputing (SC)","author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Kaiser","first_name":"Jürgen","full_name":"Kaiser, Jürgen"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"full_name":"Kuhn, Michael","first_name":"Michael","last_name":"Kuhn"},{"last_name":"Kunkel","first_name":"Julian","full_name":"Kunkel, Julian"},{"full_name":"Cortes, Toni","first_name":"Toni","last_name":"Cortes"}],"publisher":"IEEE Computer Society","date_created":"2018-03-29T14:41:55Z","status":"public","place":"Los Alamitos, CA, USA","title":"A Study on Data Deduplication in HPC Storage Systems","user_id":"24135","page":"7:1-7:11","year":"2012","type":"conference","citation":{"mla":"Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14.","bibtex":"@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }","apa":"Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14","ama":"Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14","chicago":"Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.","ieee":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11.","short":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11."},"date_updated":"2022-01-06T06:54:42Z","_id":"2099","doi":"10.1109/SC.2012.14"},{"user_id":"24135","title":"Comparison of Bayesian Move Prediction Systems for Computer Go","date_created":"2018-03-29T14:59:35Z","status":"public","publication":"Proc. IEEE Conf. on Computational Intelligence and Games (CIG)","department":[{"_id":"27"},{"_id":"78"}],"publisher":"IEEE","author":[{"first_name":"Martin","full_name":"Wistuba, Martin","last_name":"Wistuba"},{"last_name":"Schaefers","full_name":"Schaefers, Lars","first_name":"Lars"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"doi":"10.1109/CIG.2012.6374143","date_updated":"2022-01-06T06:54:42Z","_id":"2103","page":"91-99","citation":{"ieee":"M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.","short":"M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.","bibtex":"@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }","mla":"Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.","chicago":"Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.","apa":"Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143","ama":"Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143"},"year":"2012","type":"conference"},{"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z","language":[{"iso":"eng"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"type":"conference","citation":{"ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370."},"year":"2012","page":"189-196","user_id":"15278","ddc":["000"],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"has_accepted_license":"1","status":"public","date_created":"2018-03-29T15:04:25Z","file":[{"date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":2148787,"creator":"fossie","file_id":"7638","access_level":"closed","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","date_created":"2019-02-13T09:04:46Z"}],"publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"}],"file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)"},{"status":"public","date_created":"2018-03-26T15:12:01Z","publisher":"IEEE","author":[{"first_name":"Jürgen","full_name":"Kaiser, Jürgen","last_name":"Kaiser"},{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Effert","full_name":"Effert, Sascha","first_name":"Sascha"}],"department":[{"_id":"27"}],"publication":"Proc. Symp. on Mass Storage Systems and Technologies (MSST)","user_id":"24135","title":"Design of an exact data deduplication cluster","type":"conference","year":"2012","citation":{"mla":"Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12, doi:10.1109/MSST.2012.6232380.","bibtex":"@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha}, year={2012}, pages={1–12} }","apa":"Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380","ama":"Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380","chicago":"Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380.","ieee":"J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2012, pp. 1–12.","short":"J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12."},"page":"1-12","doi":"10.1109/MSST.2012.6232380","date_updated":"2022-01-06T06:53:22Z","_id":"1789"},{"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","year":"2012","citation":{"ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745."},"type":"conference","page":"1-8","_id":"615","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"file_date_updated":"2018-03-15T06:48:32Z","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"access_level":"closed","date_created":"2018-03-15T06:48:32Z","file_name":"615-ReConFig12_01.pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T06:48:32Z","content_type":"application/pdf","file_id":"1246","creator":"florida","file_size":730144}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}]},{"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","department":[{"_id":"27"}],"publisher":"IEEE","author":[{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Hartung","first_name":"Tim","full_name":"Hartung, Tim"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"date_created":"2018-03-29T14:40:04Z","status":"public","title":"ESB: Ext2 Split Block Device","user_id":"24135","page":"181-188","year":"2012","citation":{"short":"J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.","ieee":"J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.","chicago":"Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.","ama":"Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34","apa":"Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34","mla":"Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.","bibtex":"@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }"},"type":"conference","date_updated":"2022-01-06T06:54:42Z","_id":"2098","doi":"10.1109/ICPADS.2012.34"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","year":"2012","citation":{"short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"type":"conference","page":"559-562","_id":"612","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z","creator":"florida","file_id":"1247","file_size":202923,"access_level":"closed","file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z"}],"author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2018-03-15T06:49:03Z","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:51Z","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"user_id":"15278","ddc":["040"]},{"status":"public","date_created":"2018-03-29T14:43:18Z","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"full_name":"Redif, Soydan","first_name":"Soydan","last_name":"Redif"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","user_id":"24135","title":"FPGA implementation of a second-order convolutive blind signal separation algorithm","type":"conference","year":"2012","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.","short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012."},"date_updated":"2022-01-06T06:54:42Z","_id":"2100"},{"date_updated":"2022-01-06T06:54:42Z","_id":"2097","doi":"10.1109/FPT.2012.6412125","page":"135-140","year":"2012","type":"conference","citation":{"ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140."},"title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","publisher":"IEEE Computer Society","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"date_created":"2018-03-29T14:34:48Z","status":"public"},{"type":"conference","citation":{"ieee":"T. Schlemmer et al., “Generic User Management for Science Gateways via Virtual Organizations,” in Proc. EGI Technical Forum, 2012.","short":"T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.","mla":"Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via Virtual Organizations.” Proc. EGI Technical Forum, 2012.","bibtex":"@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012, title={Generic User Management for Science Gateways via Virtual Organizations}, booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke, Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn, Ralph and Kohlbacher, Oliver}, year={2012} }","chicago":"Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer, Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum, 2012.","apa":"Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn, R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways via Virtual Organizations. In Proc. EGI Technical Forum.","ama":"Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012."},"year":"2012","date_updated":"2022-01-06T06:54:42Z","_id":"2104","status":"public","date_created":"2018-03-29T15:00:48Z","author":[{"first_name":"Tobias","full_name":"Schlemmer, Tobias","last_name":"Schlemmer"},{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"last_name":"Kohlbacher","full_name":"Kohlbacher, Oliver","first_name":"Oliver"}],"department":[{"_id":"27"}],"publication":"Proc. EGI Technical Forum","title":"Generic User Management for Science Gateways via Virtual Organizations","user_id":"24135"},{"_id":"609","page":"8-9","type":"conference","citation":{"apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9."},"year":"2012","ddc":["040"],"user_id":"15278","abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"date_created":"2017-10-17T12:42:50Z","has_accepted_license":"1","status":"public","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file_date_updated":"2018-03-15T08:14:17Z","quality_controlled":"1","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"file":[{"access_level":"closed","date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z","creator":"florida","file_id":"1249","file_size":146789}],"date_updated":"2023-09-26T13:41:36Z","language":[{"iso":"eng"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"title":"One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services","user_id":"24135","author":[{"first_name":"Giuseppe","full_name":"Congiu, Giuseppe","last_name":"Congiu"},{"last_name":"Grawinkel","first_name":"Matthias","full_name":"Grawinkel, Matthias"},{"full_name":"Narasimhamurthy, Sai","first_name":"Sai","last_name":"Narasimhamurthy"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publisher":"IEEE","publication":"Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-29T15:02:15Z","date_updated":"2022-01-06T06:54:42Z","_id":"2105","doi":"10.1109/ClusterW.2012.16","year":"2012","citation":{"short":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24.","ieee":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,” in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 2012, pp. 16–24.","chicago":"Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.","apa":"Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012). One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16","ama":"Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS). IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16","mla":"Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24, doi:10.1109/ClusterW.2012.16.","bibtex":"@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services}, DOI={10.1109/ClusterW.2012.16}, booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }"},"type":"conference","page":"16-24"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","language":[{"iso":"eng"}],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-15T08:33:18Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"}],"publisher":"IEEE","quality_controlled":"1","file":[{"file_id":"1257","creator":"florida","file_size":371235,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","date_created":"2018-03-15T08:33:18Z","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed"}],"date_created":"2017-10-17T12:42:47Z","has_accepted_license":"1","status":"public","_id":"591","page":"1-8","type":"conference","citation":{"chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773."},"year":"2012"},{"project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"date_created":"2018-04-03T09:18:33Z","status":"public","keyword":["funding-enhance"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"quality_controlled":"1","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","user_id":"15278","citation":{"ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012."},"type":"conference","year":"2012","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:40:17Z","_id":"2180"},{"title":"The MoSGrid Community From National to International Scale","user_id":"24135","status":"public","date_created":"2018-04-03T09:01:19Z","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"first_name":"Sonja","full_name":"Herres-Pawlis, Sonja","last_name":"Herres-Pawlis"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"full_name":"Kacsuk, Peter","first_name":"Peter","last_name":"Kacsuk"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"},{"first_name":"Miklos","full_name":"Kozlovszky, Miklos","last_name":"Kozlovszky"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"full_name":"Schäfer, Patrick","first_name":"Patrick","last_name":"Schäfer"},{"full_name":"Steinke, Thomas","first_name":"Thomas","last_name":"Steinke"}],"department":[{"_id":"27"}],"publication":"Proc. EGI Community Forum","date_updated":"2022-01-06T06:55:11Z","_id":"2171","citation":{"mla":"Gesing, Sandra, et al. “The MoSGrid Community From National to International Scale.” Proc. EGI Community Forum, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={The MoSGrid Community From National to International Scale}, booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International Scale. In Proc. EGI Community Forum.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From National to International Scale. In: Proc. EGI Community Forum. ; 2012.","chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community From National to International Scale.” In Proc. EGI Community Forum, 2012.","ieee":"S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012.","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012."},"type":"conference","year":"2012"},{"title":"Towards Dynamic Scripted pNFS Layouts","user_id":"24135","status":"public","date_created":"2018-03-29T14:44:24Z","publisher":"IEEE","author":[{"first_name":"Matthias","full_name":"Grawinkel, Matthias","last_name":"Grawinkel"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"first_name":"Georg","full_name":"Best, Georg","last_name":"Best"},{"first_name":"Ivan","full_name":"Popov, Ivan","last_name":"Popov"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"publication":"Proc. Parallel Data Storage Workshop (PDSW)","department":[{"_id":"27"}],"doi":"10.1109/SC.Companion.2012.13","date_updated":"2022-01-06T06:54:42Z","_id":"2101","type":"conference","year":"2012","citation":{"bibtex":"@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13}, booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel, Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012}, pages={13–17} }","mla":"Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13.","apa":"Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW) (pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13","ama":"Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17. doi:10.1109/SC.Companion.2012.13","chicago":"Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann. “Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop (PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13.","ieee":"M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW), 2012, pp. 13–17.","short":"M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17."},"page":"13-17"},{"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided."}],"user_id":"15278","ddc":["040"],"file":[{"file_size":288508,"creator":"florida","file_id":"1275","date_updated":"2018-03-15T10:20:24Z","content_type":"application/pdf","success":1,"relation":"main_file","date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","access_level":"closed"}],"author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"full_name":"Carreras, Carlos","first_name":"Carlos","last_name":"Carreras"},{"last_name":"Sierra","first_name":"Roberto","full_name":"Sierra, Roberto"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2018-03-15T10:20:24Z","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:42Z","_id":"567","type":"conference","citation":{"ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973."},"year":"2012","page":"559-565"},{"user_id":"24135","title":"A Science Gateway for Molecular Simulations","publication":"Proc. EGI User Forum","department":[{"_id":"27"}],"author":[{"last_name":"Gesing","full_name":"Gesing, Sandra","first_name":"Sandra"},{"full_name":"Kacsuk, Peter","first_name":"Peter","last_name":"Kacsuk"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"first_name":"Sebastian","full_name":"Breuers, Sebastian","last_name":"Breuers"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"full_name":"Fels, Gregor","first_name":"Gregor","last_name":"Fels"},{"last_name":"Grunzke","full_name":"Grunzke, Richard","first_name":"Richard"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"first_name":"Lars","full_name":"Packschies, Lars","last_name":"Packschies"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"},{"full_name":"Szikszay Fabri, Anna","first_name":"Anna","last_name":"Szikszay Fabri"},{"full_name":"Warzecha, Klaus-Dieter","first_name":"Klaus-Dieter","last_name":"Warzecha"},{"first_name":"Martin","full_name":"Wewior, Martin","last_name":"Wewior"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"}],"date_created":"2018-04-03T15:07:11Z","status":"public","_id":"2199","date_updated":"2022-01-06T06:55:22Z","page":"94-95","citation":{"short":"S. Gesing, P. Kacsuk, M. Kozlovszky, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, R. Grunzke, S. Herres-Pawlis, J. Krüger, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, A. Szikszay Fabri, K.-D. Warzecha, M. Wewior, O. Kohlbacher, in: Proc. EGI User Forum, 2011, pp. 94–95.","ieee":"S. Gesing et al., “A Science Gateway for Molecular Simulations,” in Proc. EGI User Forum, 2011, pp. 94–95.","chicago":"Gesing, Sandra, Peter Kacsuk, Miklos Kozlovszky, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “A Science Gateway for Molecular Simulations.” In Proc. EGI User Forum, 94–95, 2011.","apa":"Gesing, S., Kacsuk, P., Kozlovszky, M., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). A Science Gateway for Molecular Simulations. In Proc. EGI User Forum (pp. 94–95).","ama":"Gesing S, Kacsuk P, Kozlovszky M, et al. A Science Gateway for Molecular Simulations. In: Proc. EGI User Forum. ; 2011:94-95.","bibtex":"@inproceedings{Gesing_Kacsuk_Kozlovszky_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Grunzke_Herres-Pawlis_et al._2011, title={A Science Gateway for Molecular Simulations}, booktitle={Proc. EGI User Forum}, author={Gesing, Sandra and Kacsuk, Peter and Kozlovszky, Miklos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Grunzke, Richard and Herres-Pawlis, Sonja and et al.}, year={2011}, pages={94–95} }","mla":"Gesing, Sandra, et al. “A Science Gateway for Molecular Simulations.” Proc. EGI User Forum, 2011, pp. 94–95."},"type":"conference","year":"2011"},{"status":"public","date_created":"2018-03-29T11:23:22Z","publication_status":"published","author":[{"full_name":"Niehörster, Oliver","first_name":"Oliver","last_name":"Niehörster"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publication":"Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","department":[{"_id":"27"}],"user_id":"15274","title":"An Energy-Aware SaaS Stack","abstract":[{"text":"We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds.","lang":"eng"}],"language":[{"iso":"eng"}],"year":"2011","citation":{"mla":"Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.","bibtex":"@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. 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Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","short":"O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011."},"type":"conference","doi":"10.1109/MASCOTS.2011.52","_id":"1972","date_updated":"2022-01-06T06:54:10Z"},{"date_updated":"2022-01-06T06:55:19Z","_id":"2190","doi":"10.1109/CloudCom.2011.28","year":"2011","type":"conference","citation":{"ieee":"O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed Configuration Effects,” in Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 2011, pp. 138–145.","short":"O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA, 2011, pp. 138–145.","mla":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.","bibtex":"@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }","chicago":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.","ama":"Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145. doi:10.1109/CloudCom.2011.28","apa":"Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) (pp. 138–145). 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Krieger, “Autonomic Resource Management with Support Vector Machines,” in Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 2011, pp. 157–164.","ama":"Niehörster O, Simon J, Brinkmann A, Krieger A. Autonomic Resource Management with Support Vector Machines. In: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID). Washington, DC, USA: IEEE Computer Society; 2011:157-164. doi:10.1109/Grid.2011.28","apa":"Niehörster, O., Simon, J., Brinkmann, A., & Krieger, A. (2011). Autonomic Resource Management with Support Vector Machines. In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) (pp. 157–164). Washington, DC, USA: IEEE Computer Society. https://doi.org/10.1109/Grid.2011.28","chicago":"Niehörster, Oliver, Jens Simon, André Brinkmann, and Alexaner Krieger. “Autonomic Resource Management with Support Vector Machines.” In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 157–64. Washington, DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/Grid.2011.28.","bibtex":"@inproceedings{Niehörster_Simon_Brinkmann_Krieger_2011, place={Washington, DC, USA}, title={Autonomic Resource Management with Support Vector Machines}, DOI={10.1109/Grid.2011.28}, booktitle={Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Krieger, Alexaner}, year={2011}, pages={157–164} }","mla":"Niehörster, Oliver, et al. “Autonomic Resource Management with Support Vector Machines.” Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, 2011, pp. 157–64, doi:10.1109/Grid.2011.28."},"type":"conference","place":"Washington, DC, USA","title":"Autonomic Resource Management with Support Vector Machines","user_id":"24135","department":[{"_id":"27"}],"publication":"Proc. IEEE/ACM Int. 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IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273."},"year":"2011","user_id":"15278","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","date_created":"2018-04-03T14:37:14Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","publication":"Proc. Int. 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(2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011."}},{"title":"Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability","user_id":"24135","date_created":"2018-04-03T15:01:31Z","status":"public","publication":"Proc. Int. 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Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, publisher={IEEE Computer Society}, author={Grawinkel, Matthias and Schäfer, Thorsten and Brinkmann, André and Hagemeyer, Jens and Porrmann, Mario}, year={2011}, pages={297–306} }","mla":"Grawinkel, Matthias, et al. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306, doi:10.1109/mascots.2011.13.","apa":"Grawinkel, M., Schäfer, T., Brinkmann, A., Hagemeyer, J., & Porrmann, M. (2011). Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) (pp. 297–306). IEEE Computer Society. https://doi.org/10.1109/mascots.2011.13","ama":"Grawinkel M, Schäfer T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society; 2011:297-306. doi:10.1109/mascots.2011.13","chicago":"Grawinkel, Matthias, Thorsten Schäfer, André Brinkmann, Jens Hagemeyer, and Mario Porrmann. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 297–306. IEEE Computer Society, 2011. https://doi.org/10.1109/mascots.2011.13.","ieee":"M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, and M. Porrmann, “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability,” in Proc. Int. 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Workshop on Scientific Gateways (IWSG), 2011.","chicago":"Gesing, Sandra, Richard Grunzke, Ákos Balaskó, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA, 2011.","apa":"Gesing, S., Grunzke, R., Balaskó, Á., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). Granular Security for a Science Gateway in Structural Bioinformatics. In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA.","ama":"Gesing S, Grunzke R, Balaskó Á, et al. Granular Security for a Science Gateway in Structural Bioinformatics. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2011.","bibtex":"@inproceedings{Gesing_Grunzke_Balaskó_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Herres-Pawlis_Kacsuk_et al._2011, title={Granular Security for a Science Gateway in Structural Bioinformatics}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Grunzke, Richard and Balaskó, Ákos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Herres-Pawlis, Sonja and Kacsuk, Peter and et al.}, year={2011} }","mla":"Gesing, Sandra, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011."},"type":"conference","year":"2011","title":"Granular Security for a Science Gateway in Structural Bioinformatics","user_id":"24135","department":[{"_id":"27"}],"publication":"Proc. Int. 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Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }"},"language":[{"iso":"eng"}],"title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","user_id":"15278","publication":"Proc. Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"full_name":"Grad, Mariusz","first_name":"Mariusz","last_name":"Grad"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"date_created":"2018-04-03T15:05:52Z","status":"public"},{"title":"Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System","user_id":"24135","status":"public","date_created":"2018-04-03T14:32:23Z","author":[{"last_name":"Grawinkel","full_name":"Grawinkel, Matthias","first_name":"Matthias"},{"full_name":"Pargmann, Markus","first_name":"Markus","last_name":"Pargmann"},{"last_name":"Dömer","full_name":"Dömer, Hubert","first_name":"Hubert"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publisher":"IEEE","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","doi":"10.1109/ICPADS.2011.77","_id":"2189","date_updated":"2022-01-06T06:55:18Z","type":"conference","citation":{"short":"M. Grawinkel, M. Pargmann, H. Dömer, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–387.","ieee":"M. Grawinkel, M. Pargmann, H. Dömer, and A. Brinkmann, “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2011, pp. 380–387.","chicago":"Grawinkel, Matthias, Markus Pargmann, Hubert Dömer, and André Brinkmann. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 380–87. IEEE, 2011. https://doi.org/10.1109/ICPADS.2011.77.","apa":"Grawinkel, M., Pargmann, M., Dömer, H., & Brinkmann, A. (2011). Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 380–387). IEEE. https://doi.org/10.1109/ICPADS.2011.77","ama":"Grawinkel M, Pargmann M, Dömer H, Brinkmann A. Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77","mla":"Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77.","bibtex":"@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }"},"year":"2011","page":"380-387"},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:59Z","quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-14T13:49:39Z","file":[{"file_size":502244,"file_id":"1220","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-14T13:49:39Z","relation":"main_file","success":1,"file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z","access_level":"closed"}],"_id":"656","citation":{"mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60."},"year":"2011","type":"conference","page":"55-60","title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2011.59","date_updated":"2023-09-26T13:46:08Z","language":[{"iso":"eng"}]},{"date_updated":"2022-01-06T06:55:23Z","_id":"2205","intvolume":" 829","citation":{"chicago":"Birkenheuer, Georg, Dirk Blunk, Sebastian Breuers, André Brinkmann, Gregor Fels, Sandra Gesing, Richard Grunzke, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” In Proc. of Grid Workflow Workshop (GWW), Vol. 829. CEUR Workshop Proceedings, 2011.","apa":"Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Fels, G., Gesing, S., … Wewior, M. (2011). MoSGrid: Progress of Workflow driven Chemical Simulations. In Proc. of Grid Workflow Workshop (GWW) (Vol. 829).","ama":"Birkenheuer G, Blunk D, Breuers S, et al. MoSGrid: Progress of Workflow driven Chemical Simulations. In: Proc. of Grid Workflow Workshop (GWW). Vol 829. CEUR Workshop Proceedings. ; 2011.","mla":"Birkenheuer, Georg, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” Proc. of Grid Workflow Workshop (GWW), vol. 829, 2011.","bibtex":"@inproceedings{Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Gesing_Grunzke_Herres-Pawlis_Kohlbacher_Krüger_et al._2011, series={CEUR Workshop Proceedings}, title={MoSGrid: Progress of Workflow driven Chemical Simulations}, volume={829}, booktitle={Proc. of Grid Workflow Workshop (GWW)}, author={Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Gesing, Sandra and Grunzke, Richard and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and et al.}, year={2011}, collection={CEUR Workshop Proceedings} }","short":"G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Gesing, R. Grunzke, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, U. Lang, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, J. Schuster, T. Steinke, K.-D. Warzecha, M. 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Berlin / Heidelberg: Springer, 2011. https://doi.org/10.1007/978-3-642-23397-5_36.","bibtex":"@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={10.1007/978-3-642-23397-5_36}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36.","short":"T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.","ieee":"T. Graf, U. Lorenz, M. Platzner, and L. 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It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. 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Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344."},"type":"conference","page":"338-344"},{"type":"conference","citation":{"short":"A. Höing, G. Scherp, S. Gudenkauf, D. Meister, A. Brinkmann, in: Proc. Int. Conf. on Service Oriented Computing (ICSOC), Springer, Berlin / Heidelberg, 2009, pp. 301–315.","ieee":"A. Höing, G. Scherp, S. Gudenkauf, D. Meister, and A. Brinkmann, “An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL,” in Proc. Int. Conf. on Service Oriented Computing (ICSOC), 2009, vol. 5900, pp. 301–315.","apa":"Höing, A., Scherp, G., Gudenkauf, S., Meister, D., & Brinkmann, A. (2009). An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL. In Proc. Int. Conf. on Service Oriented Computing (ICSOC) (Vol. 5900, pp. 301–315). Berlin / Heidelberg: Springer. https://doi.org/0.1007/978-3-642-10383-4_20","ama":"Höing A, Scherp G, Gudenkauf S, Meister D, Brinkmann A. An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL. In: Proc. Int. Conf. on Service Oriented Computing (ICSOC). Vol 5900. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2009:301-315. doi:0.1007/978-3-642-10383-4_20","chicago":"Höing, Andre, Guido Scherp, Stefan Gudenkauf, Dirk Meister, and André Brinkmann. “An Orchestration as a Service Infrastructure Using Grid Technologies and WS-BPEL.” In Proc. Int. Conf. on Service Oriented Computing (ICSOC), 5900:301–15. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2009. https://doi.org/0.1007/978-3-642-10383-4_20.","mla":"Höing, Andre, et al. “An Orchestration as a Service Infrastructure Using Grid Technologies and WS-BPEL.” Proc. Int. Conf. on Service Oriented Computing (ICSOC), vol. 5900, Springer, 2009, pp. 301–15, doi:0.1007/978-3-642-10383-4_20.","bibtex":"@inproceedings{Höing_Scherp_Gudenkauf_Meister_Brinkmann_2009, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL}, volume={5900}, DOI={0.1007/978-3-642-10383-4_20}, booktitle={Proc. Int. Conf. on Service Oriented Computing (ICSOC)}, publisher={Springer}, author={Höing, Andre and Scherp, Guido and Gudenkauf, Stefan and Meister, Dirk and Brinkmann, André}, year={2009}, pages={301–315}, collection={Lecture Notes in Computer Science (LNCS)} }"},"year":"2009","page":"301-315","series_title":"Lecture Notes in Computer Science (LNCS)","doi":"0.1007/978-3-642-10383-4_20","intvolume":" 5900","_id":"2239","date_updated":"2022-01-06T06:55:32Z","status":"public","date_created":"2018-04-05T17:14:00Z","volume":5900,"author":[{"last_name":"Höing","full_name":"Höing, Andre","first_name":"Andre"},{"last_name":"Scherp","full_name":"Scherp, Guido","first_name":"Guido"},{"last_name":"Gudenkauf","full_name":"Gudenkauf, Stefan","first_name":"Stefan"},{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"Springer","department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Service Oriented Computing (ICSOC)","user_id":"24135","title":"An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL","place":"Berlin / Heidelberg"},{"place":"Los Alamitos, CA, USA","user_id":"15278","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","publisher":"IEEE Computer Society","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","keyword":["IMORC","graphics"],"status":"public","date_created":"2018-04-05T17:11:28Z","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"_id":"2238","date_updated":"2023-09-26T13:52:32Z","doi":"10.1109/ReConFig.2009.32","language":[{"iso":"eng"}],"citation":{"ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32"},"type":"conference","year":"2009","page":"119-124"},{"department":[{"_id":"27"}],"publication":"Proc. Cracow Grid Workshop (CGW)","author":[{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Carlson, Arthur","first_name":"Arthur","last_name":"Carlson"},{"full_name":"Fölling, Alexander","first_name":"Alexander","last_name":"Fölling"},{"last_name":"Högqvist","first_name":"Mikael","full_name":"Högqvist, Mikael"},{"full_name":"Hoheisel, Andreas","first_name":"Andreas","last_name":"Hoheisel"},{"full_name":"Papaspyrou, Alexander","first_name":"Alexander","last_name":"Papaspyrou"},{"last_name":"Rieger","first_name":"Klaus","full_name":"Rieger, Klaus"},{"full_name":"Schott, Bernhard","first_name":"Bernhard","last_name":"Schott"},{"full_name":"Ziegler, Wolfgang","first_name":"Wolfgang","last_name":"Ziegler"}],"date_created":"2018-04-06T15:14:46Z","status":"public","publication_identifier":{"isbn":["978-83-61433-01-9"]},"user_id":"24135","title":"Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!","page":"96-103","type":"conference","year":"2009","citation":{"ieee":"G. Birkenheuer et al., “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!,” in Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","short":"G. Birkenheuer, A. Carlson, A. Fölling, M. Högqvist, A. Hoheisel, A. Papaspyrou, K. Rieger, B. Schott, W. Ziegler, in: Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","bibtex":"@inproceedings{Birkenheuer_Carlson_Fölling_Högqvist_Hoheisel_Papaspyrou_Rieger_Schott_Ziegler_2009, title={Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!}, booktitle={Proc. Cracow Grid Workshop (CGW)}, author={Birkenheuer, Georg and Carlson, Arthur and Fölling, Alexander and Högqvist, Mikael and Hoheisel, Andreas and Papaspyrou, Alexander and Rieger, Klaus and Schott, Bernhard and Ziegler, Wolfgang}, year={2009}, pages={96–103} }","mla":"Birkenheuer, Georg, et al. “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!” Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","chicago":"Birkenheuer, Georg, Arthur Carlson, Alexander Fölling, Mikael Högqvist, Andreas Hoheisel, Alexander Papaspyrou, Klaus Rieger, Bernhard Schott, and Wolfgang Ziegler. “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!” In Proc. Cracow Grid Workshop (CGW), 96–103, 2009.","ama":"Birkenheuer G, Carlson A, Fölling A, et al. Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In: Proc. Cracow Grid Workshop (CGW). ; 2009:96-103.","apa":"Birkenheuer, G., Carlson, A., Fölling, A., Högqvist, M., Hoheisel, A., Papaspyrou, A., … Ziegler, W. (2009). Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In Proc. Cracow Grid Workshop (CGW) (pp. 96–103)."},"_id":"2260","date_updated":"2022-01-06T06:55:37Z"},{"language":[{"iso":"eng"}],"citation":{"short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18."},"year":"2009","type":"conference","page":"11-18","date_updated":"2023-09-26T13:53:11Z","_id":"2262","status":"public","date_created":"2018-04-06T15:18:24Z","publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"first_name":"Paul","full_name":"Kaufmann, Paul","last_name":"Kaufmann"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","keyword":["EvoCache","evolvable hardware","computer architecture"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","place":"Los Alamitos, CA, USA","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}]},{"page":"275-278","year":"2009","citation":{"bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278."},"type":"conference","_id":"2350","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","publisher":"IEEE Computer Society","author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","date_created":"2018-04-16T15:05:52Z","status":"public","abstract":[{"lang":"eng","text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. "}],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:51:44Z","doi":"10.1109/FCCM.2009.25","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]},"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing"}]