[{"year":"2021","citation":{"chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116."},"type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/ipdps49936.2021.00116","date_updated":"2023-07-28T12:05:15Z","_id":"46195","publication_status":"published","date_created":"2023-07-28T12:04:27Z","status":"public","publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Martin","full_name":"Karp, Martin","last_name":"Karp"},{"last_name":"Podobas","full_name":"Podobas, Artur","first_name":"Artur"},{"last_name":"Jansson","first_name":"Niclas","full_name":"Jansson, Niclas"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Philipp","full_name":"Schlatter, Philipp","last_name":"Schlatter"},{"full_name":"Markidis, Stefano","first_name":"Stefano","last_name":"Markidis"}],"title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","user_id":"3145"},{"status":"public","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2022-02-21T14:26:37Z","publication_status":"published","author":[{"full_name":"Karp, Martin","first_name":"Martin","last_name":"Karp"},{"first_name":"Artur","full_name":"Podobas, Artur","last_name":"Podobas"},{"last_name":"Jansson","full_name":"Jansson, Niclas","first_name":"Niclas"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Schlatter","full_name":"Schlatter, Philipp","first_name":"Philipp"},{"last_name":"Markidis","first_name":"Stefano","full_name":"Markidis, Stefano"}],"quality_controlled":"1","publisher":"IEEE","publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116."},"year":"2021","doi":"10.1109/ipdps49936.2021.00116","_id":"29937","date_updated":"2024-01-22T09:59:13Z"},{"author":[{"full_name":"Bengs, Viktor","first_name":"Viktor","last_name":"Bengs"},{"last_name":"Hüllermeier","first_name":"Eyke","full_name":"Hüllermeier, Eyke"}],"publication":"arXiv:2011.00813","department":[{"_id":"27"}],"status":"public","date_created":"2022-06-28T07:26:54Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"external_id":{"arxiv":["2011.00813"]},"abstract":[{"lang":"eng","text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms."}],"user_id":"15278","title":"Multi-Armed Bandits with Censored Consumption of Resources","language":[{"iso":"eng"}],"type":"preprint","year":"2020","citation":{"mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020.","short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020)."},"_id":"32242","date_updated":"2022-06-28T07:27:19Z"},{"page":"1127-1140","type":"conference","citation":{"ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.","bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084."},"year":"2020","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"conference":{"name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","location":"Atlanta, GA, US"},"_id":"16898","date_created":"2020-04-28T14:44:21Z","status":"public","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"id":"75963","last_name":"Schade","full_name":"Schade, Robert","orcid":"0000-0002-6268-539","first_name":"Robert"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"user_id":"75963","abstract":[{"text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/SC41405.2020.00084","date_updated":"2023-08-02T14:55:59Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","external_id":{"arxiv":["2004.10811"]},"place":"Los Alamitos, CA, USA"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:42:53Z","doi":"10.1109/h2rc51942.2020.00007","department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["9781665415927"]},"publication_status":"published","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","related_material":{"link":[{"relation":"supplementary_material","description":"Official repository of the benchmark suite on GitHub","url":"https://github.com/pc2/HPCC_FPGA"}]},"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"type":"conference","citation":{"mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020."},"year":"2020","_id":"21632","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","quality_controlled":"1","author":[{"full_name":"Meyer, Marius","first_name":"Marius","id":"40778","last_name":"Meyer"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"date_created":"2021-04-16T10:17:22Z","status":"public","abstract":[{"text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.","lang":"eng"}],"user_id":"15278"},{"date_updated":"2022-01-06T06:52:26Z","doi":"10.1109/ICFPT47387.2019.00020","language":[{"iso":"eng"}],"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"33","name":"HighPerMeshes","grant_number":"01|H16005"},{"grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"}],"_id":"15478","conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"citation":{"apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019."},"year":"2019","type":"conference","abstract":[{"text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.","lang":"eng"}],"user_id":"3145","ddc":["004"],"file":[{"relation":"main_file","success":1,"date_updated":"2020-01-09T12:53:57Z","content_type":"application/pdf","creator":"plessl","file_id":"15479","file_size":250559,"access_level":"closed","date_created":"2020-01-09T12:53:57Z","file_name":"gorlani19_fpt.pdf"}],"publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Paolo","full_name":"Gorlani, Paolo","last_name":"Gorlani","id":"72045"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2020-01-09T12:53:57Z","has_accepted_license":"1","status":"public","date_created":"2020-01-09T12:54:48Z"},{"date_updated":"2022-01-06T06:55:22Z","doi":"10.1007/978-3-319-77398-8_8","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","department":[{"_id":"27"}],"editor":[{"last_name":"Klusáček","first_name":"D.","full_name":"Klusáček, D."},{"last_name":"Cirne","first_name":"W.","full_name":"Cirne, W."},{"full_name":"Desai, N.","first_name":"N.","last_name":"Desai"}],"publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"publication_status":"published","_id":"22","intvolume":" 10773","conference":{"end_date":"2017-06-02","location":"Orlando, FL, USA","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","start_date":"2017-06-02"},"year":"2018","citation":{"ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.","mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8."},"type":"conference","page":"132-151","abstract":[{"lang":"eng","text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation."}],"user_id":"15274","author":[{"first_name":"Axel","full_name":"Keller, Axel","last_name":"Keller","id":"15274"}],"publisher":"Springer","keyword":["Scheduling Planning Mapping Workload management"],"publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","volume":10773,"status":"public","date_created":"2017-07-25T14:54:08Z"},{"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037","language":[{"iso":"eng"}],"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"_id":"33","grant_number":"01|H16005A","name":"HighPerMeshes"},{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"_id":"1588","year":"2018","type":"conference","citation":{"ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037"},"abstract":[{"text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.","lang":"eng"}],"user_id":"15278","ddc":["000"],"file":[{"access_level":"closed","file_name":"08457652.pdf","date_created":"2018-11-02T14:45:05Z","date_updated":"2018-11-02T14:45:05Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":269130,"creator":"ups","file_id":"5282"}],"keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T14:45:05Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Gopinath","full_name":"Mahale, Gopinath","last_name":"Mahale"},{"full_name":"Alhaddad, Samer","first_name":"Samer","id":"42456","last_name":"Alhaddad"},{"full_name":"Grynko, Yevgen","first_name":"Yevgen","id":"26059","last_name":"Grynko"},{"full_name":"Schmitt, Christian","first_name":"Christian","last_name":"Schmitt"},{"full_name":"Afzal, Ayesha","first_name":"Ayesha","last_name":"Afzal"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"last_name":"Förstner","id":"158","first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"date_created":"2018-03-22T10:48:01Z","status":"public","has_accepted_license":"1"},{"doi":"10.1145/3218176.3218231","date_updated":"2023-09-26T11:48:12Z","language":[{"iso":"eng"}],"title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","external_id":{"arxiv":["1710.10899"]},"place":"New York, NY, USA","publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"project":[{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"conference":{"end_date":"2018-07-04","location":"Basel, Switzerland","start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)"},"_id":"1590","citation":{"short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231."},"year":"2018","type":"conference","user_id":"15278","abstract":[{"text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.","lang":"eng"}],"date_created":"2018-03-22T10:53:01Z","status":"public","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","publisher":"ACM","author":[{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"last_name":"Mohr","full_name":"Mohr, Stephan","first_name":"Stephan"},{"last_name":"Wiebeler","first_name":"Hendrik","full_name":"Wiebeler, Hendrik"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1"},{"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"}],"publication_identifier":{"isbn":["9781450349826"]},"publication_status":"published","date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534","language":[{"iso":"eng"}],"user_id":"15278","ddc":["000"],"file":[{"access_level":"closed","date_created":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf","success":1,"relation":"main_file","date_updated":"2018-11-02T14:43:37Z","content_type":"application/pdf","file_id":"5281","creator":"ups","file_size":447769}],"file_date_updated":"2018-11-02T14:43:37Z","keyword":["htrop"],"publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publisher":"ACM","date_created":"2018-03-08T14:45:18Z","has_accepted_license":"1","status":"public","_id":"1204","type":"conference","year":"2018","citation":{"apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534."}},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"},{"_id":"33","grant_number":"01|H16005A","name":"HighPerMeshes"},{"_id":"32","grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"title":"Flexible FPGA design for FDTD using OpenCL","year":"2017","citation":{"bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844","apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.","ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017."},"type":"conference","_id":"1592","file":[{"access_level":"closed","date_created":"2018-11-02T15:02:28Z","file_name":"08056844.pdf","content_type":"application/pdf","date_updated":"2018-11-02T15:02:28Z","success":1,"relation":"main_file","file_size":230235,"creator":"ups","file_id":"5291"}],"keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T15:02:28Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"158","last_name":"Förstner","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"IEEE","quality_controlled":"1","date_created":"2018-03-22T11:10:23Z","has_accepted_license":"1","status":"public","abstract":[{"lang":"eng","text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures."}],"user_id":"15278","ddc":["000"]},{"publication_identifier":{"issn":["2212-0173"]},"volume":22,"date_created":"2017-07-26T15:25:33Z","status":"public","publication":"Progress in Industrial Mathematics at ECMI","department":[{"_id":"27"},{"_id":"101"}],"author":[{"first_name":"Michael","full_name":"Dellnitz, Michael","last_name":"Dellnitz"},{"full_name":"Eckstein, Julian","first_name":"Julian","last_name":"Eckstein"},{"last_name":"Flaßkamp","full_name":"Flaßkamp, Kathrin","first_name":"Kathrin"},{"first_name":"Patrick","full_name":"Friedel, Patrick","last_name":"Friedel"},{"first_name":"Christian","full_name":"Horenkamp, Christian","last_name":"Horenkamp"},{"last_name":"Köhler","full_name":"Köhler, Ulrich","first_name":"Ulrich"},{"last_name":"Ober-Blöbaum","first_name":"Sina","full_name":"Ober-Blöbaum, Sina"},{"last_name":"Peitz","first_name":"Sebastian","full_name":"Peitz, Sebastian"},{"last_name":"Tiemeyer","full_name":"Tiemeyer, Sebastian","first_name":"Sebastian"}],"publisher":"Springer International Publishing","title":"Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control","user_id":"24135","place":"Cham","page":"633-641","year":"2016","type":"conference","citation":{"short":"M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.","ieee":"M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641.","ama":"Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87","apa":"Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87","chicago":"Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.","bibtex":"@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }","mla":"Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87."},"series_title":"Mathematics in Industry","doi":"10.1007/978-3-319-23413-7_87","_id":"34","date_updated":"2022-01-06T06:59:14Z","intvolume":" 22"},{"status":"public","date_created":"2017-07-25T14:36:16Z","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"publication_status":"published","author":[{"id":"24135","last_name":"Lass","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","first_name":"Michael"},{"last_name":"Leibenger","full_name":"Leibenger, Dominik","first_name":"Dominik"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"publisher":"IEEE","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. 41st Conference on Local Computer Networks (LCN)","keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"user_id":"24135","title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","abstract":[{"lang":"eng","text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments."}],"language":[{"iso":"eng"}],"year":"2016","type":"conference","citation":{"bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11.","ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016.","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016."},"doi":"10.1109/lcn.2016.11","_id":"19","date_updated":"2022-01-06T06:53:56Z"},{"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","ddc":["040"],"user_id":"15278","date_created":"2017-07-26T15:16:31Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"has_accepted_license":"1","status":"public","file_date_updated":"2019-01-11T11:56:55Z","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","author":[{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Trainiti","first_name":"Ettore M. G.","full_name":"Trainiti, Ettore M. G."},{"last_name":"Durelli","full_name":"Durelli, Gianluca C.","first_name":"Gianluca C."},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"quality_controlled":"1","file":[{"access_level":"closed","date_created":"2019-01-11T11:56:55Z","file_name":"wrc_upb_polimi_final.pdf","content_type":"application/pdf","date_updated":"2019-01-11T11:56:55Z","relation":"main_file","success":1,"file_size":394563,"creator":"deffel","file_id":"6626"}],"date_updated":"2023-09-26T13:25:59Z","_id":"31","type":"conference","year":"2016","citation":{"ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016."},"language":[{"iso":"eng"}]},{"date_updated":"2023-09-26T13:26:17Z","_id":"24","language":[{"iso":"eng"}],"type":"conference","year":"2016","citation":{"ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016."},"user_id":"15278","ddc":["004"],"title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","status":"public","has_accepted_license":"1","date_created":"2017-07-26T15:00:43Z","project":[{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"}],"file":[{"file_name":"paper_26.pdf","date_created":"2018-11-14T12:38:45Z","access_level":"closed","creator":"kenter","file_id":"5602","file_size":129552,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-11-14T12:38:45Z"}],"quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"file_date_updated":"2018-11-14T12:38:45Z","publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","department":[{"_id":"27"},{"_id":"518"}]},{"year":"2016","type":"conference","citation":{"ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.","short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }","mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC)."},"language":[{"iso":"eng"}],"_id":"25","date_updated":"2023-09-26T13:25:17Z","status":"public","date_created":"2017-07-26T15:02:20Z","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"publication":"Workshop on Approximate Computing (AC)","title":"Using Approximate Computing in Scientific Codes","user_id":"15278"},{"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_updated":"2023-09-26T13:28:11Z","doi":"10.1109/RTSI.2016.7740545","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads."}],"user_id":"15278","ddc":["040"],"file":[{"success":1,"relation":"main_file","date_updated":"2018-03-21T13:01:09Z","content_type":"application/pdf","file_id":"1560","creator":"florida","file_size":184334,"access_level":"closed","file_name":"138-07740545.pdf","date_created":"2018-03-21T13:01:09Z"}],"quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Trainiti","first_name":"Ettore M. G. ","full_name":"Trainiti, Ettore M. G. "},{"first_name":"Gianluca C.","full_name":"Durelli, Gianluca C.","last_name":"Durelli"},{"last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele","first_name":"Emanuele"},{"last_name":"Santambrogio","first_name":"Marco D. ","full_name":"Santambrogio, Marco D. "},{"first_name":"Christina","full_name":"Bolchini, Christina","last_name":"Bolchini"}],"file_date_updated":"2018-03-21T13:01:09Z","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:18Z","_id":"138","type":"conference","year":"2016","citation":{"mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5."},"page":"1-5"},{"abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"date_created":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","access_level":"closed","file_size":261356,"creator":"florida","file_id":"1541","content_type":"application/pdf","date_updated":"2018-03-21T12:41:55Z","success":1,"relation":"main_file"}],"publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","file_date_updated":"2018-03-21T12:41:55Z","quality_controlled":"1","publisher":"EDA Consortium / IEEE","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","_id":"168","page":"912-917","type":"conference","citation":{"bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016.","ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917."},"year":"2016","title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}]},{"date_updated":"2023-09-26T13:27:21Z","_id":"171","type":"conference","citation":{"bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016."},"year":"2016","language":[{"iso":"eng"}],"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"],"user_id":"15278","date_created":"2017-10-17T12:41:25Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"status":"public","has_accepted_license":"1","department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","publication":"Workshop on Reconfigurable Computing (WRC)","quality_controlled":"1","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file":[{"creator":"florida","file_id":"1538","file_size":54421,"success":1,"relation":"main_file","date_updated":"2018-03-21T12:39:46Z","content_type":"application/pdf","file_name":"171-plessl16_fpl_wrc.pdf","date_created":"2018-03-21T12:39:46Z","access_level":"closed"}]},{"year":"2015","citation":{"short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }"},"type":"conference","_id":"303","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:41:51Z","file":[{"content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file","file_size":1176620,"creator":"florida","file_id":"1442","access_level":"open_access","file_name":"303-plessl15_adapt.pdf","date_created":"2018-03-20T07:46:46Z"}],"author":[{"full_name":"Damschen, Marvin","first_name":"Marvin","last_name":"Damschen"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","file_date_updated":"2019-08-01T09:10:44Z","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","user_id":"15278","ddc":["040"],"abstract":[{"text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.","lang":"eng"}],"language":[{"iso":"eng"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]}}]