[{"publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"date_created":"2018-04-03T14:37:14Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","user_id":"15278","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","language":[{"iso":"eng"}],"page":"223-226","type":"conference","year":"2011","citation":{"mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226."},"date_updated":"2023-09-26T13:43:48Z","_id":"2193","doi":"10.1109/ASAP.2011.6043273"},{"date_updated":"2023-09-26T13:46:08Z","doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"_id":"656","citation":{"chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59."},"year":"2011","type":"conference","page":"55-60","abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"ddc":["040"],"user_id":"15278","quality_controlled":"1","author":[{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","file_date_updated":"2018-03-14T13:49:39Z","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file":[{"file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z","access_level":"closed","file_size":502244,"file_id":"1220","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-14T13:49:39Z","relation":"main_file","success":1}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:59Z"},{"title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","user_id":"15278","place":"New York, NY, USA","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"status":"public","date_created":"2018-04-03T15:08:13Z","quality_controlled":"1","publisher":"ACM","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"doi":"10.1145/1950413.1950448","_id":"2200","date_updated":"2023-09-26T13:45:04Z","type":"conference","year":"2011","citation":{"short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }"},"page":"177-180","language":[{"iso":"eng"}]},{"language":[{"iso":"eng"}],"page":"278-285","citation":{"apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153."},"type":"conference","year":"2011","doi":"10.1109/IPDPS.2011.153","date_updated":"2023-09-26T13:44:39Z","_id":"2198","date_created":"2018-04-03T15:05:52Z","status":"public","publication":"Proc. Reconfigurable Architectures Workshop (RAW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"publisher":"IEEE Computer Society","user_id":"15278","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture"},{"place":"Berlin / Heidelberg","title":"SkewCCC+: A Heterogeneous Distributed Hash Table","user_id":"24135","author":[{"first_name":"Marcin","full_name":"Bienkowski, Marcin","last_name":"Bienkowski"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"full_name":"Klonowski, Marek","first_name":"Marek","last_name":"Klonowski"},{"first_name":"Miroslaw","full_name":"Korzeniowski, Miroslaw","last_name":"Korzeniowski"}],"publisher":"Springer","department":[{"_id":"27"}],"publication":"Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)","volume":6490,"status":"public","date_created":"2018-04-05T14:49:51Z","date_updated":"2022-01-06T06:55:28Z","_id":"2217","intvolume":" 6490","doi":"10.1007/978-3-642-17653-1_18","series_title":"Lecture Notes in Computer Science (LNCS)","type":"conference","citation":{"short":"M. Bienkowski, A. Brinkmann, M. Klonowski, M. Korzeniowski, in: Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), Springer, Berlin / Heidelberg, 2010.","ieee":"M. Bienkowski, A. Brinkmann, M. Klonowski, and M. Korzeniowski, “SkewCCC+: A Heterogeneous Distributed Hash Table,” in Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), 2010, vol. 6490.","apa":"Bienkowski, M., Brinkmann, A., Klonowski, M., & Korzeniowski, M. (2010). SkewCCC+: A Heterogeneous Distributed Hash Table. In Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) (Vol. 6490). Berlin / Heidelberg: Springer. https://doi.org/10.1007/978-3-642-17653-1_18","ama":"Bienkowski M, Brinkmann A, Klonowski M, Korzeniowski M. SkewCCC+: A Heterogeneous Distributed Hash Table. In: Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis). Vol 6490. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2010. doi:10.1007/978-3-642-17653-1_18","chicago":"Bienkowski, Marcin, André Brinkmann, Marek Klonowski, and Miroslaw Korzeniowski. “SkewCCC+: A Heterogeneous Distributed Hash Table.” In Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), Vol. 6490. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2010. https://doi.org/10.1007/978-3-642-17653-1_18.","mla":"Bienkowski, Marcin, et al. “SkewCCC+: A Heterogeneous Distributed Hash Table.” Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), vol. 6490, Springer, 2010, doi:10.1007/978-3-642-17653-1_18.","bibtex":"@inproceedings{Bienkowski_Brinkmann_Klonowski_Korzeniowski_2010, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={SkewCCC+: A Heterogeneous Distributed Hash Table}, volume={6490}, DOI={10.1007/978-3-642-17653-1_18}, booktitle={Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)}, publisher={Springer}, author={Bienkowski, Marcin and Brinkmann, André and Klonowski, Marek and Korzeniowski, Miroslaw}, year={2010}, collection={Lecture Notes in Computer Science (LNCS)} }"},"year":"2010"},{"date_created":"2018-04-05T14:53:40Z","status":"public","publication":"Proc. Int. Workshop on Scientific Gateways (IWSG)","department":[{"_id":"27"}],"publisher":"Consorzio COMETA","author":[{"full_name":"Wewior, Martin","first_name":"Martin","last_name":"Wewior"},{"last_name":"Packschies","first_name":"Lars","full_name":"Packschies, Lars"},{"full_name":"Blunk, Dirk","first_name":"Dirk","last_name":"Blunk"},{"last_name":"Wickeroth","full_name":"Wickeroth, Daniel","first_name":"Daniel"},{"last_name":"Warzecha","first_name":"Klaus-Dieter","full_name":"Warzecha, Klaus-Dieter"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"first_name":"Sandra","full_name":"Gesing, Sandra","last_name":"Gesing"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Lang","first_name":"Ulrich","full_name":"Lang, Ulrich"}],"user_id":"24135","title":"The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations","page":"39-43","year":"2010","type":"conference","citation":{"mla":"Wewior, Martin, et al. “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43.","bibtex":"@inproceedings{Wewior_Packschies_Blunk_Wickeroth_Warzecha_Herres-Pawlis_Gesing_Breuers_Krüger_Birkenheuer_et al._2010, title={The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Wewior, Martin and Packschies, Lars and Blunk, Dirk and Wickeroth, Daniel and Warzecha, Klaus-Dieter and Herres-Pawlis, Sonja and Gesing, Sandra and Breuers, Sebastian and Krüger, Jens and Birkenheuer, Georg and et al.}, year={2010}, pages={39–43} }","apa":"Wewior, M., Packschies, L., Blunk, D., Wickeroth, D., Warzecha, K.-D., Herres-Pawlis, S., … Lang, U. (2010). The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 39–43). Consorzio COMETA.","ama":"Wewior M, Packschies L, Blunk D, et al. The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2010:39-43.","chicago":"Wewior, Martin, Lars Packschies, Dirk Blunk, Daniel Wickeroth, Klaus-Dieter Warzecha, Sonja Herres-Pawlis, Sandra Gesing, et al. “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations.” In Proc. Int. Workshop on Scientific Gateways (IWSG), 39–43. Consorzio COMETA, 2010.","ieee":"M. Wewior et al., “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 39–43.","short":"M. Wewior, L. Packschies, D. Blunk, D. Wickeroth, K.-D. Warzecha, S. Herres-Pawlis, S. Gesing, S. Breuers, J. Krüger, G. Birkenheuer, U. Lang, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43."},"date_updated":"2022-01-06T06:55:28Z","_id":"2218"},{"page":"44-48","type":"conference","citation":{"chicago":"Gesing, Sandra, Istvan Marton, Georg Birkenheuer, Bernd Schuller, Richard Grunzke, Jens Krüger, Sebastian Breuers, et al. “Workflow Interoperability in a Grid Portal for Molecular Simulations.” In Proc. Int. Workshop on Scientific Gateways (IWSG), 44–48. Consorzio COMETA, 2010.","ama":"Gesing S, Marton I, Birkenheuer G, et al. Workflow Interoperability in a Grid Portal for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2010:44-48.","apa":"Gesing, S., Marton, I., Birkenheuer, G., Schuller, B., Grunzke, R., Krüger, J., … Kozlovszky, M. (2010). Workflow Interoperability in a Grid Portal for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 44–48). Consorzio COMETA.","mla":"Gesing, Sandra, et al. “Workflow Interoperability in a Grid Portal for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","bibtex":"@inproceedings{Gesing_Marton_Birkenheuer_Schuller_Grunzke_Krüger_Breuers_Blunk_Fels_Packschies_et al._2010, title={Workflow Interoperability in a Grid Portal for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Marton, Istvan and Birkenheuer, Georg and Schuller, Bernd and Grunzke, Richard and Krüger, Jens and Breuers, Sebastian and Blunk, Dirk and Fels, Gregor and Packschies, Lars and et al.}, year={2010}, pages={44–48} }","short":"S. Gesing, I. Marton, G. Birkenheuer, B. Schuller, R. Grunzke, J. Krüger, S. Breuers, D. Blunk, G. Fels, L. Packschies, A. Brinkmann, O. Kohlbacher, M. Kozlovszky, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","ieee":"S. Gesing et al., “Workflow Interoperability in a Grid Portal for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 44–48."},"year":"2010","_id":"2219","date_updated":"2022-01-06T06:55:28Z","department":[{"_id":"27"}],"publication":"Proc. Int. Workshop on Scientific Gateways (IWSG)","publisher":"Consorzio COMETA","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"full_name":"Marton, Istvan","first_name":"Istvan","last_name":"Marton"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"last_name":"Schuller","first_name":"Bernd","full_name":"Schuller, Bernd"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"first_name":"Sebastian","full_name":"Breuers, Sebastian","last_name":"Breuers"},{"full_name":"Blunk, Dirk","first_name":"Dirk","last_name":"Blunk"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"last_name":"Packschies","first_name":"Lars","full_name":"Packschies, Lars"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"last_name":"Kohlbacher","full_name":"Kohlbacher, Oliver","first_name":"Oliver"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"}],"date_created":"2018-04-05T14:55:48Z","status":"public","title":"Workflow Interoperability in a Grid Portal for Molecular Simulations","user_id":"24135"},{"doi":"10.1109/NAS.2010.11","date_updated":"2022-01-06T06:55:29Z","_id":"2225","page":"126-134","year":"2010","type":"conference","citation":{"bibtex":"@inproceedings{Gao_Meister_Brinkmann_2010, title={Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors}, DOI={10.1109/NAS.2010.11}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE}, author={Gao, Yan and Meister, Dirk and Brinkmann, André}, year={2010}, pages={126–134} }","mla":"Gao, Yan, et al. “Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2010, pp. 126–34, doi:10.1109/NAS.2010.11.","apa":"Gao, Y., Meister, D., & Brinkmann, A. (2010). Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 126–134). IEEE. https://doi.org/10.1109/NAS.2010.11","ama":"Gao Y, Meister D, Brinkmann A. Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). IEEE; 2010:126-134. doi:10.1109/NAS.2010.11","chicago":"Gao, Yan, Dirk Meister, and André Brinkmann. “Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 126–34. IEEE, 2010. https://doi.org/10.1109/NAS.2010.11.","ieee":"Y. Gao, D. Meister, and A. Brinkmann, “Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2010, pp. 126–134.","short":"Y. Gao, D. Meister, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2010, pp. 126–134."},"user_id":"24135","title":"Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors","date_created":"2018-04-05T16:37:26Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","author":[{"last_name":"Gao","first_name":"Yan","full_name":"Gao, Yan"},{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"IEEE"},{"doi":"10.1145/1810479.1810500","_id":"2229","date_updated":"2022-01-06T06:55:30Z","citation":{"mla":"Berenbrink, Petra, et al. “Balls into Bins with Related Random Choices.” Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, 2010, pp. 100–05, doi:10.1145/1810479.1810500.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Nagel_2010, place={New York}, title={Balls into Bins with Related Random Choices}, DOI={10.1145/1810479.1810500}, booktitle={Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA)}, publisher={ACM}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}, year={2010}, pages={100–105} }","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, and Lars Nagel. “Balls into Bins with Related Random Choices.” In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 100–105. New York: ACM, 2010. https://doi.org/10.1145/1810479.1810500.","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Nagel L. Balls into Bins with Related Random Choices. In: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA). New York: ACM; 2010:100-105. doi:10.1145/1810479.1810500","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., & Nagel, L. (2010). Balls into Bins with Related Random Choices. In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) (pp. 100–105). New York: ACM. https://doi.org/10.1145/1810479.1810500","ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, and L. Nagel, “Balls into Bins with Related Random Choices,” in Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 2010, pp. 100–105.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, New York, 2010, pp. 100–105."},"type":"conference","year":"2010","page":"100-105","user_id":"24135","title":"Balls into Bins with Related Random Choices","place":"New York","status":"public","date_created":"2018-04-05T16:45:55Z","author":[{"first_name":"Petra","full_name":"Berenbrink, Petra","last_name":"Berenbrink"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Friedetzky","first_name":"Tom","full_name":"Friedetzky, Tom"},{"first_name":"Lars","full_name":"Nagel, Lars","last_name":"Nagel"}],"publisher":"ACM","department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA)"},{"title":"dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)","user_id":"24135","place":"Washington, DC","status":"public","date_created":"2018-04-05T16:47:23Z","publisher":"IEEE Computer Society","author":[{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"department":[{"_id":"27"}],"publication":"Proc. Symp. on Mass Storage Systems and Technologies (MSST)","doi":"10.1109/MSST.2010.5496992","_id":"2230","date_updated":"2022-01-06T06:55:30Z","type":"conference","year":"2010","citation":{"chicago":"Meister, Dirk, and André Brinkmann. “Dedupv1: Improving Deduplication Throughput Using Solid State Drives (SSD).” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–6. Washington, DC: IEEE Computer Society, 2010. https://doi.org/10.1109/MSST.2010.5496992.","ama":"Meister D, Brinkmann A. dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD). In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). Washington, DC: IEEE Computer Society; 2010:1-6. doi:10.1109/MSST.2010.5496992","apa":"Meister, D., & Brinkmann, A. (2010). dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD). In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–6). Washington, DC: IEEE Computer Society. https://doi.org/10.1109/MSST.2010.5496992","mla":"Meister, Dirk, and André Brinkmann. “Dedupv1: Improving Deduplication Throughput Using Solid State Drives (SSD).” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE Computer Society, 2010, pp. 1–6, doi:10.1109/MSST.2010.5496992.","bibtex":"@inproceedings{Meister_Brinkmann_2010, place={Washington, DC}, title={dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)}, DOI={10.1109/MSST.2010.5496992}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Brinkmann, André}, year={2010}, pages={1–6} }","short":"D. Meister, A. Brinkmann, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE Computer Society, Washington, DC, 2010, pp. 1–6.","ieee":"D. Meister and A. Brinkmann, “dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD),” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2010, pp. 1–6."},"page":"1-6"},{"doi":"10.1109/SNAPI.2010.12","_id":"2231","date_updated":"2022-01-06T06:55:31Z","page":"33-42","type":"conference","year":"2010","citation":{"short":"P.H. Lensing, D. Meister, A. Brinkmann, in: Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI), IEEE, 2010, pp. 33–42.","ieee":"P. H. Lensing, D. Meister, and A. Brinkmann, “hashFS: Applying Hashing to Optimized File Systems for Small File Reads,” in Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI), 2010, pp. 33–42.","apa":"Lensing, P. H., Meister, D., & Brinkmann, A. (2010). hashFS: Applying Hashing to Optimized File Systems for Small File Reads. In Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI) (pp. 33–42). IEEE. https://doi.org/10.1109/SNAPI.2010.12","ama":"Lensing PH, Meister D, Brinkmann A. hashFS: Applying Hashing to Optimized File Systems for Small File Reads. In: Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI). IEEE; 2010:33-42. doi:10.1109/SNAPI.2010.12","chicago":"Lensing, Paul Hermann, Dirk Meister, and André Brinkmann. “HashFS: Applying Hashing to Optimized File Systems for Small File Reads.” In Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI), 33–42. IEEE, 2010. https://doi.org/10.1109/SNAPI.2010.12.","bibtex":"@inproceedings{Lensing_Meister_Brinkmann_2010, title={hashFS: Applying Hashing to Optimized File Systems for Small File Reads}, DOI={10.1109/SNAPI.2010.12}, booktitle={Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI)}, publisher={IEEE}, author={Lensing, Paul Hermann and Meister, Dirk and Brinkmann, André}, year={2010}, pages={33–42} }","mla":"Lensing, Paul Hermann, et al. “HashFS: Applying Hashing to Optimized File Systems for Small File Reads.” Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI), IEEE, 2010, pp. 33–42, doi:10.1109/SNAPI.2010.12."},"user_id":"24135","title":"hashFS: Applying Hashing to Optimized File Systems for Small File Reads","date_created":"2018-04-05T16:48:01Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI)","publisher":"IEEE","author":[{"last_name":"Lensing","full_name":"Lensing, Paul Hermann","first_name":"Paul Hermann"},{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}]},{"status":"public","date_created":"2018-04-05T16:50:03Z","publisher":"IEEE","author":[{"first_name":"Petra","full_name":"Berenbrink, Petra","last_name":"Berenbrink"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"first_name":"Tom","full_name":"Friedetzky, Tom","last_name":"Friedetzky"},{"full_name":"Nagel, Lars","first_name":"Lars","last_name":"Nagel"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS)","user_id":"24135","title":"Balls into Non-uniform Bins","year":"2010","citation":{"ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, and L. Nagel, “Balls into Non-uniform Bins,” in Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), 2010, pp. 1–10.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2010, pp. 1–10.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Nagel_2010, title={Balls into Non-uniform Bins}, DOI={10.1109/IPDPS.2010.5470355}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}, year={2010}, pages={1–10} }","mla":"Berenbrink, Petra, et al. “Balls into Non-Uniform Bins.” Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2010, pp. 1–10, doi:10.1109/IPDPS.2010.5470355.","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, and Lars Nagel. “Balls into Non-Uniform Bins.” In Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), 1–10. IEEE, 2010. https://doi.org/10.1109/IPDPS.2010.5470355.","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Nagel L. Balls into Non-uniform Bins. In: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS). IEEE; 2010:1-10. doi:10.1109/IPDPS.2010.5470355","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., & Nagel, L. (2010). Balls into Non-uniform Bins. In Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) (pp. 1–10). IEEE. https://doi.org/10.1109/IPDPS.2010.5470355"},"type":"conference","page":"1-10","doi":"10.1109/IPDPS.2010.5470355","_id":"2232","date_updated":"2022-01-06T06:55:31Z"},{"citation":{"chicago":"Bolte, Matthias, Michael Sievers, Georg Birkenheuer, Oliver Niehörster, and André Brinkmann. “Non-Intrusive Virtualization Management Using Libvirt.” In Proc. Design, Automation and Test in Europe Conf. (DATE). EDA Consortium, 2010.","apa":"Bolte, M., Sievers, M., Birkenheuer, G., Niehörster, O., & Brinkmann, A. (2010). Non-intrusive Virtualization Management Using libvirt. In Proc. Design, Automation and Test in Europe Conf. (DATE). EDA Consortium.","ama":"Bolte M, Sievers M, Birkenheuer G, Niehörster O, Brinkmann A. Non-intrusive Virtualization Management Using libvirt. In: Proc. Design, Automation and Test in Europe Conf. (DATE). EDA Consortium; 2010.","mla":"Bolte, Matthias, et al. “Non-Intrusive Virtualization Management Using Libvirt.” Proc. Design, Automation and Test in Europe Conf. (DATE), EDA Consortium, 2010.","bibtex":"@inproceedings{Bolte_Sievers_Birkenheuer_Niehörster_Brinkmann_2010, title={Non-intrusive Virtualization Management Using libvirt}, booktitle={Proc. Design, Automation and Test in Europe Conf. (DATE)}, publisher={EDA Consortium}, author={Bolte, Matthias and Sievers, Michael and Birkenheuer, Georg and Niehörster, Oliver and Brinkmann, André}, year={2010} }","short":"M. Bolte, M. Sievers, G. Birkenheuer, O. Niehörster, A. Brinkmann, in: Proc. Design, Automation and Test in Europe Conf. (DATE), EDA Consortium, 2010.","ieee":"M. Bolte, M. Sievers, G. Birkenheuer, O. Niehörster, and A. Brinkmann, “Non-intrusive Virtualization Management Using libvirt,” in Proc. Design, Automation and Test in Europe Conf. (DATE), 2010."},"year":"2010","type":"conference","_id":"2234","date_updated":"2022-01-06T06:55:31Z","publication":"Proc. Design, Automation and Test in Europe Conf. (DATE)","department":[{"_id":"27"}],"publisher":"EDA Consortium","author":[{"last_name":"Bolte","first_name":"Matthias","full_name":"Bolte, Matthias"},{"full_name":"Sievers, Michael","first_name":"Michael","last_name":"Sievers"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"date_created":"2018-04-05T16:52:36Z","status":"public","user_id":"24135","title":"Non-intrusive Virtualization Management Using libvirt"},{"page":"177-184","type":"conference","year":"2010","citation":{"short":"G. Birkenheuer, S. Breuers, A. Brinkmann, D. Blunk, G. Fels, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, L. Packschies, in: Proc. of Grid Workflow Workshop (GWW), Gesellschaft für Informatik (GI), 2010, pp. 177–184.","ieee":"G. Birkenheuer et al., “Grid-Workflows in Molecular Science,” in Proc. of Grid Workflow Workshop (GWW), 2010, pp. 177–184.","chicago":"Birkenheuer, Georg, Sebastian Breuers, André Brinkmann, Dirk Blunk, Gregor Fels, Sandra Gesing, Sonja Herres-Pawlis, Oliver Kohlbacher, Jens Krüger, and Lars Packschies. “Grid-Workflows in Molecular Science.” In Proc. of Grid Workflow Workshop (GWW), 177–84. Lecture Notes in Informatics. Gesellschaft für Informatik (GI), 2010.","apa":"Birkenheuer, G., Breuers, S., Brinkmann, A., Blunk, D., Fels, G., Gesing, S., … Packschies, L. (2010). Grid-Workflows in Molecular Science. In Proc. of Grid Workflow Workshop (GWW) (pp. 177–184). Gesellschaft für Informatik (GI).","ama":"Birkenheuer G, Breuers S, Brinkmann A, et al. Grid-Workflows in Molecular Science. In: Proc. of Grid Workflow Workshop (GWW). Lecture Notes in Informatics. Gesellschaft für Informatik (GI); 2010:177-184.","mla":"Birkenheuer, Georg, et al. “Grid-Workflows in Molecular Science.” Proc. of Grid Workflow Workshop (GWW), Gesellschaft für Informatik (GI), 2010, pp. 177–84.","bibtex":"@inproceedings{Birkenheuer_Breuers_Brinkmann_Blunk_Fels_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Packschies_2010, series={Lecture Notes in Informatics}, title={Grid-Workflows in Molecular Science}, booktitle={Proc. of Grid Workflow Workshop (GWW)}, publisher={Gesellschaft für Informatik (GI)}, author={Birkenheuer, Georg and Breuers, Sebastian and Brinkmann, André and Blunk, Dirk and Fels, Gregor and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Packschies, Lars}, year={2010}, pages={177–184}, collection={Lecture Notes in Informatics} }"},"series_title":"Lecture Notes in Informatics","_id":"2236","date_updated":"2022-01-06T06:55:31Z","date_created":"2018-04-05T17:03:41Z","status":"public","publication":"Proc. of Grid Workflow Workshop (GWW)","department":[{"_id":"27"}],"author":[{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"full_name":"Breuers, Sebastian","first_name":"Sebastian","last_name":"Breuers"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"first_name":"Oliver","full_name":"Kohlbacher, Oliver","last_name":"Kohlbacher"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"last_name":"Packschies","first_name":"Lars","full_name":"Packschies, Lars"}],"publisher":"Gesellschaft für Informatik (GI)","user_id":"24135","title":"Grid-Workflows in Molecular Science"},{"citation":{"short":"O. Niehörster, A. Brinkmann, G. Fels, J. Krüger, J. Simon, in: Proc. Int. Conf. on Cluster Computing (CLUSTER), IEEE, 2010, pp. 178–187.","ieee":"O. Niehörster, A. Brinkmann, G. Fels, J. Krüger, and J. Simon, “Enforcing SLAs in Scientific Clouds,” in Proc. Int. Conf. on Cluster Computing (CLUSTER), 2010, pp. 178–187.","ama":"Niehörster O, Brinkmann A, Fels G, Krüger J, Simon J. Enforcing SLAs in Scientific Clouds. In: Proc. Int. Conf. on Cluster Computing (CLUSTER). IEEE; 2010:178-187. doi:10.1109/CLUSTER.2010.42","apa":"Niehörster, O., Brinkmann, A., Fels, G., Krüger, J., & Simon, J. (2010). Enforcing SLAs in Scientific Clouds. In Proc. Int. Conf. on Cluster Computing (CLUSTER) (pp. 178–187). IEEE. https://doi.org/10.1109/CLUSTER.2010.42","chicago":"Niehörster, Oliver, André Brinkmann, Gregor Fels, Jens Krüger, and Jens Simon. “Enforcing SLAs in Scientific Clouds.” In Proc. Int. Conf. on Cluster Computing (CLUSTER), 178–87. IEEE, 2010. https://doi.org/10.1109/CLUSTER.2010.42.","bibtex":"@inproceedings{Niehörster_Brinkmann_Fels_Krüger_Simon_2010, title={Enforcing SLAs in Scientific Clouds}, DOI={10.1109/CLUSTER.2010.42}, booktitle={Proc. Int. Conf. on Cluster Computing (CLUSTER)}, publisher={IEEE}, author={Niehörster, Oliver and Brinkmann, André and Fels, Gregor and Krüger, Jens and Simon, Jens}, year={2010}, pages={178–187} }","mla":"Niehörster, Oliver, et al. “Enforcing SLAs in Scientific Clouds.” Proc. Int. Conf. on Cluster Computing (CLUSTER), IEEE, 2010, pp. 178–87, doi:10.1109/CLUSTER.2010.42."},"year":"2010","type":"conference","page":"178-187","doi":"10.1109/CLUSTER.2010.42","date_updated":"2022-01-06T06:55:32Z","_id":"2237","status":"public","date_created":"2018-04-05T17:05:44Z","publication_identifier":{"issn":["1552-5244"]},"author":[{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"last_name":"Simon","id":"15273","first_name":"Jens","full_name":"Simon, Jens"}],"publisher":"IEEE","publication":"Proc. Int. Conf. on Cluster Computing (CLUSTER)","department":[{"_id":"27"}],"user_id":"24135","title":"Enforcing SLAs in Scientific Clouds"},{"citation":{"chicago":"Birkenheuer, Georg, Andre Brinkmann, and Holger Karl. “Risk Aware Overbooking for Commercial Grids.” In Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers, 51–76, 2010. https://doi.org/10.1007/978-3-642-16505-4_4.","apa":"Birkenheuer, G., Brinkmann, A., & Karl, H. (2010). Risk Aware Overbooking for Commercial Grids. In Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers (pp. 51–76). https://doi.org/10.1007/978-3-642-16505-4_4","ama":"Birkenheuer G, Brinkmann A, Karl H. Risk Aware Overbooking for Commercial Grids. In: Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers. ; 2010:51-76. doi:10.1007/978-3-642-16505-4_4","mla":"Birkenheuer, Georg, et al. “Risk Aware Overbooking for Commercial Grids.” Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers, 2010, pp. 51–76, doi:10.1007/978-3-642-16505-4_4.","bibtex":"@inproceedings{Birkenheuer_Brinkmann_Karl_2010, title={Risk Aware Overbooking for Commercial Grids}, DOI={10.1007/978-3-642-16505-4_4}, booktitle={Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers}, author={Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}, year={2010}, pages={51–76} }","short":"G. Birkenheuer, A. Brinkmann, H. Karl, in: Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers, 2010, pp. 51–76.","ieee":"G. Birkenheuer, A. Brinkmann, and H. Karl, “Risk Aware Overbooking for Commercial Grids,” in Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers, 2010, pp. 51–76."},"year":"2010","type":"conference","page":"51-76","doi":"10.1007/978-3-642-16505-4_4","_id":"809","date_updated":"2022-01-06T07:03:50Z","status":"public","date_created":"2017-11-27T10:22:26Z","author":[{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"last_name":"Brinkmann","first_name":"Andre","full_name":"Brinkmann, Andre"},{"id":"126","last_name":"Karl","full_name":"Karl, Holger","first_name":"Holger"}],"publication":"Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers","department":[{"_id":"75"},{"_id":"27"}],"title":"Risk Aware Overbooking for Commercial Grids","user_id":"24135"},{"date_updated":"2023-09-26T13:48:32Z","_id":"2223","language":[{"iso":"eng"}],"page":"225-231","year":"2010","type":"conference","citation":{"short":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, B. Plattner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–231.","ieee":"E. Lübbers, M. Platzner, C. Plessl, A. Keller, and B. Plattner, “Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 225–231.","apa":"Lübbers, E., Platzner, M., Plessl, C., Keller, A., & Plattner, B. (2010). Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–231.","ama":"Lübbers E, Platzner M, Plessl C, Keller A, Plattner B. Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:225-231.","chicago":"Lübbers, Enno, Marco Platzner, Christian Plessl, Ariane Keller, and Bernhard Plattner. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 225–31. CSREA Press, 2010.","mla":"Lübbers, Enno, et al. “Towards Adaptive Networking for Embedded Devices Based on Reconfigurable Hardware.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 225–31.","bibtex":"@inproceedings{Lübbers_Platzner_Plessl_Keller_Plattner_2010, title={Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}, year={2010}, pages={225–231} }"},"user_id":"15278","title":"Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Ariane","full_name":"Keller, Ariane","last_name":"Keller"},{"first_name":"Bernhard","full_name":"Plattner, Bernhard","last_name":"Plattner"}],"publisher":"CSREA Press","date_created":"2018-04-05T16:27:13Z","status":"public","publication_identifier":{"isbn":["1-60132-140-6"]}},{"type":"conference","citation":{"chicago":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. Los Alamitos, CA, USA: IEEE Computer Society, 2010. https://doi.org/10.1109/ReConFig.2010.19.","apa":"Grad, M., & Plessl, C. (2010). Pruning the Design Space for Just-In-Time Processor Customization. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 67–72. https://doi.org/10.1109/ReConFig.2010.19","ama":"Grad M, Plessl C. Pruning the Design Space for Just-In-Time Processor Customization. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2010:67-72. doi:10.1109/ReConFig.2010.19","mla":"Grad, Mariusz, and Christian Plessl. “Pruning the Design Space for Just-In-Time Processor Customization.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2010, pp. 67–72, doi:10.1109/ReConFig.2010.19.","bibtex":"@inproceedings{Grad_Plessl_2010, place={Los Alamitos, CA, USA}, title={Pruning the Design Space for Just-In-Time Processor Customization}, DOI={10.1109/ReConFig.2010.19}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={67–72} }","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2010, pp. 67–72.","ieee":"M. Grad and C. Plessl, “Pruning the Design Space for Just-In-Time Processor Customization,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2010, pp. 67–72, doi: 10.1109/ReConFig.2010.19."},"year":"2010","page":"67-72","language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2010.19","date_updated":"2023-09-26T13:47:11Z","_id":"2216","status":"public","date_created":"2018-04-05T14:48:51Z","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","title":"Pruning the Design Space for Just-In-Time Processor Customization","user_id":"15278","place":"Los Alamitos, CA, USA"},{"publication_identifier":{"isbn":["1-60132-140-6"]},"date_created":"2018-04-05T16:28:38Z","status":"public","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"CSREA Press","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","title":"An Open Source Circuit Library with Benchmarking Facilities","user_id":"15278","page":"144-150","year":"2010","type":"conference","citation":{"chicago":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.","apa":"Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.","ama":"Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.","mla":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.","bibtex":"@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.","ieee":"M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150."},"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:48:59Z","_id":"2224"},{"date_updated":"2023-09-26T13:47:33Z","_id":"2220","language":[{"iso":"eng"}],"page":"165","year":"2010","citation":{"chicago":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165. CSREA Press, 2010.","ama":"Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.","apa":"Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.","bibtex":"@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }","mla":"Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","short":"D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.","ieee":"D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165."},"type":"conference","user_id":"15278","title":"Configurable Processor Architectures: History and Trends","date_created":"2018-04-05T14:57:07Z","status":"public","publication_identifier":{"isbn":["1-60132-140-6"]},"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","publisher":"CSREA Press","author":[{"full_name":"Andrews, David","first_name":"David","last_name":"Andrews"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1"}]