[{"abstract":[{"text":"We investigate the early time development of the anisotropic transverse flow\r\nand spatial eccentricities of a fireball with various particle-based transport\r\napproaches using a fixed initial condition. In numerical simulations ranging\r\nfrom the quasi-collisionless case to the hydrodynamic regime, we find that the\r\nonset of $v_n$ and of related measures of anisotropic flow can be described\r\nwith a simple power-law ansatz, with an exponent that depends on the amount of\r\nrescatterings in the system. In the few-rescatterings regime we perform\r\nsemi-analytical calculations, based on a systematic expansion in powers of time\r\nand the cross section, which can reproduce the numerical findings.","lang":"eng"}],"external_id":{"arxiv":["2201.13294"]},"user_id":"67287","title":"Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers","author":[{"last_name":"Borghini","full_name":"Borghini, Nicolas","first_name":"Nicolas"},{"last_name":"Borrell","first_name":"Marc","full_name":"Borrell, Marc"},{"last_name":"Roch","first_name":"Hendrik","full_name":"Roch, Hendrik"}],"publication":"arXiv:2201.13294","department":[{"_id":"27"}],"status":"public","date_created":"2022-06-27T09:08:04Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_updated":"2022-06-27T09:35:53Z","_id":"32177","language":[{"iso":"eng"}],"year":"2022","type":"preprint","citation":{"ieee":"N. Borghini, M. Borrell, and H. Roch, “Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers,” arXiv:2201.13294. 2022.","short":"N. Borghini, M. Borrell, H. Roch, ArXiv:2201.13294 (2022).","mla":"Borghini, Nicolas, et al. “Early Time Behavior of Spatial and Momentum Anisotropies in Kinetic Theory across Different Knudsen Numbers.” ArXiv:2201.13294, 2022.","bibtex":"@article{Borghini_Borrell_Roch_2022, title={Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers}, journal={arXiv:2201.13294}, author={Borghini, Nicolas and Borrell, Marc and Roch, Hendrik}, year={2022} }","apa":"Borghini, N., Borrell, M., & Roch, H. (2022). Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers. In arXiv:2201.13294.","ama":"Borghini N, Borrell M, Roch H. Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers. arXiv:220113294. Published online 2022.","chicago":"Borghini, Nicolas, Marc Borrell, and Hendrik Roch. “Early Time Behavior of Spatial and Momentum Anisotropies in Kinetic Theory across Different Knudsen Numbers.” ArXiv:2201.13294, 2022."}},{"author":[{"last_name":"Bachmann","first_name":"Benedikt","full_name":"Bachmann, Benedikt"},{"first_name":"Nicolas","full_name":"Borghini, Nicolas","last_name":"Borghini"},{"last_name":"Feld","full_name":"Feld, Nina","first_name":"Nina"},{"first_name":"Hendrik","full_name":"Roch, Hendrik","last_name":"Roch"}],"department":[{"_id":"27"}],"publication":"arXiv:2203.13306","status":"public","date_created":"2022-06-27T09:12:26Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"external_id":{"arxiv":["2203.13306"]},"abstract":[{"text":"We test the ability of the \"escape mechanism\" to create the anisotropic flow\r\nobserved in high-energy nuclear collisions. We compare the flow harmonics $v_n$\r\nin the few-rescatterings regime from two types of transport simulations, with\r\n$2\\to 2$ and $2\\to 0$ collision kernels respectively, and from analytical\r\ncalculations neglecting the gain term of the Boltzmann equation. We find that\r\nthe even flow harmonics are similar in the three approaches, while the odd\r\nharmonics differ significantly.","lang":"eng"}],"title":"Even anisotropic-flow harmonics are from Venus, odd ones are from Mars","user_id":"67287","year":"2022","type":"preprint","citation":{"mla":"Bachmann, Benedikt, et al. “Even Anisotropic-Flow Harmonics Are from Venus, Odd Ones Are from Mars.” ArXiv:2203.13306, 2022.","bibtex":"@article{Bachmann_Borghini_Feld_Roch_2022, title={Even anisotropic-flow harmonics are from Venus, odd ones are from Mars}, journal={arXiv:2203.13306}, author={Bachmann, Benedikt and Borghini, Nicolas and Feld, Nina and Roch, Hendrik}, year={2022} }","ieee":"B. Bachmann, N. Borghini, N. Feld, and H. Roch, “Even anisotropic-flow harmonics are from Venus, odd ones are from Mars,” arXiv:2203.13306. 2022.","chicago":"Bachmann, Benedikt, Nicolas Borghini, Nina Feld, and Hendrik Roch. “Even Anisotropic-Flow Harmonics Are from Venus, Odd Ones Are from Mars.” ArXiv:2203.13306, 2022.","short":"B. Bachmann, N. Borghini, N. Feld, H. Roch, ArXiv:2203.13306 (2022).","apa":"Bachmann, B., Borghini, N., Feld, N., & Roch, H. (2022). Even anisotropic-flow harmonics are from Venus, odd ones are from Mars. In arXiv:2203.13306.","ama":"Bachmann B, Borghini N, Feld N, Roch H. Even anisotropic-flow harmonics are from Venus, odd ones are from Mars. arXiv:220313306. Published online 2022."},"language":[{"iso":"eng"}],"date_updated":"2022-06-27T09:35:34Z","_id":"32178"},{"_id":"33493","date_updated":"2023-07-28T08:03:41Z","citation":{"bibtex":"@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747}, author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson, William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }","mla":"Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","ama":"Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022.","apa":"Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky, J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese, L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F., … Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era. In arXiv:2209.12747.","chicago":"Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","ieee":"V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale Era,” arXiv:2209.12747. 2022.","short":"V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022)."},"year":"2022","type":"preprint","language":[{"iso":"eng"}],"title":"Roadmap on Electronic Structure Codes in the Exascale Era","user_id":"24135","abstract":[{"lang":"eng","text":"Electronic structure calculations have been instrumental in providing many\r\nimportant insights into a range of physical and chemical properties of various\r\nmolecular and solid-state systems. Their importance to various fields,\r\nincluding materials science, chemical sciences, computational chemistry and\r\ndevice physics, is underscored by the large fraction of available public\r\nsupercomputing resources devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities to increase simulation numbers, sizes,\r\nand accuracies present themselves. In order to realize these promises, the\r\ncommunity of electronic structure software developers will however first have\r\nto tackle a number of challenges pertaining to the efficient use of new\r\narchitectures that will rely heavily on massive parallelism and hardware\r\naccelerators. This roadmap provides a broad overview of the state-of-the-art in\r\nelectronic structure calculations and of the various new directions being\r\npursued by the community. It covers 14 electronic structure codes, presenting\r\ntheir current status, their development priorities over the next five years,\r\nand their plans towards tackling the challenges and leveraging the\r\nopportunities presented by the advent of exascale computing."}],"external_id":{"arxiv":["2209.12747"]},"date_created":"2022-09-28T05:25:10Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","department":[{"_id":"27"},{"_id":"518"}],"publication":"arXiv:2209.12747","author":[{"first_name":"Vikram","full_name":"Gavini, Vikram","last_name":"Gavini"},{"last_name":"Baroni","full_name":"Baroni, Stefano","first_name":"Stefano"},{"last_name":"Blum","full_name":"Blum, Volker","first_name":"Volker"},{"last_name":"Bowler","first_name":"David R.","full_name":"Bowler, David R."},{"full_name":"Buccheri, Alexander","first_name":"Alexander","last_name":"Buccheri"},{"last_name":"Chelikowsky","first_name":"James R.","full_name":"Chelikowsky, James R."},{"first_name":"Sambit","full_name":"Das, Sambit","last_name":"Das"},{"full_name":"Dawson, William","first_name":"William","last_name":"Dawson"},{"last_name":"Delugas","full_name":"Delugas, Pietro","first_name":"Pietro"},{"last_name":"Dogan","first_name":"Mehmet","full_name":"Dogan, Mehmet"},{"last_name":"Draxl","full_name":"Draxl, Claudia","first_name":"Claudia"},{"last_name":"Galli","first_name":"Giulia","full_name":"Galli, Giulia"},{"last_name":"Genovese","full_name":"Genovese, Luigi","first_name":"Luigi"},{"first_name":"Paolo","full_name":"Giannozzi, Paolo","last_name":"Giannozzi"},{"last_name":"Giantomassi","first_name":"Matteo","full_name":"Giantomassi, Matteo"},{"last_name":"Gonze","full_name":"Gonze, Xavier","first_name":"Xavier"},{"full_name":"Govoni, Marco","first_name":"Marco","last_name":"Govoni"},{"last_name":"Gulans","first_name":"Andris","full_name":"Gulans, Andris"},{"full_name":"Gygi, François","first_name":"François","last_name":"Gygi"},{"first_name":"John M.","full_name":"Herbert, John M.","last_name":"Herbert"},{"full_name":"Kokott, Sebastian","first_name":"Sebastian","last_name":"Kokott"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"last_name":"Liou","full_name":"Liou, Kai-Hsin","first_name":"Kai-Hsin"},{"full_name":"Miyazaki, Tsuyoshi","first_name":"Tsuyoshi","last_name":"Miyazaki"},{"last_name":"Motamarri","full_name":"Motamarri, Phani","first_name":"Phani"},{"last_name":"Nakata","first_name":"Ayako","full_name":"Nakata, Ayako"},{"full_name":"Pask, John E.","first_name":"John E.","last_name":"Pask"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Ratcliff","first_name":"Laura E.","full_name":"Ratcliff, Laura E."},{"last_name":"Richard","full_name":"Richard, Ryan M.","first_name":"Ryan M."},{"first_name":"Mariana","full_name":"Rossi, Mariana","last_name":"Rossi"},{"id":"75963","last_name":"Schade","full_name":"Schade, Robert","orcid":"0000-0002-6268-539","first_name":"Robert"},{"first_name":"Matthias","full_name":"Scheffler, Matthias","last_name":"Scheffler"},{"last_name":"Schütt","first_name":"Ole","full_name":"Schütt, Ole"},{"last_name":"Suryanarayana","first_name":"Phanish","full_name":"Suryanarayana, Phanish"},{"first_name":"Marc","full_name":"Torrent, Marc","last_name":"Torrent"},{"first_name":"Lionel","full_name":"Truflandier, Lionel","last_name":"Truflandier"},{"last_name":"Windus","full_name":"Windus, Theresa L.","first_name":"Theresa L."},{"last_name":"Xu","full_name":"Xu, Qimen","first_name":"Qimen"},{"last_name":"Yu","first_name":"Victor W. -Z.","full_name":"Yu, Victor W. -Z."},{"last_name":"Perez","full_name":"Perez, Danny","first_name":"Danny"}]},{"abstract":[{"lang":"eng","text":"Electronic structure calculations have been instrumental in providing many\r\nimportant insights into a range of physical and chemical properties of various\r\nmolecular and solid-state systems. Their importance to various fields,\r\nincluding materials science, chemical sciences, computational chemistry and\r\ndevice physics, is underscored by the large fraction of available public\r\nsupercomputing resources devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities to increase simulation numbers, sizes,\r\nand accuracies present themselves. In order to realize these promises, the\r\ncommunity of electronic structure software developers will however first have\r\nto tackle a number of challenges pertaining to the efficient use of new\r\narchitectures that will rely heavily on massive parallelism and hardware\r\naccelerators. This roadmap provides a broad overview of the state-of-the-art in\r\nelectronic structure calculations and of the various new directions being\r\npursued by the community. It covers 14 electronic structure codes, presenting\r\ntheir current status, their development priorities over the next five years,\r\nand their plans towards tackling the challenges and leveraging the\r\nopportunities presented by the advent of exascale computing."}],"external_id":{"arxiv":["2209.12747"]},"user_id":"75963","title":"Roadmap on Electronic Structure Codes in the Exascale Era","department":[{"_id":"27"}],"publication":"arXiv:2209.12747","author":[{"last_name":"Gavini","full_name":"Gavini, Vikram","first_name":"Vikram"},{"last_name":"Baroni","first_name":"Stefano","full_name":"Baroni, Stefano"},{"last_name":"Blum","full_name":"Blum, Volker","first_name":"Volker"},{"full_name":"Bowler, David R.","first_name":"David R.","last_name":"Bowler"},{"full_name":"Buccheri, Alexander","first_name":"Alexander","last_name":"Buccheri"},{"last_name":"Chelikowsky","full_name":"Chelikowsky, James R.","first_name":"James R."},{"full_name":"Das, Sambit","first_name":"Sambit","last_name":"Das"},{"last_name":"Dawson","full_name":"Dawson, William","first_name":"William"},{"last_name":"Delugas","full_name":"Delugas, Pietro","first_name":"Pietro"},{"last_name":"Dogan","full_name":"Dogan, Mehmet","first_name":"Mehmet"},{"last_name":"Draxl","full_name":"Draxl, Claudia","first_name":"Claudia"},{"last_name":"Galli","full_name":"Galli, Giulia","first_name":"Giulia"},{"first_name":"Luigi","full_name":"Genovese, Luigi","last_name":"Genovese"},{"full_name":"Giannozzi, Paolo","first_name":"Paolo","last_name":"Giannozzi"},{"first_name":"Matteo","full_name":"Giantomassi, Matteo","last_name":"Giantomassi"},{"last_name":"Gonze","first_name":"Xavier","full_name":"Gonze, Xavier"},{"first_name":"Marco","full_name":"Govoni, Marco","last_name":"Govoni"},{"first_name":"Andris","full_name":"Gulans, Andris","last_name":"Gulans"},{"full_name":"Gygi, François","first_name":"François","last_name":"Gygi"},{"last_name":"Herbert","first_name":"John M.","full_name":"Herbert, John M."},{"last_name":"Kokott","full_name":"Kokott, Sebastian","first_name":"Sebastian"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"first_name":"Kai-Hsin","full_name":"Liou, Kai-Hsin","last_name":"Liou"},{"last_name":"Miyazaki","full_name":"Miyazaki, Tsuyoshi","first_name":"Tsuyoshi"},{"last_name":"Motamarri","full_name":"Motamarri, Phani","first_name":"Phani"},{"last_name":"Nakata","first_name":"Ayako","full_name":"Nakata, Ayako"},{"last_name":"Pask","first_name":"John E.","full_name":"Pask, John E."},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Ratcliff","first_name":"Laura E.","full_name":"Ratcliff, Laura E."},{"last_name":"Richard","full_name":"Richard, Ryan M.","first_name":"Ryan M."},{"full_name":"Rossi, Mariana","first_name":"Mariana","last_name":"Rossi"},{"first_name":"Robert","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","last_name":"Schade","id":"75963"},{"last_name":"Scheffler","full_name":"Scheffler, Matthias","first_name":"Matthias"},{"last_name":"Schütt","full_name":"Schütt, Ole","first_name":"Ole"},{"last_name":"Suryanarayana","full_name":"Suryanarayana, Phanish","first_name":"Phanish"},{"last_name":"Torrent","first_name":"Marc","full_name":"Torrent, Marc"},{"full_name":"Truflandier, Lionel","first_name":"Lionel","last_name":"Truflandier"},{"last_name":"Windus","first_name":"Theresa L.","full_name":"Windus, Theresa L."},{"last_name":"Xu","full_name":"Xu, Qimen","first_name":"Qimen"},{"full_name":"Yu, Victor W. -Z.","first_name":"Victor W. -Z.","last_name":"Yu"},{"first_name":"Danny","full_name":"Perez, Danny","last_name":"Perez"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2023-08-02T14:59:18Z","status":"public","_id":"46275","date_updated":"2023-08-02T15:00:47Z","language":[{"iso":"eng"}],"citation":{"chicago":"Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","apa":"Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky, J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese, L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F., … Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era. In arXiv:2209.12747.","ama":"Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022.","bibtex":"@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747}, author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson, William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }","mla":"Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022.","short":"V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022).","ieee":"V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale Era,” arXiv:2209.12747. 2022."},"year":"2022","type":"preprint"},{"main_file_link":[{"open_access":"1","url":"https://dl.acm.org/doi/pdf/10.1145/3468267.3470617"}],"language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Kenter_Shambhu_Faghih-Naini_Aizinger_2021, title={Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA}, DOI={10.1145/3468267.3470617}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Kenter, Tobias and Shambhu, Adesh and Faghih-Naini, Sara and Aizinger, Vadym}, year={2021} }","mla":"Kenter, Tobias, et al. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021, doi:10.1145/3468267.3470617.","ama":"Kenter T, Shambhu A, Faghih-Naini S, Aizinger V. Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2021. doi:10.1145/3468267.3470617","apa":"Kenter, T., Shambhu, A., Faghih-Naini, S., & Aizinger, V. (2021). Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3468267.3470617","chicago":"Kenter, Tobias, Adesh Shambhu, Sara Faghih-Naini, and Vadym Aizinger. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2021. https://doi.org/10.1145/3468267.3470617.","ieee":"T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,” 2021, doi: 10.1145/3468267.3470617.","short":"T. Kenter, A. Shambhu, S. Faghih-Naini, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021."},"type":"conference","year":"2021","date_updated":"2023-07-28T12:03:19Z","_id":"46194","oa":"1","doi":"10.1145/3468267.3470617","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proceedings of the Platform for Advanced Scientific Computing Conference","publisher":"ACM","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Adesh","full_name":"Shambhu, Adesh","last_name":"Shambhu"},{"full_name":"Faghih-Naini, Sara","first_name":"Sara","last_name":"Faghih-Naini"},{"last_name":"Aizinger","full_name":"Aizinger, Vadym","first_name":"Vadym"}],"quality_controlled":"1","date_created":"2023-07-28T11:58:14Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","publication_status":"published","user_id":"3145","title":"Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA"},{"user_id":"27340","title":"Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts","department":[{"_id":"66"},{"_id":"534"},{"_id":"624"},{"_id":"219"},{"_id":"27"}],"publication":"Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision","author":[{"last_name":"Nickchen","first_name":"Tobias","full_name":"Nickchen, Tobias"},{"last_name":"Heindorf","full_name":"Heindorf, Stefan","first_name":"Stefan"},{"full_name":"Engels, Gregor","first_name":"Gregor","last_name":"Engels"}],"date_created":"2021-01-07T15:32:45Z","status":"public","publication_status":"published","conference":{"location":"Hawaii","start_date":"2021-05-01","name":"IEEE/CVF Winter Conference on Applications of Computer Vision","end_date":"2021-09-01"},"date_updated":"2022-01-06T06:54:41Z","_id":"20886","language":[{"iso":"eng"}],"page":"1994-2002","year":"2021","citation":{"short":"T. Nickchen, S. Heindorf, G. Engels, in: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2021, pp. 1994–2002.","ieee":"T. Nickchen, S. Heindorf, and G. Engels, “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts,” in Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, Hawaii, 2021, pp. 1994–2002.","ama":"Nickchen T, Heindorf S, Engels G. Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts. In: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision. ; 2021:1994-2002.","apa":"Nickchen, T., Heindorf, S., & Engels, G. (2021). Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts. In Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision (pp. 1994–2002). Hawaii.","chicago":"Nickchen, Tobias, Stefan Heindorf, and Gregor Engels. “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts.” In Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 1994–2002, 2021.","bibtex":"@inproceedings{Nickchen_Heindorf_Engels_2021, title={Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts}, booktitle={Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision}, author={Nickchen, Tobias and Heindorf, Stefan and Engels, Gregor}, year={2021}, pages={1994–2002} }","mla":"Nickchen, Tobias, et al. “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts.” Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2021, pp. 1994–2002."},"type":"conference"},{"status":"public","date_created":"2023-07-28T12:04:27Z","publication_status":"published","publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Martin","full_name":"Karp, Martin","last_name":"Karp"},{"last_name":"Podobas","full_name":"Podobas, Artur","first_name":"Artur"},{"last_name":"Jansson","full_name":"Jansson, Niclas","first_name":"Niclas"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Schlatter","first_name":"Philipp","full_name":"Schlatter, Philipp"},{"last_name":"Markidis","full_name":"Markidis, Stefano","first_name":"Stefano"}],"publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","language":[{"iso":"eng"}],"citation":{"mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021."},"year":"2021","type":"conference","doi":"10.1109/ipdps49936.2021.00116","_id":"46195","date_updated":"2023-07-28T12:05:15Z"},{"language":[{"iso":"eng"}],"type":"conference","year":"2021","citation":{"ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116."},"date_updated":"2024-01-22T09:59:13Z","_id":"29937","doi":"10.1109/ipdps49936.2021.00116","author":[{"last_name":"Karp","first_name":"Martin","full_name":"Karp, Martin"},{"last_name":"Podobas","first_name":"Artur","full_name":"Podobas, Artur"},{"last_name":"Jansson","full_name":"Jansson, Niclas","first_name":"Niclas"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Schlatter","full_name":"Schlatter, Philipp","first_name":"Philipp"},{"last_name":"Markidis","full_name":"Markidis, Stefano","first_name":"Stefano"}],"quality_controlled":"1","publisher":"IEEE","department":[{"_id":"27"},{"_id":"518"}],"publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","status":"public","date_created":"2022-02-21T14:26:37Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_status":"published","user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection"},{"language":[{"iso":"eng"}],"type":"preprint","citation":{"ieee":"H. Farheen, T. Leuteritz, S. Linden, V. Myroshnychenko, and J. Förstner, “Optimization of optical waveguide antennas for directive emission of light,” arXiv:2106.02468. 2021.","short":"H. Farheen, T. Leuteritz, S. Linden, V. Myroshnychenko, J. Förstner, ArXiv:2106.02468 (2021).","mla":"Farheen, Henna, et al. “Optimization of Optical Waveguide Antennas for Directive Emission of Light.” ArXiv:2106.02468, 2021.","bibtex":"@article{Farheen_Leuteritz_Linden_Myroshnychenko_Förstner_2021, title={Optimization of optical waveguide antennas for directive emission of light}, journal={arXiv:2106.02468}, author={Farheen, Henna and Leuteritz, Till and Linden, Stefan and Myroshnychenko, Viktor and Förstner, Jens}, year={2021} }","ama":"Farheen H, Leuteritz T, Linden S, Myroshnychenko V, Förstner J. Optimization of optical waveguide antennas for directive emission of light. arXiv:210602468. Published online 2021.","apa":"Farheen, H., Leuteritz, T., Linden, S., Myroshnychenko, V., & Förstner, J. (2021). Optimization of optical waveguide antennas for directive emission of light. In arXiv:2106.02468.","chicago":"Farheen, Henna, Till Leuteritz, Stefan Linden, Viktor Myroshnychenko, and Jens Förstner. “Optimization of Optical Waveguide Antennas for Directive Emission of Light.” ArXiv:2106.02468, 2021."},"year":"2021","_id":"32245","date_updated":"2022-06-28T08:01:39Z","author":[{"last_name":"Farheen","first_name":"Henna","full_name":"Farheen, Henna"},{"last_name":"Leuteritz","full_name":"Leuteritz, Till","first_name":"Till"},{"full_name":"Linden, Stefan","first_name":"Stefan","last_name":"Linden"},{"last_name":"Myroshnychenko","first_name":"Viktor","full_name":"Myroshnychenko, Viktor"},{"full_name":"Förstner, Jens","first_name":"Jens","last_name":"Förstner"}],"publication":"arXiv:2106.02468","department":[{"_id":"27"}],"status":"public","date_created":"2022-06-28T08:01:09Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"external_id":{"arxiv":["2106.02468"]},"abstract":[{"lang":"eng","text":"Optical travelling wave antennas offer unique opportunities to control and\r\nselectively guide light into a specific direction which renders them as\r\nexcellent candidates for optical communication and sensing. These applications\r\nrequire state of the art engineering to reach optimized functionalities such as\r\nhigh directivity and radiation efficiency, low side lobe level, broadband and\r\ntunable capabilities, and compact design. In this work we report on the\r\nnumerical optimization of the directivity of optical travelling wave antennas\r\nmade from low-loss dielectric materials using full-wave numerical simulations\r\nin conjunction with a particle swarm optimization algorithm. The antennas are\r\ncomposed of a reflector and a director deposited on a glass substrate and an\r\nemitter placed in the feed gap between them serves as an internal source of\r\nexcitation. In particular, we analysed antennas with rectangular- and\r\nhorn-shaped directors made of either Hafnium dioxide or Silicon. The optimized\r\nantennas produce highly directional emission due to the presence of two\r\ndominant guided TE modes in the director in addition to leaky modes. These\r\nguided modes dominate the far-field emission pattern and govern the direction\r\nof the main lobe emission which predominately originates from the end facet of\r\nthe director. Our work also provides a comprehensive analysis of the modes,\r\nradiation patterns, parametric influences, and bandwidths of the antennas that\r\nhighlights their robust nature."}],"user_id":"15278","title":"Optimization of optical waveguide antennas for directive emission of light"},{"user_id":"14931","title":"Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities","abstract":[{"lang":"eng","text":"The interaction between quantum light and matter is being intensively studied\r\nfor systems that are enclosed in high-$Q$ cavities which strongly enhance the\r\nlight-matter coupling. However, for many applications, cavities with lower\r\n$Q$-factors are preferred due to the increased spectral width of the cavity\r\nmode. Here, we investigate the interaction between quantum light and matter\r\nrepresented by a $\\Lambda$-type three-level system in lossy cavities, assuming\r\nthat cavity losses are the dominant loss mechanism. We demonstrate that cavity\r\nlosses lead to non-trivial steady states of the electronic occupations that can\r\nbe controlled by the loss rate and the initial statistics of the quantum\r\nfields. The mechanism of formation of such steady states can be understood on\r\nthe basis of the equations of motion. Analytical expressions for steady states\r\nand their numerical simulations are presented and discussed."}],"external_id":{"arxiv":["2109.00842"]},"date_created":"2022-06-28T07:03:29Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","department":[{"_id":"27"}],"publication":"arXiv:2109.00842","author":[{"last_name":"Rose","full_name":"Rose, H.","first_name":"H."},{"first_name":"O. V.","full_name":"Tikhonova, O. V.","last_name":"Tikhonova"},{"last_name":"Meier","full_name":"Meier, T.","first_name":"T."},{"last_name":"Sharapova","full_name":"Sharapova, P. ","first_name":"P. "}],"date_updated":"2023-02-10T16:00:12Z","_id":"32236","language":[{"iso":"eng"}],"type":"preprint","year":"2021","citation":{"ama":"Rose H, Tikhonova OV, Meier T, Sharapova P. Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities. arXiv:210900842. Published online 2021.","apa":"Rose, H., Tikhonova, O. V., Meier, T., & Sharapova, P. (2021). Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities. In arXiv:2109.00842.","chicago":"Rose, H., O. V. Tikhonova, T. Meier, and P. Sharapova. “Steady States of $Λ$-Type Three-Level Systems Excited by Quantum Light in Lossy Cavities.” ArXiv:2109.00842, 2021.","bibtex":"@article{Rose_Tikhonova_Meier_Sharapova_2021, title={Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities}, journal={arXiv:2109.00842}, author={Rose, H. and Tikhonova, O. V. and Meier, T. and Sharapova, P. }, year={2021} }","mla":"Rose, H., et al. “Steady States of $Λ$-Type Three-Level Systems Excited by Quantum Light in Lossy Cavities.” ArXiv:2109.00842, 2021.","short":"H. Rose, O.V. Tikhonova, T. Meier, P. Sharapova, ArXiv:2109.00842 (2021).","ieee":"H. Rose, O. V. Tikhonova, T. Meier, and P. Sharapova, “Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities,” arXiv:2109.00842. 2021."}},{"date_updated":"2022-06-28T07:49:31Z","_id":"32244","language":[{"iso":"eng"}],"type":"preprint","citation":{"mla":"Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021.","bibtex":"@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et al._2021, title={Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms}, journal={arXiv:2104.08245}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas D. and et al.}, year={2021} }","ama":"Schade R, Kenter T, Elgabarty H, et al. Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms. arXiv:210408245. Published online 2021.","apa":"Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T. D., & Plessl, C. (2021). Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms. In arXiv:2104.08245.","chicago":"Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt, Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021.","ieee":"R. Schade et al., “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms,” arXiv:2104.08245. 2021.","short":"R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T.D. Kühne, C. Plessl, ArXiv:2104.08245 (2021)."},"year":"2021","external_id":{"arxiv":["2104.08245"]},"abstract":[{"text":"We push the boundaries of electronic structure-based \\textit{ab-initio}\r\nmolecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise\r\nbarely reachable with classical force-field methods or novel neural network and\r\nmachine learning potentials. We achieve this breakthrough by combining\r\ninnovations in linear-scaling AIMD, efficient and approximate sparse linear\r\nalgebra, low and mixed-precision floating-point computation on GPUs, and a\r\ncompensation scheme for the errors introduced by numerical approximations. The\r\ncore of our work is the non-orthogonalized local submatrix method (NOLSM),\r\nwhich scales very favorably to massively parallel computing systems and\r\ntranslates large sparse matrix operations into highly parallel, dense matrix\r\noperations that are ideally suited to hardware accelerators. We demonstrate\r\nthat the NOLSM method, which is at the center point of each AIMD step, is able\r\nto achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision\r\ncorresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs.","lang":"eng"}],"user_id":"15278","title":"Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms","department":[{"_id":"27"}],"publication":"arXiv:2104.08245","author":[{"first_name":"Robert","full_name":"Schade, Robert","last_name":"Schade"},{"full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter"},{"last_name":"Elgabarty","first_name":"Hossam","full_name":"Elgabarty, Hossam"},{"last_name":"Lass","first_name":"Michael","full_name":"Lass, Michael"},{"last_name":"Schütt","full_name":"Schütt, Ole","first_name":"Ole"},{"first_name":"Alfio","full_name":"Lazzaro, Alfio","last_name":"Lazzaro"},{"full_name":"Pabst, Hans","first_name":"Hans","last_name":"Pabst"},{"full_name":"Mohr, Stephan","first_name":"Stephan","last_name":"Mohr"},{"last_name":"Hutter","full_name":"Hutter, Jürg","first_name":"Jürg"},{"last_name":"Kühne","full_name":"Kühne, Thomas D.","first_name":"Thomas D."},{"first_name":"Christian","full_name":"Plessl, Christian","last_name":"Plessl"}],"date_created":"2022-06-28T07:48:31Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public"},{"title":"Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks","user_id":"40778","author":[{"id":"40778","last_name":"Meyer","full_name":"Meyer, Marius","first_name":"Marius"}],"publication":"Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","department":[{"_id":"27"}],"publication_status":"published","status":"public","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2021-11-10T14:42:17Z","_id":"27365","date_updated":"2022-01-06T06:57:38Z","doi":"10.1145/3468044.3468058","citation":{"apa":"Meyer, M. (2021). Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3468044.3468058","ama":"Meyer M. Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ; 2021. doi:10.1145/3468044.3468058","chicago":"Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” In Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021. https://doi.org/10.1145/3468044.3468058.","mla":"Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021, doi:10.1145/3468044.3468058.","bibtex":"@inproceedings{Meyer_2021, title={Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks}, DOI={10.1145/3468044.3468058}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Meyer, Marius}, year={2021} }","short":"M. Meyer, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021.","ieee":"M. Meyer, “Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks,” 2021, doi: 10.1145/3468044.3468058."},"year":"2021","type":"conference","language":[{"iso":"eng"}]},{"date_created":"2020-04-28T14:44:21Z","status":"public","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"id":"24135","last_name":"Lass","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael"},{"first_name":"Robert","orcid":"0000-0002-6268-539","full_name":"Schade, Robert","last_name":"Schade","id":"75963"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"user_id":"75963","abstract":[{"text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs.","lang":"eng"}],"page":"1127-1140","year":"2020","type":"conference","citation":{"short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084."},"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"conference":{"location":"Atlanta, GA, US","name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)"},"_id":"16898","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K","external_id":{"arxiv":["2004.10811"]},"place":"Los Alamitos, CA, USA","language":[{"iso":"eng"}],"doi":"10.1109/SC41405.2020.00084","date_updated":"2023-08-02T14:55:59Z"},{"citation":{"ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007."},"type":"conference","year":"2020","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"_id":"21632","status":"public","date_created":"2021-04-16T10:17:22Z","quality_controlled":"1","author":[{"first_name":"Marius","full_name":"Meyer, Marius","last_name":"Meyer","id":"40778"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"user_id":"15278","abstract":[{"text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/h2rc51942.2020.00007","date_updated":"2023-09-26T11:42:53Z","publication_status":"published","publication_identifier":{"isbn":["9781665415927"]},"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","description":"Official repository of the benchmark suite on GitHub","relation":"supplementary_material"}]}},{"date_updated":"2022-06-28T07:27:19Z","_id":"32242","language":[{"iso":"eng"}],"type":"preprint","year":"2020","citation":{"bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }","mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020.","short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020)."},"user_id":"15278","title":"Multi-Armed Bandits with Censored Consumption of Resources","abstract":[{"lang":"eng","text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms."}],"external_id":{"arxiv":["2011.00813"]},"date_created":"2022-06-28T07:26:54Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","department":[{"_id":"27"}],"publication":"arXiv:2011.00813","author":[{"last_name":"Bengs","full_name":"Bengs, Viktor","first_name":"Viktor"},{"last_name":"Hüllermeier","first_name":"Eyke","full_name":"Hüllermeier, Eyke"}]},{"conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"_id":"15478","type":"conference","year":"2019","citation":{"short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019.","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020."},"abstract":[{"lang":"eng","text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS."}],"user_id":"3145","ddc":["004"],"file":[{"access_level":"closed","date_created":"2020-01-09T12:53:57Z","file_name":"gorlani19_fpt.pdf","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2020-01-09T12:53:57Z","creator":"plessl","file_id":"15479","file_size":250559}],"file_date_updated":"2020-01-09T12:53:57Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","quality_controlled":"1","publisher":"IEEE","author":[{"first_name":"Paolo","full_name":"Gorlani, Paolo","last_name":"Gorlani","id":"72045"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"date_created":"2020-01-09T12:54:48Z","status":"public","has_accepted_license":"1","date_updated":"2022-01-06T06:52:26Z","doi":"10.1109/ICFPT47387.2019.00020","language":[{"iso":"eng"}],"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"HighPerMeshes","grant_number":"01|H16005","_id":"33"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1","_id":"32"}]},{"_id":"22","intvolume":" 10773","conference":{"location":"Orlando, FL, USA","start_date":"2017-06-02","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","end_date":"2017-06-02"},"type":"conference","citation":{"ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.","mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8."},"year":"2018","page":"132-151","abstract":[{"lang":"eng","text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation."}],"user_id":"15274","author":[{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"}],"publisher":"Springer","publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","keyword":["Scheduling Planning Mapping Workload management"],"volume":10773,"status":"public","date_created":"2017-07-25T14:54:08Z","date_updated":"2022-01-06T06:55:22Z","doi":"10.1007/978-3-319-77398-8_8","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","department":[{"_id":"27"}],"editor":[{"last_name":"Klusáček","full_name":"Klusáček, D.","first_name":"D."},{"last_name":"Cirne","full_name":"Cirne, W.","first_name":"W."},{"last_name":"Desai","full_name":"Desai, N.","first_name":"N."}],"publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"publication_status":"published"},{"user_id":"15278","abstract":[{"lang":"eng","text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution."}],"status":"public","date_created":"2018-03-22T10:53:01Z","quality_controlled":"1","author":[{"first_name":"Michael","full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","last_name":"Lass","id":"24135"},{"first_name":"Stephan","full_name":"Mohr, Stephan","last_name":"Mohr"},{"last_name":"Wiebeler","full_name":"Wiebeler, Hendrik","first_name":"Hendrik"},{"first_name":"Thomas","full_name":"Kühne, Thomas","last_name":"Kühne","id":"49079"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"ACM","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","_id":"1590","conference":{"name":"Platform for Advanced Scientific Computing Conference (PASC)","start_date":"2018-07-02","location":"Basel, Switzerland","end_date":"2018-07-04"},"type":"conference","citation":{"short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231."},"year":"2018","title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","place":"New York, NY, USA","external_id":{"arxiv":["1710.10899"]},"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"project":[{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"doi":"10.1145/3218176.3218231","date_updated":"2023-09-26T11:48:12Z","language":[{"iso":"eng"}]},{"file_date_updated":"2018-11-02T14:43:37Z","publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","keyword":["htrop"],"publisher":"ACM","quality_controlled":"1","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"file":[{"file_size":447769,"file_id":"5281","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T14:43:37Z","success":1,"relation":"main_file","date_created":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf","access_level":"closed"}],"date_created":"2018-03-08T14:45:18Z","has_accepted_license":"1","status":"public","ddc":["000"],"user_id":"15278","year":"2018","citation":{"short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }"},"type":"conference","_id":"1204","department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","publication_identifier":{"isbn":["9781450349826"]},"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"160364472","name":"SFB 901 - Subproject C2","_id":"14"}],"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534"},{"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037","language":[{"iso":"eng"}],"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"grant_number":"01|H16005A","name":"HighPerMeshes","_id":"33"},{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"}],"conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"_id":"1588","year":"2018","citation":{"short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037."},"type":"conference","abstract":[{"lang":"eng","text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x."}],"user_id":"15278","ddc":["000"],"file":[{"file_size":269130,"file_id":"5282","creator":"ups","content_type":"application/pdf","date_updated":"2018-11-02T14:45:05Z","relation":"main_file","success":1,"date_created":"2018-11-02T14:45:05Z","file_name":"08457652.pdf","access_level":"closed"}],"file_date_updated":"2018-11-02T14:45:05Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","keyword":["tet_topic_hpc"],"author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Mahale","first_name":"Gopinath","full_name":"Mahale, Gopinath"},{"full_name":"Alhaddad, Samer","first_name":"Samer","id":"42456","last_name":"Alhaddad"},{"last_name":"Grynko","id":"26059","first_name":"Yevgen","full_name":"Grynko, Yevgen"},{"full_name":"Schmitt, Christian","first_name":"Christian","last_name":"Schmitt"},{"first_name":"Ayesha","full_name":"Afzal, Ayesha","last_name":"Afzal"},{"full_name":"Hannig, Frank","first_name":"Frank","last_name":"Hannig"},{"last_name":"Förstner","id":"158","first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"quality_controlled":"1","publisher":"IEEE","date_created":"2018-03-22T10:48:01Z","has_accepted_license":"1","status":"public"},{"date_updated":"2023-09-26T13:24:38Z","doi":"10.23919/FPL.2017.8056844","language":[{"iso":"eng"}],"title":"Flexible FPGA design for FDTD using OpenCL","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"},{"grant_number":"01|H16005A","name":"HighPerMeshes","_id":"33"},{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"_id":"1592","citation":{"apa":"Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844","ama":"Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844","chicago":"Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.","mla":"Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844.","bibtex":"@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }","short":"T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.","ieee":"T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844."},"type":"conference","year":"2017","abstract":[{"lang":"eng","text":"Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures."}],"user_id":"15278","ddc":["000"],"file":[{"file_id":"5291","creator":"ups","file_size":230235,"success":1,"relation":"main_file","date_updated":"2018-11-02T15:02:28Z","content_type":"application/pdf","file_name":"08056844.pdf","date_created":"2018-11-02T15:02:28Z","access_level":"closed"}],"keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T15:02:28Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","publisher":"IEEE","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","date_created":"2018-03-22T11:10:23Z","status":"public","has_accepted_license":"1"},{"citation":{"bibtex":"@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }","mla":"Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.","ama":"Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11","apa":"Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11","chicago":"Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11.","ieee":"M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016.","short":"M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016."},"type":"conference","year":"2016","language":[{"iso":"eng"}],"doi":"10.1109/lcn.2016.11","date_updated":"2022-01-06T06:53:56Z","_id":"19","publication_status":"published","publication_identifier":{"isbn":["978-1-5090-2054-6"]},"date_created":"2017-07-25T14:36:16Z","status":"public","department":[{"_id":"27"},{"_id":"518"}],"keyword":["access control","distributed version control systems","mercurial","peer-to-peer","convergent encryption","confidentiality","authenticity"],"publication":"Proc. 41st Conference on Local Computer Networks (LCN)","author":[{"last_name":"Lass","id":"24135","first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael"},{"first_name":"Dominik","full_name":"Leibenger, Dominik","last_name":"Leibenger"},{"full_name":"Sorge, Christoph","first_name":"Christoph","last_name":"Sorge"}],"publisher":"IEEE","title":"Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension","user_id":"24135","abstract":[{"text":"Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments.","lang":"eng"}]},{"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","file_date_updated":"2018-11-14T12:38:45Z","quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-14T12:38:45Z","file_id":"5602","creator":"kenter","file_size":129552,"access_level":"closed","file_name":"paper_26.pdf","date_created":"2018-11-14T12:38:45Z"}],"project":[{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subproject C2"}],"date_created":"2017-07-26T15:00:43Z","has_accepted_license":"1","status":"public","title":"Microdisk Cavity FDTD Simulation on FPGA using OpenCL","ddc":["004"],"user_id":"15278","year":"2016","citation":{"bibtex":"@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }","mla":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","chicago":"Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.","ama":"Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.","apa":"Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC).","ieee":"T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016.","short":"T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:26:17Z","_id":"24"},{"series_title":"Mathematics in Industry","page":"633-641","citation":{"chicago":"Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.","apa":"Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87","ama":"Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87","mla":"Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87.","bibtex":"@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }","short":"M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.","ieee":"M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641."},"type":"conference","year":"2016","date_updated":"2022-01-06T06:59:14Z","_id":"34","intvolume":" 22","doi":"10.1007/978-3-319-23413-7_87","department":[{"_id":"27"},{"_id":"101"}],"publication":"Progress in Industrial Mathematics at ECMI","author":[{"last_name":"Dellnitz","full_name":"Dellnitz, Michael","first_name":"Michael"},{"last_name":"Eckstein","full_name":"Eckstein, Julian","first_name":"Julian"},{"last_name":"Flaßkamp","full_name":"Flaßkamp, Kathrin","first_name":"Kathrin"},{"full_name":"Friedel, Patrick","first_name":"Patrick","last_name":"Friedel"},{"first_name":"Christian","full_name":"Horenkamp, Christian","last_name":"Horenkamp"},{"last_name":"Köhler","first_name":"Ulrich","full_name":"Köhler, Ulrich"},{"last_name":"Ober-Blöbaum","first_name":"Sina","full_name":"Ober-Blöbaum, Sina"},{"last_name":"Peitz","first_name":"Sebastian","full_name":"Peitz, Sebastian"},{"first_name":"Sebastian","full_name":"Tiemeyer, Sebastian","last_name":"Tiemeyer"}],"publisher":"Springer International Publishing","publication_identifier":{"issn":["2212-0173"]},"volume":22,"date_created":"2017-07-26T15:25:33Z","status":"public","place":"Cham","title":"Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control","user_id":"24135"},{"title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","ddc":["040"],"user_id":"15278","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"department":[{"_id":"27"},{"_id":"518"}],"file_date_updated":"2018-03-21T12:39:46Z","publication":"Workshop on Reconfigurable Computing (WRC)","file":[{"file_name":"171-plessl16_fpl_wrc.pdf","date_created":"2018-03-21T12:39:46Z","access_level":"closed","file_id":"1538","creator":"florida","file_size":54421,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-21T12:39:46Z"}],"has_accepted_license":"1","status":"public","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2017-10-17T12:41:25Z","date_updated":"2023-09-26T13:27:21Z","_id":"171","type":"conference","year":"2016","citation":{"short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016.","apa":"Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC).","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }"},"language":[{"iso":"eng"}]},{"ddc":["040"],"user_id":"15278","abstract":[{"text":"The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.","lang":"eng"}],"date_created":"2017-10-17T12:41:24Z","status":"public","has_accepted_license":"1","file_date_updated":"2018-03-21T12:41:55Z","publication":"Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","publisher":"EDA Consortium / IEEE","author":[{"first_name":"Achim","full_name":"Lösch, Achim","last_name":"Lösch","id":"43646"},{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"quality_controlled":"1","file":[{"creator":"florida","file_id":"1541","file_size":261356,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-21T12:41:55Z","file_name":"168-07459438.pdf","date_created":"2018-03-21T12:41:55Z","access_level":"closed"}],"_id":"168","page":"912-917","type":"conference","year":"2016","citation":{"ieee":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917.","short":"A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.","bibtex":"@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }","mla":"Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17.","ama":"Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.","apa":"Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917.","chicago":"Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016."},"title":"Performance-centric scheduling with task migration for a heterogeneous compute node in the data center","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_updated":"2023-09-26T13:27:00Z","language":[{"iso":"eng"}]},{"user_id":"15278","title":"Using Approximate Computing in Scientific Codes","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"date_created":"2017-07-26T15:02:20Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"publication":"Workshop on Approximate Computing (AC)","author":[{"full_name":"Lass, Michael","orcid":"0000-0002-5708-7632","first_name":"Michael","id":"24135","last_name":"Lass"},{"last_name":"Kühne","id":"49079","first_name":"Thomas","full_name":"Kühne, Thomas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"quality_controlled":"1","_id":"25","date_updated":"2023-09-26T13:25:17Z","language":[{"iso":"eng"}],"citation":{"short":"M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.","ieee":"M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016.","chicago":"Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.","apa":"Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC).","ama":"Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.","mla":"Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016.","bibtex":"@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }"},"year":"2016","type":"conference"},{"year":"2016","citation":{"apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC).","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016."},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:25:59Z","_id":"31","file_date_updated":"2019-01-11T11:56:55Z","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Trainiti, Ettore M. G.","first_name":"Ettore M. G.","last_name":"Trainiti"},{"last_name":"Durelli","first_name":"Gianluca C.","full_name":"Durelli, Gianluca C."},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"quality_controlled":"1","file":[{"file_id":"6626","creator":"deffel","file_size":394563,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-01-11T11:56:55Z","file_name":"wrc_upb_polimi_final.pdf","date_created":"2019-01-11T11:56:55Z","access_level":"closed"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"SFB 901 - Subproject C2","grant_number":"160364472","_id":"14"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_created":"2017-07-26T15:16:31Z","status":"public","has_accepted_license":"1","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","ddc":["040"],"user_id":"15278"},{"_id":"138","page":"1-5","year":"2016","citation":{"ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.","ieee":"H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545."},"type":"conference","abstract":[{"text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.","lang":"eng"}],"ddc":["040"],"user_id":"15278","file_date_updated":"2018-03-21T13:01:09Z","publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","publisher":"IEEE","quality_controlled":"1","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Trainiti","full_name":"Trainiti, Ettore M. G. ","first_name":"Ettore M. G. "},{"full_name":"Durelli, Gianluca C.","first_name":"Gianluca C.","last_name":"Durelli"},{"last_name":"Del Sozzo","full_name":"Del Sozzo, Emanuele","first_name":"Emanuele"},{"last_name":"Santambrogio","first_name":"Marco D. ","full_name":"Santambrogio, Marco D. "},{"last_name":"Bolchini","full_name":"Bolchini, Christina","first_name":"Christina"}],"file":[{"date_created":"2018-03-21T13:01:09Z","file_name":"138-07740545.pdf","access_level":"closed","file_size":184334,"file_id":"1560","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-21T13:01:09Z","success":1,"relation":"main_file"}],"date_created":"2017-10-17T12:41:18Z","status":"public","has_accepted_license":"1","date_updated":"2023-09-26T13:28:11Z","doi":"10.1109/RTSI.2016.7740545","language":[{"iso":"eng"}],"title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}]},{"language":[{"iso":"eng"}],"oa":"1","date_updated":"2023-09-26T13:29:59Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores","external_id":{"arxiv":["1412.3906"]},"citation":{"short":"M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","ieee":"M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015.","chicago":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","apa":"Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT).","ama":"Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.","mla":"Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.","bibtex":"@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }"},"year":"2015","type":"conference","_id":"303","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:41:51Z","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","publication":"Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)","file_date_updated":"2019-08-01T09:10:44Z","file":[{"date_created":"2018-03-20T07:46:46Z","file_name":"303-plessl15_adapt.pdf","access_level":"open_access","file_size":1176620,"creator":"florida","file_id":"1442","content_type":"application/pdf","date_updated":"2019-08-01T09:10:44Z","relation":"main_file"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.","lang":"eng"}]},{"citation":{"chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824."},"year":"2015","type":"conference","language":[{"iso":"eng"}],"doi":"10.1145/2675743.2771824","_id":"1773","date_updated":"2023-09-26T13:31:01Z","date_created":"2018-03-23T14:09:33Z","status":"public","publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"last_name":"T. Anderson","first_name":"J.","full_name":"T. Anderson, J."},{"last_name":"Borga","full_name":"Borga, A.","first_name":"A."},{"last_name":"Boterenbrood","full_name":"Boterenbrood, H.","first_name":"H."},{"first_name":"H.","full_name":"Chen, H.","last_name":"Chen"},{"last_name":"Chen","full_name":"Chen, K.","first_name":"K."},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"last_name":"Francis","full_name":"Francis, D.","first_name":"D."},{"first_name":"B.","full_name":"Gorini, B.","last_name":"Gorini"},{"last_name":"Lanni","first_name":"F.","full_name":"Lanni, F."},{"last_name":"Lehmann-Miotto","first_name":"Giovanna","full_name":"Lehmann-Miotto, Giovanna"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"last_name":"Narevicius","full_name":"Narevicius, J.","first_name":"J."},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Roich, A.","first_name":"A.","last_name":"Roich"},{"last_name":"Ryu","full_name":"Ryu, S.","first_name":"S."},{"last_name":"P. Schreuder","full_name":"P. Schreuder, F.","first_name":"F."},{"last_name":"Vandelli","first_name":"Wainer","full_name":"Vandelli, Wainer"},{"last_name":"Vermeulen","full_name":"Vermeulen, J.","first_name":"J."},{"full_name":"Zhang, J.","first_name":"J.","last_name":"Zhang"}],"publisher":"ACM","quality_controlled":"1","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","user_id":"15278"},{"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.7873/DATE.2015.1124","date_updated":"2023-09-26T13:31:44Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"date_created":"2017-10-17T12:41:38Z","status":"public","has_accepted_license":"1","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-21T10:29:49Z","content_type":"application/pdf","file_id":"1500","creator":"florida","file_size":380552,"access_level":"closed","file_name":"238-plessl15_date.pdf","date_created":"2018-03-21T10:29:49Z"}],"file_date_updated":"2018-03-21T10:29:49Z","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","quality_controlled":"1","publisher":"EDA Consortium / IEEE","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"_id":"238","page":"1078-1083","type":"conference","citation":{"ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124."},"year":"2015"},{"page":"1-8","year":"2014","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509."},"type":"conference","_id":"439","date_created":"2017-10-17T12:42:17Z","status":"public","has_accepted_license":"1","file":[{"creator":"florida","file_id":"1353","file_size":557362,"success":1,"relation":"main_file","date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:29:52Z","publisher":"IEEE","author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","user_id":"15278","ddc":["040"],"abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime"},{"date_updated":"2023-09-26T13:36:40Z","doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}],"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"_id":"406","page":"1-8","citation":{"bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"type":"conference","year":"2014","abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"user_id":"15278","ddc":["040"],"file":[{"access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","relation":"main_file","success":1,"file_size":932852,"creator":"florida","file_id":"1366"}],"file_date_updated":"2018-03-16T11:37:42Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","publisher":"IEEE","quality_controlled":"1","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"date_created":"2017-10-17T12:42:11Z","has_accepted_license":"1","status":"public"},{"_id":"1781","date_updated":"2022-01-06T06:53:20Z","doi":"10.1007/978-3-319-09063-4_19","page":"233-243","type":"conference","citation":{"ieee":"T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.","short":"T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.","mla":"Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.","bibtex":"@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }","chicago":"Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.","apa":"Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19","ama":"Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19"},"year":"2014","abstract":[{"lang":"eng","text":"In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment."}],"title":"Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres","user_id":"24135","department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"publication":"Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)","publisher":"Springer International Publishing","author":[{"first_name":"Tobias","full_name":"Steinle, Tobias","last_name":"Steinle"},{"full_name":"Vrabec, Jadran","first_name":"Jadran","last_name":"Vrabec"},{"first_name":"Andrea","full_name":"Walther, Andrea","last_name":"Walther"}],"publication_identifier":{"isbn":["978-3-319-09063-4"]},"editor":[{"last_name":"Bock","full_name":"Bock, Hans Georg","first_name":"Hans Georg"},{"last_name":"Hoang","first_name":"Xuan Phu","full_name":"Hoang, Xuan Phu"},{"first_name":"Rolf","full_name":"Rannacher, Rolf","last_name":"Rannacher"},{"last_name":"Schlöder","full_name":"Schlöder, Johannes P.","first_name":"Johannes P."}],"date_created":"2018-03-26T13:47:16Z","status":"public"},{"date_created":"2018-03-26T13:50:37Z","status":"public","publication":"Proc. Conf. on Computers and Games (CG)","department":[{"_id":"27"},{"_id":"78"}],"publisher":"Springer","author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"},{"last_name":"Schaefers","full_name":"Schaefers, Lars","first_name":"Lars"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"24135","title":"On Semeai Detection in Monte-Carlo Go","place":"Switzerland","page":"14-25","citation":{"mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25."},"type":"conference","year":"2014","series_title":"Lecture Notes in Computer Science","issue":"8427","doi":"10.1007/978-3-319-09165-5_2","date_updated":"2022-01-06T06:53:20Z","_id":"1782"},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","file_date_updated":"2018-03-20T07:02:02Z","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","publisher":"Springer International Publishing","file":[{"access_level":"closed","date_created":"2018-03-20T07:02:02Z","file_name":"388-plessl14_arc.pdf","content_type":"application/pdf","date_updated":"2018-03-20T07:02:02Z","relation":"main_file","success":1,"file_size":330193,"file_id":"1387","creator":"florida"}],"volume":8405,"date_created":"2017-10-17T12:42:07Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties."}],"ddc":["040"],"user_id":"15278","page":"144-155","type":"conference","citation":{"ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13."},"year":"2014","_id":"388","intvolume":" 8405"},{"date_created":"2017-10-17T12:42:05Z","has_accepted_license":"1","status":"public","keyword":["coldboot"],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","file_date_updated":"2018-03-20T07:14:20Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"file":[{"file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z","access_level":"closed","creator":"florida","file_id":"1397","file_size":1003907,"success":1,"relation":"main_file","date_updated":"2018-03-20T07:14:20Z","content_type":"application/pdf"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"page":"222-229","citation":{"mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229."},"year":"2014","type":"conference","_id":"377","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","date_updated":"2023-09-26T13:33:50Z"},{"date_updated":"2023-09-26T13:35:40Z","_id":"1778","doi":"10.1109/ISPA.2014.27","page":"142-149","year":"2014","type":"conference","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."},"language":[{"iso":"eng"}],"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"quality_controlled":"1","publisher":"IEEE","project":[{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2018-03-26T13:40:14Z","status":"public"},{"date_updated":"2023-09-26T13:36:20Z","_id":"1780","doi":"10.1007/978-3-319-05960-0_38","citation":{"bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014."},"type":"conference","year":"2014","language":[{"iso":"eng"}],"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Copolla","first_name":"Marcello","full_name":"Copolla, Marcello"},{"first_name":"Karim","full_name":"Djafarian, Karim","last_name":"Djafarian"},{"full_name":"Koranaros, George","first_name":"George","last_name":"Koranaros"},{"first_name":"Antonio","full_name":"Miele, Antonio","last_name":"Miele"},{"first_name":"Michele","full_name":"Paolino, Michele","last_name":"Paolino"},{"full_name":"Pell, Oliver","first_name":"Oliver","last_name":"Pell"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"first_name":"Marco","full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio"},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"quality_controlled":"1","publisher":"Springer","project":[{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"date_created":"2018-03-26T13:45:35Z","status":"public"},{"citation":{"ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }","mla":"Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148.","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148."},"year":"2013","type":"conference","doi":"10.1109/IPDPSW.2013.148","_id":"1788","date_updated":"2022-01-06T06:53:22Z","date_created":"2018-03-26T14:52:56Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","author":[{"last_name":"Berenbrink","first_name":"Petra","full_name":"Berenbrink, Petra"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Friedetzky","full_name":"Friedetzky, Tom","first_name":"Tom"},{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"last_name":"Nagel","first_name":"Lars","full_name":"Nagel, Lars"}],"publisher":"IEEE","user_id":"24135","title":"Distributing Storage in Cloud Environments"},{"year":"2013","type":"conference","citation":{"short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013.","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }"},"page":"175-182","_id":"1793","date_updated":"2022-01-06T06:53:23Z","publisher":"USENIX Association","author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"}],"department":[{"_id":"27"}],"publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","status":"public","date_created":"2018-03-26T15:16:03Z","user_id":"24135","title":"File Recipe Compression in Data Deduplication Systems"},{"date_created":"2018-03-26T14:48:53Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","publisher":"IEEE","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","user_id":"24135","citation":{"short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }"},"year":"2013","type":"conference","doi":"10.1109/SIU.2013.6531530","date_updated":"2022-01-06T06:53:20Z","_id":"1786"},{"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","language":[{"iso":"eng"}],"abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z","access_level":"closed","file_size":822680,"creator":"florida","file_id":"1294","content_type":"application/pdf","date_updated":"2018-03-15T10:36:08Z","success":1,"relation":"main_file"}],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2018-03-15T10:36:08Z","keyword":["coldboot"],"publisher":"IEEE","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","date_created":"2017-10-17T12:42:35Z","status":"public","has_accepted_license":"1","_id":"528","page":"386-389","year":"2013","type":"conference","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389."}},{"user_id":"24135","title":"MCD: Overcoming the Data Download Bottleneck in Data Centers","place":"Washington DC, USA","date_created":"2018-03-26T14:43:38Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","author":[{"last_name":"Kaiser","first_name":"Jürgen","full_name":"Kaiser, Jürgen"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"full_name":"Gottfried, Viktor","first_name":"Viktor","last_name":"Gottfried"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publisher":"IEEE Computer Society","doi":"10.1109/NAS.2013.18","_id":"1784","date_updated":"2022-01-06T06:53:20Z","page":"88-97","year":"2013","type":"conference","citation":{"short":"J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97.","ieee":"J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. 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Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.","mla":"Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.","bibtex":"@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers}, DOI={10.1109/NAS.2013.18}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }"}},{"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","language":[{"iso":"eng"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"505","citation":{"bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"year":"2013","type":"conference","user_id":"15278","ddc":["040"],"abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"date_created":"2017-10-17T12:42:30Z","status":"public","has_accepted_license":"1","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-15T13:38:56Z","content_type":"application/pdf","file_id":"1308","creator":"florida","file_size":1040834,"access_level":"closed","file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","publisher":"IEEE","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"last_name":"Kling","full_name":"Kling, Peter","first_name":"Peter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","id":"15523"}],"quality_controlled":"1"},{"publication_identifier":{"isbn":["978-0-7695-4979-8"]},"date_created":"2018-03-26T14:51:05Z","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"status":"public","publication":"Proc. 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