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(SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }"},"type":"conference","doi":"10.1109/SIU.2013.6531530","date_updated":"2022-01-06T06:53:20Z","_id":"1786"},{"citation":{"bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389."},"type":"conference","year":"2013","page":"386-389","_id":"528","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:35Z","file":[{"date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file","file_size":822680,"file_id":"1294","creator":"florida","access_level":"closed","date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf"}],"author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-15T10:36:08Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","keyword":["coldboot"],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"language":[{"iso":"eng"}],"doi":"10.1109/FPT.2013.6718394","date_updated":"2023-09-26T13:37:35Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES"},{"page":"88-97","type":"conference","year":"2013","citation":{"mla":"Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. 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After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas."}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:30Z","publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"quality_controlled":"1","file_date_updated":"2018-03-15T13:38:56Z","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","success":1,"relation":"main_file","file_size":1040834,"file_id":"1308","creator":"florida","access_level":"closed","date_created":"2018-03-15T13:38:56Z","file_name":"505-Plessl13_seus.pdf"}],"_id":"505","type":"conference","year":"2013","citation":{"ieee":"M. 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A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.","ieee":"R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.","short":"R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012."}},{"title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","user_id":"24135","author":[{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"full_name":"Kacsuk, Peter","first_name":"Peter","last_name":"Kacsuk"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"last_name":"Steinke","full_name":"Steinke, Thomas","first_name":"Thomas"}],"publication":"Proceedings of Science","department":[{"_id":"27"}],"volume":"PoS(EGICF12-EMITC2)050","status":"public","date_created":"2018-04-03T09:15:35Z","date_updated":"2022-01-06T06:55:13Z","_id":"2178","type":"conference","citation":{"ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050.","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050)."},"year":"2012"},{"status":"public","date_created":"2018-03-29T14:41:55Z","author":[{"full_name":"Meister, Dirk","first_name":"Dirk","last_name":"Meister"},{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Kuhn","first_name":"Michael","full_name":"Kuhn, Michael"},{"last_name":"Kunkel","full_name":"Kunkel, Julian","first_name":"Julian"},{"first_name":"Toni","full_name":"Cortes, Toni","last_name":"Cortes"}],"publisher":"IEEE Computer Society","publication":"Proc. Int. Conf. on Supercomputing (SC)","department":[{"_id":"27"}],"user_id":"24135","title":"A Study on Data Deduplication in HPC Storage Systems","place":"Los Alamitos, CA, USA","type":"conference","citation":{"apa":"Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14","ama":"Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14","chicago":"Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.","bibtex":"@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }","mla":"Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14.","short":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.","ieee":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11."},"year":"2012","page":"7:1-7:11","doi":"10.1109/SC.2012.14","_id":"2099","date_updated":"2022-01-06T06:54:42Z"},{"page":"91-99","citation":{"mla":"Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.","bibtex":"@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }","ama":"Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143","apa":"Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143","chicago":"Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.","ieee":"M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.","short":"M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99."},"year":"2012","type":"conference","_id":"2103","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/CIG.2012.6374143","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Conf. on Computational Intelligence and Games (CIG)","publisher":"IEEE","author":[{"last_name":"Wistuba","full_name":"Wistuba, Martin","first_name":"Martin"},{"full_name":"Schaefers, Lars","first_name":"Lars","last_name":"Schaefers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2018-03-29T14:59:35Z","status":"public","title":"Comparison of Bayesian Move Prediction Systems for Computer Go","user_id":"24135"},{"status":"public","has_accepted_license":"1","date_created":"2018-03-29T15:04:25Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"158","last_name":"Förstner","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","first_name":"Jens"}],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file_date_updated":"2019-02-13T09:04:46Z","file":[{"date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","access_level":"closed","file_size":2148787,"creator":"fossie","file_id":"7638","date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","relation":"main_file","success":1}],"ddc":["000"],"user_id":"15278","abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"type":"conference","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }"},"year":"2012","page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:39:13Z"},{"publication":"Proc. Symp. on Mass Storage Systems and Technologies (MSST)","department":[{"_id":"27"}],"publisher":"IEEE","author":[{"full_name":"Kaiser, Jürgen","first_name":"Jürgen","last_name":"Kaiser"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Effert","full_name":"Effert, Sascha","first_name":"Sascha"}],"date_created":"2018-03-26T15:12:01Z","status":"public","title":"Design of an exact data deduplication cluster","user_id":"24135","page":"1-12","year":"2012","type":"conference","citation":{"chicago":"Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380.","apa":"Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380","ama":"Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380","mla":"Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12, doi:10.1109/MSST.2012.6232380.","bibtex":"@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha}, year={2012}, pages={1–12} }","short":"J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.","ieee":"J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2012, pp. 1–12."},"_id":"1789","date_updated":"2022-01-06T06:53:22Z","doi":"10.1109/MSST.2012.6232380"},{"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices."}],"user_id":"15278","ddc":["040"],"file":[{"creator":"florida","file_id":"1246","file_size":730144,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z","access_level":"closed"}],"author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Hangmann","full_name":"Hangmann, Hendrik","first_name":"Hendrik"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:51Z","_id":"615","year":"2012","type":"conference","citation":{"mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"page":"1-8"},{"date_created":"2018-03-29T14:40:04Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","publisher":"IEEE","author":[{"full_name":"Kaiser, Jürgen","first_name":"Jürgen","last_name":"Kaiser"},{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Hartung","first_name":"Tim","full_name":"Hartung, Tim"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"user_id":"24135","title":"ESB: Ext2 Split Block Device","page":"181-188","type":"conference","year":"2012","citation":{"short":"J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.","ieee":"J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.","ama":"Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34","apa":"Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34","chicago":"Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.","bibtex":"@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }","mla":"Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34."},"doi":"10.1109/ICPADS.2012.34","date_updated":"2022-01-06T06:54:42Z","_id":"2098"},{"page":"559-562","year":"2012","type":"conference","citation":{"mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562."},"_id":"612","date_created":"2017-10-17T12:42:51Z","status":"public","has_accepted_license":"1","file":[{"file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","access_level":"closed","file_size":202923,"file_id":"1247","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","author":[{"last_name":"Rüthing","first_name":"Christoph","full_name":"Rüthing, Christoph"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"language":[{"iso":"eng"}],"doi":"10.1109/FPL.2012.6339370","date_updated":"2023-09-26T13:42:03Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs"},{"title":"FPGA implementation of a second-order convolutive blind signal separation algorithm","user_id":"24135","date_created":"2018-03-29T14:43:18Z","status":"public","department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"full_name":"Redif, Soydan","first_name":"Soydan","last_name":"Redif"}],"date_updated":"2022-01-06T06:54:42Z","_id":"2100","type":"conference","citation":{"short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }"},"year":"2012"},{"doi":"10.1109/FPT.2012.6412125","_id":"2097","date_updated":"2022-01-06T06:54:42Z","type":"conference","citation":{"short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140.","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125."},"year":"2012","page":"135-140","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","status":"public","date_created":"2018-03-29T14:34:48Z","publisher":"IEEE Computer Society","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)"},{"year":"2012","type":"conference","citation":{"chicago":"Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer, Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum, 2012.","apa":"Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn, R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways via Virtual Organizations. In Proc. EGI Technical Forum.","ama":"Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.","mla":"Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via Virtual Organizations.” Proc. EGI Technical Forum, 2012.","bibtex":"@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012, title={Generic User Management for Science Gateways via Virtual Organizations}, booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke, Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn, Ralph and Kohlbacher, Oliver}, year={2012} }","short":"T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.","ieee":"T. Schlemmer et al., “Generic User Management for Science Gateways via Virtual Organizations,” in Proc. EGI Technical Forum, 2012."},"_id":"2104","date_updated":"2022-01-06T06:54:42Z","department":[{"_id":"27"}],"publication":"Proc. EGI Technical Forum","author":[{"last_name":"Schlemmer","full_name":"Schlemmer, Tobias","first_name":"Tobias"},{"last_name":"Grunzke","first_name":"Richard","full_name":"Grunzke, Richard"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"full_name":"Krüger, Jens","first_name":"Jens","last_name":"Krüger"},{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"}],"date_created":"2018-03-29T15:00:48Z","status":"public","user_id":"24135","title":"Generic User Management for Science Gateways via Virtual Organizations"},{"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:50Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file":[{"file_size":146789,"file_id":"1249","creator":"florida","date_updated":"2018-03-15T08:14:17Z","content_type":"application/pdf","success":1,"relation":"main_file","date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf","access_level":"closed"}],"_id":"609","citation":{"ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012."},"type":"conference","year":"2012","page":"8-9","title":"Hardware/Software Platform for Self-aware Compute Nodes","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"date_updated":"2023-09-26T13:41:36Z","language":[{"iso":"eng"}]},{"publication":"Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)","department":[{"_id":"27"}],"author":[{"last_name":"Congiu","first_name":"Giuseppe","full_name":"Congiu, Giuseppe"},{"last_name":"Grawinkel","first_name":"Matthias","full_name":"Grawinkel, Matthias"},{"last_name":"Narasimhamurthy","full_name":"Narasimhamurthy, Sai","first_name":"Sai"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publisher":"IEEE","date_created":"2018-03-29T15:02:15Z","status":"public","user_id":"24135","title":"One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services","page":"16-24","citation":{"short":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24.","ieee":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,” in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 2012, pp. 16–24.","chicago":"Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.","apa":"Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012). One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16","ama":"Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS). IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16","bibtex":"@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services}, DOI={10.1109/ClusterW.2012.16}, booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }","mla":"Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24, doi:10.1109/ClusterW.2012.16."},"type":"conference","year":"2012","_id":"2105","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/ClusterW.2012.16"},{"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"date_created":"2017-10-17T12:42:47Z","status":"public","has_accepted_license":"1","file":[{"file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z","access_level":"closed","file_size":371235,"file_id":"1257","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","success":1,"relation":"main_file"}],"file_date_updated":"2018-03-15T08:33:18Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Schmitz","full_name":"Schmitz, Henning","first_name":"Henning"}],"_id":"591","page":"1-8","year":"2012","type":"conference","citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773"}},{"project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"date_created":"2018-04-03T09:18:33Z","status":"public","keyword":["funding-enhance"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","quality_controlled":"1","author":[{"last_name":"Beisel","first_name":"Tobias","full_name":"Beisel, Tobias"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","user_id":"15278","type":"conference","citation":{"short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012."},"year":"2012","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:40:17Z","_id":"2180"},{"year":"2012","type":"conference","citation":{"short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012.","ieee":"S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From National to International Scale. In: Proc. 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EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","mla":"Gesing, Sandra, et al. “The MoSGrid Community From National to International Scale.” Proc. EGI Community Forum, 2012."},"date_updated":"2022-01-06T06:55:11Z","_id":"2171","date_created":"2018-04-03T09:01:19Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. 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In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"ddc":["040"],"user_id":"15278","citation":{"ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. 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During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds.","lang":"eng"}],"language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","short":"O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. 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IEEE Computer Society. https://doi.org/10.1109/mascots.2011.13","ama":"Grawinkel M, Schäfer T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society; 2011:297-306. doi:10.1109/mascots.2011.13","ieee":"M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, and M. Porrmann, “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability,” in Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, pp. 297–306.","short":"M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, M. Porrmann, in: Proc. Int. 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Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 380–387). IEEE. https://doi.org/10.1109/ICPADS.2011.77","ama":"Grawinkel M, Pargmann M, Dömer H, Brinkmann A. Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77","bibtex":"@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }","mla":"Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77."},"page":"380-387","date_updated":"2022-01-06T06:55:18Z","_id":"2189","doi":"10.1109/ICPADS.2011.77","author":[{"full_name":"Grawinkel, Matthias","first_name":"Matthias","last_name":"Grawinkel"},{"last_name":"Pargmann","first_name":"Markus","full_name":"Pargmann, Markus"},{"last_name":"Dömer","full_name":"Dömer, Hubert","first_name":"Hubert"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"IEEE","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","status":"public","date_created":"2018-04-03T14:32:23Z","title":"Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System","user_id":"24135"},{"_id":"656","citation":{"short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). 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Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59."},"year":"2011","type":"conference","page":"55-60","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:59Z","file":[{"relation":"main_file","success":1,"date_updated":"2018-03-14T13:49:39Z","content_type":"application/pdf","file_id":"1220","creator":"florida","file_size":502244,"access_level":"closed","date_created":"2018-03-14T13:49:39Z","file_name":"656-2011_happe_reconfig.pdf"}],"publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","file_date_updated":"2018-03-14T13:49:39Z","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","doi":"10.1109/ReConFig.2011.59","date_updated":"2023-09-26T13:46:08Z","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"author":[{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Blunk","first_name":"Dirk","full_name":"Blunk, Dirk"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"first_name":"Ulrich","full_name":"Lang, Ulrich","last_name":"Lang"},{"full_name":"Packschies, Lars","first_name":"Lars","last_name":"Packschies"},{"last_name":"Müller-Pfefferkorn","full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"last_name":"Schuster","full_name":"Schuster, Johannes","first_name":"Johannes"},{"last_name":"Steinke","full_name":"Steinke, Thomas","first_name":"Thomas"},{"last_name":"Warzecha","full_name":"Warzecha, Klaus-Dieter","first_name":"Klaus-Dieter"},{"last_name":"Wewior","full_name":"Wewior, Martin","first_name":"Martin"}],"publication":"Proc. of Grid Workflow Workshop (GWW)","department":[{"_id":"27"}],"volume":829,"status":"public","date_created":"2018-04-04T09:34:24Z","title":"MoSGrid: Progress of Workflow driven Chemical Simulations","user_id":"24135","series_title":"CEUR Workshop Proceedings","year":"2011","type":"conference","citation":{"apa":"Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Fels, G., Gesing, S., … Wewior, M. (2011). MoSGrid: Progress of Workflow driven Chemical Simulations. In Proc. of Grid Workflow Workshop (GWW) (Vol. 829).","ama":"Birkenheuer G, Blunk D, Breuers S, et al. MoSGrid: Progress of Workflow driven Chemical Simulations. In: Proc. of Grid Workflow Workshop (GWW). Vol 829. CEUR Workshop Proceedings. ; 2011.","chicago":"Birkenheuer, Georg, Dirk Blunk, Sebastian Breuers, André Brinkmann, Gregor Fels, Sandra Gesing, Richard Grunzke, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” In Proc. of Grid Workflow Workshop (GWW), Vol. 829. CEUR Workshop Proceedings, 2011.","bibtex":"@inproceedings{Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Gesing_Grunzke_Herres-Pawlis_Kohlbacher_Krüger_et al._2011, series={CEUR Workshop Proceedings}, title={MoSGrid: Progress of Workflow driven Chemical Simulations}, volume={829}, booktitle={Proc. of Grid Workflow Workshop (GWW)}, author={Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Gesing, Sandra and Grunzke, Richard and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and et al.}, year={2011}, collection={CEUR Workshop Proceedings} }","mla":"Birkenheuer, Georg, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” Proc. of Grid Workflow Workshop (GWW), vol. 829, 2011.","short":"G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Gesing, R. Grunzke, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, U. Lang, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, J. Schuster, T. Steinke, K.-D. Warzecha, M. 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Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in Proc. European Conf. on Parallel Processing (Euro-Par), 2011, vol. 6853.","short":"T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.","mla":"Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36.","bibtex":"@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={10.1007/978-3-642-23397-5_36}, booktitle={Proc. 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Washington, DC: IEEE Computer Society; 2011:1-10. doi:10.1109/HiPC.2011.6152745","chicago":"Miranda, Alberto, Sascha Effert, Yangwook Kang, Ethan Miller, André Brinkmann, and Toni Cortes. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” In Proc. Int. Conf. on High Performance Computing (HIPC), 1–10. Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745.","bibtex":"@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }","mla":"Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745."},"year":"2011","type":"conference","date_updated":"2022-01-06T06:55:18Z","_id":"2188","doi":"10.1109/HiPC.2011.6152745"},{"_id":"2196","date_updated":"2022-01-06T06:55:21Z","doi":"10.1109/NAS.2011.25","citation":{"ieee":"A. Brinkmann, Y. Gao, M. Korzeniowski, and D. Meister, “Request Load Balancing for Highly Skewed Traffic in P2P Networks,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2011, pp. 53–62.","short":"A. Brinkmann, Y. Gao, M. Korzeniowski, D. Meister, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62.","bibtex":"@inproceedings{Brinkmann_Gao_Korzeniowski_Meister_2011, title={Request Load Balancing for Highly Skewed Traffic in P2P Networks}, DOI={10.1109/NAS.2011.25}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE}, author={Brinkmann, André and Gao, Yan and Korzeniowski, Miroslaw and Meister, Dirk}, year={2011}, pages={53–62} }","mla":"Brinkmann, André, et al. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62, doi:10.1109/NAS.2011.25.","chicago":"Brinkmann, André, Yan Gao, Miroslaw Korzeniowski, and Dirk Meister. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 53–62. IEEE, 2011. https://doi.org/10.1109/NAS.2011.25.","ama":"Brinkmann A, Gao Y, Korzeniowski M, Meister D. Request Load Balancing for Highly Skewed Traffic in P2P Networks. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). IEEE; 2011:53-62. doi:10.1109/NAS.2011.25","apa":"Brinkmann, A., Gao, Y., Korzeniowski, M., & Meister, D. (2011). Request Load Balancing for Highly Skewed Traffic in P2P Networks. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 53–62). IEEE. https://doi.org/10.1109/NAS.2011.25"},"type":"conference","year":"2011","page":"53-62","user_id":"24135","title":"Request Load Balancing for Highly Skewed Traffic in P2P Networks","author":[{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"first_name":"Yan","full_name":"Gao, Yan","last_name":"Gao"},{"full_name":"Korzeniowski, Miroslaw","first_name":"Miroslaw","last_name":"Korzeniowski"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"}],"publisher":"IEEE","publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","department":[{"_id":"27"}],"status":"public","date_created":"2018-04-03T15:03:17Z"},{"language":[{"iso":"eng"}],"year":"2011","type":"conference","citation":{"chicago":"Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69.","apa":"Kleineweber, C., Keller, A., Niehörster, O., & Brinkmann, A. (2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69","ama":"Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69","bibtex":"@inproceedings{Kleineweber_Keller_Niehörster_Brinkmann_2011, title={Rule Based Mapping of Virtual Machines in Clouds}, DOI={10.1109/PDP.2011.69}, booktitle={Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)}, author={Kleineweber, Christoph and Keller, Axel and Niehörster, Oliver and Brinkmann, André}, year={2011} }","mla":"Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011, doi:10.1109/PDP.2011.69.","short":"C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011.","ieee":"C. Kleineweber, A. Keller, O. Niehörster, and A. Brinkmann, “Rule Based Mapping of Virtual Machines in Clouds,” in Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011."},"date_updated":"2022-01-06T06:54:10Z","_id":"1968","doi":"10.1109/PDP.2011.69","author":[{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"last_name":"Keller","id":"15274","first_name":"Axel","full_name":"Keller, Axel"},{"last_name":"Niehörster","first_name":"Oliver","full_name":"Niehörster, Oliver"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)","status":"public","date_created":"2018-03-29T11:21:05Z","publication_status":"published","abstract":[{"text":"Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.","lang":"eng"}],"user_id":"15274","title":"Rule Based Mapping of Virtual Machines in Clouds"},{"title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","user_id":"15278","keyword":["tet_topic_hpc"],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Jens","full_name":"Förstner, Jens","orcid":"0000-0001-7059-9862","last_name":"Förstner","id":"158"}],"quality_controlled":"1","publisher":"IEEE Computer Society","date_created":"2018-04-03T14:55:57Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","date_updated":"2023-09-26T13:44:11Z","_id":"2194","doi":"10.1109/SAAHPC.2011.12","page":"60-63","type":"conference","citation":{"bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12","apa":"Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.","ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.","short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63."},"year":"2011","language":[{"iso":"eng"}]},{"_id":"2224","date_updated":"2023-09-26T13:48:59Z","language":[{"iso":"eng"}],"year":"2010","citation":{"chicago":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010.","ama":"Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.","apa":"Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150.","bibtex":"@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }","mla":"Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50.","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.","ieee":"M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. 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Berenbrink, A. Brinkmann, T. Friedetzky, and L. Nagel, “Balls into Bins with Related Random Choices,” in Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 2010, pp. 100–105.","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., & Nagel, L. (2010). Balls into Bins with Related Random Choices. In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) (pp. 100–105). New York: ACM. https://doi.org/10.1145/1810479.1810500","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Nagel L. Balls into Bins with Related Random Choices. In: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA). New York: ACM; 2010:100-105. doi:10.1145/1810479.1810500","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, and Lars Nagel. “Balls into Bins with Related Random Choices.” In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 100–105. New York: ACM, 2010. https://doi.org/10.1145/1810479.1810500.","mla":"Berenbrink, Petra, et al. “Balls into Bins with Related Random Choices.” Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, 2010, pp. 100–05, doi:10.1145/1810479.1810500.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Nagel_2010, place={New York}, title={Balls into Bins with Related Random Choices}, DOI={10.1145/1810479.1810500}, booktitle={Proc. Int. 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