[{"status":"public","date_created":"2018-03-23T14:09:33Z","publisher":"ACM","author":[{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"first_name":"J.","full_name":"T. Anderson, J.","last_name":"T. Anderson"},{"full_name":"Borga, A.","first_name":"A.","last_name":"Borga"},{"last_name":"Boterenbrood","first_name":"H.","full_name":"Boterenbrood, H."},{"full_name":"Chen, H.","first_name":"H.","last_name":"Chen"},{"full_name":"Chen, K.","first_name":"K.","last_name":"Chen"},{"last_name":"Drake","first_name":"G.","full_name":"Drake, G."},{"last_name":"Francis","full_name":"Francis, D.","first_name":"D."},{"last_name":"Gorini","first_name":"B.","full_name":"Gorini, B."},{"first_name":"F.","full_name":"Lanni, F.","last_name":"Lanni"},{"full_name":"Lehmann-Miotto, Giovanna","first_name":"Giovanna","last_name":"Lehmann-Miotto"},{"last_name":"Levinson","first_name":"L.","full_name":"Levinson, L."},{"last_name":"Narevicius","first_name":"J.","full_name":"Narevicius, J."},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Roich, A.","first_name":"A.","last_name":"Roich"},{"last_name":"Ryu","full_name":"Ryu, S.","first_name":"S."},{"last_name":"P. Schreuder","full_name":"P. Schreuder, F.","first_name":"F."},{"full_name":"Vandelli, Wainer","first_name":"Wainer","last_name":"Vandelli"},{"last_name":"Vermeulen","first_name":"J.","full_name":"Vermeulen, J."},{"first_name":"J.","full_name":"Zhang, J.","last_name":"Zhang"}],"quality_controlled":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)","title":"Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm","user_id":"15278","type":"conference","year":"2015","citation":{"chicago":"Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.","apa":"Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824","ama":"Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824","mla":"Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.","bibtex":"@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }","short":"J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.","ieee":"J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824."},"language":[{"iso":"eng"}],"doi":"10.1145/2675743.2771824","_id":"1773","date_updated":"2023-09-26T13:31:01Z"},{"file_date_updated":"2018-03-21T10:29:49Z","publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","publisher":"EDA Consortium / IEEE","quality_controlled":"1","author":[{"last_name":"Damschen","first_name":"Marvin","full_name":"Damschen, Marvin"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","last_name":"Riebler","id":"8961"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"file":[{"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-21T10:29:49Z","file_id":"1500","creator":"florida","file_size":380552,"access_level":"closed","date_created":"2018-03-21T10:29:49Z","file_name":"238-plessl15_date.pdf"}],"date_created":"2017-10-17T12:41:38Z","status":"public","has_accepted_license":"1","abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"ddc":["040"],"user_id":"15278","page":"1078-1083","citation":{"bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.","apa":"Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124","ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083."},"type":"conference","year":"2015","_id":"238","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:31:44Z","doi":"10.7873/DATE.2015.1124"},{"doi":"10.1007/978-3-319-09063-4_19","date_updated":"2022-01-06T06:53:20Z","_id":"1781","year":"2014","citation":{"ieee":"T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.","short":"T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.","bibtex":"@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }","mla":"Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.","apa":"Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19","ama":"Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19","chicago":"Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19."},"type":"conference","page":"233-243","title":"Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres","user_id":"24135","abstract":[{"lang":"eng","text":"In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment."}],"editor":[{"last_name":"Bock","full_name":"Bock, Hans Georg","first_name":"Hans Georg"},{"full_name":"Hoang, Xuan Phu","first_name":"Xuan Phu","last_name":"Hoang"},{"full_name":"Rannacher, Rolf","first_name":"Rolf","last_name":"Rannacher"},{"full_name":"Schlöder, Johannes P.","first_name":"Johannes P.","last_name":"Schlöder"}],"publication_identifier":{"isbn":["978-3-319-09063-4"]},"status":"public","date_created":"2018-03-26T13:47:16Z","publisher":"Springer International Publishing","author":[{"last_name":"Steinle","first_name":"Tobias","full_name":"Steinle, Tobias"},{"last_name":"Vrabec","first_name":"Jadran","full_name":"Vrabec, Jadran"},{"full_name":"Walther, Andrea","first_name":"Andrea","last_name":"Walther"}],"department":[{"_id":"27"},{"_id":"104"},{"_id":"155"}],"publication":"Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)"},{"type":"conference","year":"2014","citation":{"ama":"Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2","apa":"Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2","chicago":"Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.","bibtex":"@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }","mla":"Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.","short":"T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.","ieee":"T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25."},"page":"14-25","series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-319-09165-5_2","issue":"8427","_id":"1782","date_updated":"2022-01-06T06:53:20Z","status":"public","date_created":"2018-03-26T13:50:37Z","publisher":"Springer","author":[{"full_name":"Graf, Tobias","first_name":"Tobias","last_name":"Graf"},{"full_name":"Schaefers, Lars","first_name":"Lars","last_name":"Schaefers"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publication":"Proc. Conf. on Computers and Games (CG)","department":[{"_id":"27"},{"_id":"78"}],"title":"On Semeai Detection in Monte-Carlo Go","user_id":"24135","place":"Switzerland"},{"date_updated":"2023-09-26T13:34:08Z","doi":"10.1007/978-3-319-05960-0_13","series_title":"Lecture Notes in Computer Science (LNCS)","language":[{"iso":"eng"}],"place":"Cham","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"_id":"388","intvolume":" 8405","page":"144-155","year":"2014","citation":{"ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","apa":"Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13."},"type":"conference","abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"access_level":"closed","file_name":"388-plessl14_arc.pdf","date_created":"2018-03-20T07:02:02Z","success":1,"relation":"main_file","date_updated":"2018-03-20T07:02:02Z","content_type":"application/pdf","creator":"florida","file_id":"1387","file_size":330193}],"file_date_updated":"2018-03-20T07:02:02Z","publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","quality_controlled":"1","publisher":"Springer International Publishing","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Vaz","id":"30332","first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"date_created":"2017-10-17T12:42:07Z","has_accepted_license":"1","status":"public","volume":8405},{"date_updated":"2023-09-26T13:33:50Z","doi":"10.1109/FCCM.2014.67","language":[{"iso":"eng"}],"title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"_id":"377","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67","apa":"Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229."},"type":"conference","year":"2014","page":"222-229","abstract":[{"lang":"eng","text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates."}],"user_id":"15278","ddc":["040"],"file":[{"file_name":"377-FCCM14.pdf","date_created":"2018-03-20T07:14:20Z","access_level":"closed","file_id":"1397","creator":"florida","file_size":1003907,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-20T07:14:20Z"}],"quality_controlled":"1","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Sorge","full_name":"Sorge, Christoph","first_name":"Christoph"}],"publisher":"IEEE","keyword":["coldboot"],"file_date_updated":"2018-03-20T07:14:20Z","publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:05Z"},{"user_id":"15278","title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"C. Durelli","full_name":"C. Durelli, Gianluca","first_name":"Gianluca"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"D. Santambrogio","first_name":"Marco","full_name":"D. Santambrogio, Marco"},{"last_name":"Bolchini","first_name":"Cristiana","full_name":"Bolchini, Cristiana"}],"date_created":"2018-03-26T13:40:14Z","project":[{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"status":"public","_id":"1778","date_updated":"2023-09-26T13:35:40Z","doi":"10.1109/ISPA.2014.27","language":[{"iso":"eng"}],"page":"142-149","type":"conference","year":"2014","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27","ieee":"G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149."}},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:37:02Z","doi":"10.1109/ReConFig.2014.7032509","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"title":"Deferring Accelerator Offloading Decisions to Application Runtime","type":"conference","citation":{"ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509","apa":"Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509"},"year":"2014","page":"1-8","_id":"439","author":[{"id":"30332","last_name":"Vaz","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"},{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-16T11:29:52Z","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file":[{"creator":"florida","file_id":"1353","file_size":557362,"relation":"main_file","success":1,"date_updated":"2018-03-16T11:29:52Z","content_type":"application/pdf","date_created":"2018-03-16T11:29:52Z","file_name":"439-plessl14a_reconfig.pdf","access_level":"closed"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:17Z","abstract":[{"lang":"eng","text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes."}],"ddc":["040"],"user_id":"15278"},{"title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/ReConFig.2014.7032535","date_updated":"2023-09-26T13:36:40Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design."}],"date_created":"2017-10-17T12:42:11Z","status":"public","has_accepted_license":"1","file":[{"content_type":"application/pdf","date_updated":"2018-03-16T11:37:42Z","success":1,"relation":"main_file","file_size":932852,"file_id":"1366","creator":"florida","access_level":"closed","date_created":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-16T11:37:42Z","quality_controlled":"1","author":[{"last_name":"Kenter","id":"3145","first_name":"Tobias","full_name":"Kenter, Tobias"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","_id":"406","page":"1-8","type":"conference","citation":{"short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.","chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535","apa":"Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535."},"year":"2014"},{"doi":"10.1007/978-3-319-05960-0_38","_id":"1780","date_updated":"2023-09-26T13:36:20Z","citation":{"bibtex":"@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }","mla":"C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.","ama":"C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38","apa":"C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38","chicago":"C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.","ieee":"G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.","short":"G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014."},"type":"conference","year":"2014","language":[{"iso":"eng"}],"title":"SAVE: Towards efficient resource management in heterogeneous system architectures","user_id":"15278","status":"public","date_created":"2018-03-26T13:45:35Z","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"publisher":"Springer","quality_controlled":"1","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"first_name":"Marcello","full_name":"Copolla, Marcello","last_name":"Copolla"},{"last_name":"Djafarian","full_name":"Djafarian, Karim","first_name":"Karim"},{"last_name":"Koranaros","full_name":"Koranaros, George","first_name":"George"},{"full_name":"Miele, Antonio","first_name":"Antonio","last_name":"Miele"},{"full_name":"Paolino, Michele","first_name":"Michele","last_name":"Paolino"},{"first_name":"Oliver","full_name":"Pell, Oliver","last_name":"Pell"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"D. Santambrogio, Marco","first_name":"Marco","last_name":"D. Santambrogio"},{"first_name":"Cristiana","full_name":"Bolchini, Cristiana","last_name":"Bolchini"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)"},{"place":"Washington DC, USA","user_id":"24135","title":"MCD: Overcoming the Data Download Bottleneck in Data Centers","publisher":"IEEE Computer Society","author":[{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"first_name":"Viktor","full_name":"Gottfried, Viktor","last_name":"Gottfried"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-26T14:43:38Z","_id":"1784","date_updated":"2022-01-06T06:53:20Z","doi":"10.1109/NAS.2013.18","year":"2013","citation":{"bibtex":"@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers}, DOI={10.1109/NAS.2013.18}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }","mla":"Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.","chicago":"Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.","apa":"Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/NAS.2013.18","ama":"Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97. doi:10.1109/NAS.2013.18","ieee":"J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2013, pp. 88–97.","short":"J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97."},"type":"conference","page":"88-97"},{"year":"2013","citation":{"short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013.","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }"},"type":"conference","doi":"10.1109/SIU.2013.6531530","_id":"1786","date_updated":"2022-01-06T06:53:20Z","status":"public","date_created":"2018-03-26T14:48:53Z","publisher":"IEEE","author":[{"last_name":"Kasap","full_name":"Kasap, Server","first_name":"Server"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","user_id":"24135","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm"},{"citation":{"mla":"Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148.","ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013."},"year":"2013","type":"conference","date_updated":"2022-01-06T06:53:22Z","_id":"1788","doi":"10.1109/IPDPSW.2013.148","department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","author":[{"last_name":"Berenbrink","first_name":"Petra","full_name":"Berenbrink, Petra"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Friedetzky","full_name":"Friedetzky, Tom","first_name":"Tom"},{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"first_name":"Lars","full_name":"Nagel, Lars","last_name":"Nagel"}],"publisher":"IEEE","date_created":"2018-03-26T14:52:56Z","status":"public","user_id":"24135","title":"Distributing Storage in Cloud Environments"},{"_id":"1793","date_updated":"2022-01-06T06:53:23Z","year":"2013","citation":{"ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.","short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182."},"type":"conference","page":"175-182","user_id":"24135","title":"File Recipe Compression in Data Deduplication Systems","author":[{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"}],"publisher":"USENIX Association","publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-26T15:16:03Z"},{"date_updated":"2023-09-26T13:37:35Z","doi":"10.1109/FPT.2013.6718394","language":[{"iso":"eng"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"_id":"528","type":"conference","year":"2013","citation":{"short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }"},"page":"386-389","abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"ddc":["040"],"user_id":"15278","publisher":"IEEE","author":[{"full_name":"Riebler, Heinrich","first_name":"Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"last_name":"Sorge","first_name":"Christoph","full_name":"Sorge, Christoph"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"quality_controlled":"1","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","file_date_updated":"2018-03-15T10:36:08Z","keyword":["coldboot"],"file":[{"access_level":"closed","date_created":"2018-03-15T10:36:08Z","file_name":"528-plessl13_fpt.pdf","date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","relation":"main_file","success":1,"file_size":822680,"file_id":"1294","creator":"florida"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:35Z"},{"language":[{"iso":"eng"}],"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","type":"conference","year":"2013","citation":{"mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013."},"_id":"505","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:30Z","quality_controlled":"1","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"publisher":"IEEE","publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","file":[{"file_id":"1308","creator":"florida","file_size":1040834,"success":1,"relation":"main_file","date_updated":"2018-03-15T13:38:56Z","content_type":"application/pdf","file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z","access_level":"closed"}],"ddc":["040"],"user_id":"15278","abstract":[{"lang":"eng","text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas."}]},{"_id":"1787","date_updated":"2023-09-26T13:38:05Z","doi":"10.1109/IPDPSW.2013.136","language":[{"iso":"eng"}],"page":"64-73","year":"2013","type":"conference","citation":{"short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136."},"place":"Washington, DC, USA","user_id":"15278","title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Suess","first_name":"Tim","full_name":"Suess, Tim"},{"first_name":"Andrew","full_name":"Schoenrock, Andrew","last_name":"Schoenrock"},{"last_name":"Meisner","first_name":"Sebastian","full_name":"Meisner, Sebastian"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2018-03-26T14:51:05Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","publication_identifier":{"isbn":["978-0-7695-4979-8"]}},{"date_created":"2018-03-29T14:34:48Z","status":"public","publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","department":[{"_id":"27"},{"_id":"78"}],"author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"last_name":"Redif","first_name":"Soydan","full_name":"Redif, Soydan"}],"publisher":"IEEE Computer Society","title":"FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm","user_id":"24135","page":"135-140","type":"conference","citation":{"ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140.","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125."},"year":"2012","doi":"10.1109/FPT.2012.6412125","date_updated":"2022-01-06T06:54:42Z","_id":"2097"},{"status":"public","date_created":"2018-03-29T14:40:04Z","publisher":"IEEE","author":[{"first_name":"Jürgen","full_name":"Kaiser, Jürgen","last_name":"Kaiser"},{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Hartung","full_name":"Hartung, Tim","first_name":"Tim"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","user_id":"24135","title":"ESB: Ext2 Split Block Device","year":"2012","type":"conference","citation":{"bibtex":"@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }","mla":"Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.","chicago":"Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.","ama":"Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34","apa":"Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34","ieee":"J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.","short":"J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188."},"page":"181-188","doi":"10.1109/ICPADS.2012.34","date_updated":"2022-01-06T06:54:42Z","_id":"2098"},{"citation":{"ama":"Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14","apa":"Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14","chicago":"Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.","bibtex":"@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }","mla":"Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14.","short":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.","ieee":"D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11."},"type":"conference","year":"2012","page":"7:1-7:11","_id":"2099","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/SC.2012.14","publisher":"IEEE Computer Society","author":[{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"last_name":"Kaiser","first_name":"Jürgen","full_name":"Kaiser, Jürgen"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"full_name":"Kuhn, Michael","first_name":"Michael","last_name":"Kuhn"},{"last_name":"Kunkel","first_name":"Julian","full_name":"Kunkel, Julian"},{"last_name":"Cortes","first_name":"Toni","full_name":"Cortes, Toni"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Supercomputing (SC)","status":"public","date_created":"2018-03-29T14:41:55Z","place":"Los Alamitos, CA, USA","title":"A Study on Data Deduplication in HPC Storage Systems","user_id":"24135"},{"_id":"2100","date_updated":"2022-01-06T06:54:42Z","type":"conference","year":"2012","citation":{"ama":"Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.","apa":"Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG).","chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012.","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012.","short":"S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.","ieee":"S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012."},"title":"FPGA implementation of a second-order convolutive blind signal separation algorithm","user_id":"24135","department":[{"_id":"27"},{"_id":"78"}],"publication":"Int. Architecture and Engineering Symp. (ARCHENG)","author":[{"full_name":"Kasap, Server","first_name":"Server","last_name":"Kasap"},{"first_name":"Soydan","full_name":"Redif, Soydan","last_name":"Redif"}],"date_created":"2018-03-29T14:43:18Z","status":"public"},{"_id":"2101","date_updated":"2022-01-06T06:54:42Z","doi":"10.1109/SC.Companion.2012.13","page":"13-17","citation":{"apa":"Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW) (pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13","ama":"Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17. doi:10.1109/SC.Companion.2012.13","chicago":"Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann. “Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop (PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13.","bibtex":"@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13}, booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel, Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012}, pages={13–17} }","mla":"Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13.","short":"M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17.","ieee":"M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW), 2012, pp. 13–17."},"year":"2012","type":"conference","title":"Towards Dynamic Scripted pNFS Layouts","user_id":"24135","publication":"Proc. Parallel Data Storage Workshop (PDSW)","department":[{"_id":"27"}],"author":[{"last_name":"Grawinkel","first_name":"Matthias","full_name":"Grawinkel, Matthias"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"last_name":"Best","first_name":"Georg","full_name":"Best, Georg"},{"full_name":"Popov, Ivan","first_name":"Ivan","last_name":"Popov"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publisher":"IEEE","date_created":"2018-03-29T14:44:24Z","status":"public"},{"author":[{"first_name":"Martin","full_name":"Wistuba, Martin","last_name":"Wistuba"},{"first_name":"Lars","full_name":"Schaefers, Lars","last_name":"Schaefers"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE","department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Conf. on Computational Intelligence and Games (CIG)","status":"public","date_created":"2018-03-29T14:59:35Z","title":"Comparison of Bayesian Move Prediction Systems for Computer Go","user_id":"24135","citation":{"ieee":"M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99.","short":"M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.","bibtex":"@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }","mla":"Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.","apa":"Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143","ama":"Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143","chicago":"Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143."},"year":"2012","type":"conference","page":"91-99","date_updated":"2022-01-06T06:54:42Z","_id":"2103","doi":"10.1109/CIG.2012.6374143"},{"user_id":"24135","title":"Generic User Management for Science Gateways via Virtual Organizations","date_created":"2018-03-29T15:00:48Z","status":"public","publication":"Proc. EGI Technical Forum","department":[{"_id":"27"}],"author":[{"first_name":"Tobias","full_name":"Schlemmer, Tobias","last_name":"Schlemmer"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"first_name":"Sandra","full_name":"Gesing, Sandra","last_name":"Gesing"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph","last_name":"Müller-Pfefferkorn"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"}],"date_updated":"2022-01-06T06:54:42Z","_id":"2104","citation":{"apa":"Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn, R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways via Virtual Organizations. In Proc. EGI Technical Forum.","ama":"Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.","chicago":"Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer, Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum, 2012.","mla":"Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via Virtual Organizations.” Proc. EGI Technical Forum, 2012.","bibtex":"@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012, title={Generic User Management for Science Gateways via Virtual Organizations}, booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke, Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn, Ralph and Kohlbacher, Oliver}, year={2012} }","short":"T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.","ieee":"T. Schlemmer et al., “Generic User Management for Science Gateways via Virtual Organizations,” in Proc. EGI Technical Forum, 2012."},"type":"conference","year":"2012"},{"department":[{"_id":"27"}],"publication":"Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)","publisher":"IEEE","author":[{"full_name":"Congiu, Giuseppe","first_name":"Giuseppe","last_name":"Congiu"},{"last_name":"Grawinkel","full_name":"Grawinkel, Matthias","first_name":"Matthias"},{"first_name":"Sai","full_name":"Narasimhamurthy, Sai","last_name":"Narasimhamurthy"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"date_created":"2018-03-29T15:02:15Z","status":"public","title":"One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services","user_id":"24135","page":"16-24","type":"conference","year":"2012","citation":{"ieee":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,” in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 2012, pp. 16–24.","short":"G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24.","bibtex":"@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services}, DOI={10.1109/ClusterW.2012.16}, booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }","mla":"Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24, doi:10.1109/ClusterW.2012.16.","chicago":"Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.","apa":"Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012). One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16","ama":"Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS). IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16"},"date_updated":"2022-01-06T06:54:42Z","_id":"2105","doi":"10.1109/ClusterW.2012.16"},{"_id":"2107","date_updated":"2022-01-06T06:54:44Z","type":"conference","year":"2012","citation":{"short":"R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.","ieee":"R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012.","ama":"Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.","apa":"Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit.","chicago":"Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012.","bibtex":"@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }","mla":"Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012."},"title":"A Data Driven Science Gateway for Computational Workflows","user_id":"24135","author":[{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Blunk","first_name":"Dirk","full_name":"Blunk, Dirk"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Gesing","full_name":"Gesing, Sandra","first_name":"Sandra"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"first_name":"Martin","full_name":"Kruse, Martin","last_name":"Kruse"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"full_name":"Schuller, Bernd","first_name":"Bernd","last_name":"Schuller"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"},{"last_name":"Zink","full_name":"Zink, Andreas","first_name":"Andreas"}],"department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. UNICORE Summit","status":"public","date_created":"2018-03-29T15:06:46Z"},{"date_updated":"2022-01-06T06:53:22Z","_id":"1789","doi":"10.1109/MSST.2012.6232380","page":"1-12","type":"conference","citation":{"chicago":"Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380.","ama":"Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380","apa":"Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380","mla":"Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12, doi:10.1109/MSST.2012.6232380.","bibtex":"@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha}, year={2012}, pages={1–12} }","short":"J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.","ieee":"J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2012, pp. 1–12."},"year":"2012","title":"Design of an exact data deduplication cluster","user_id":"24135","publication":"Proc. Symp. on Mass Storage Systems and Technologies (MSST)","department":[{"_id":"27"}],"author":[{"last_name":"Kaiser","full_name":"Kaiser, Jürgen","first_name":"Jürgen"},{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"first_name":"Sascha","full_name":"Effert, Sascha","last_name":"Effert"}],"publisher":"IEEE","date_created":"2018-03-26T15:12:01Z","status":"public"},{"date_created":"2018-04-03T09:01:19Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. EGI Community Forum","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"first_name":"Sonja","full_name":"Herres-Pawlis, Sonja","last_name":"Herres-Pawlis"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"last_name":"Kacsuk","full_name":"Kacsuk, Peter","first_name":"Peter"},{"first_name":"Oliver","full_name":"Kohlbacher, Oliver","last_name":"Kohlbacher"},{"last_name":"Kozlovszky","full_name":"Kozlovszky, Miklos","first_name":"Miklos"},{"full_name":"Krüger, Jens","first_name":"Jens","last_name":"Krüger"},{"last_name":"Müller-Pfefferkorn","full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph"},{"last_name":"Schäfer","full_name":"Schäfer, Patrick","first_name":"Patrick"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"}],"title":"The MoSGrid Community From National to International Scale","user_id":"24135","citation":{"short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012.","ieee":"S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012.","chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community From National to International Scale.” In Proc. EGI Community Forum, 2012.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From National to International Scale. In: Proc. EGI Community Forum. ; 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International Scale. In Proc. EGI Community Forum.","mla":"Gesing, Sandra, et al. “The MoSGrid Community From National to International Scale.” Proc. EGI Community Forum, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={The MoSGrid Community From National to International Scale}, booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }"},"year":"2012","type":"conference","_id":"2171","date_updated":"2022-01-06T06:55:11Z"},{"user_id":"24135","title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","date_created":"2018-04-03T09:15:35Z","status":"public","volume":"PoS(EGICF12-EMITC2)050","publication":"Proceedings of Science","department":[{"_id":"27"}],"author":[{"first_name":"Sandra","full_name":"Gesing, Sandra","last_name":"Gesing"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"last_name":"Grunzke","full_name":"Grunzke, Richard","first_name":"Richard"},{"full_name":"Kacsuk, Peter","first_name":"Peter","last_name":"Kacsuk"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Kozlovszky","full_name":"Kozlovszky, Miklos","first_name":"Miklos"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph","last_name":"Müller-Pfefferkorn"},{"full_name":"Schäfer, Patrick","first_name":"Patrick","last_name":"Schäfer"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"}],"_id":"2178","date_updated":"2022-01-06T06:55:13Z","type":"conference","citation":{"chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050).","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.","ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050."},"year":"2012"},{"year":"2012","type":"conference","citation":{"mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196."},"page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"publisher":"IEEE","author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"}],"quality_controlled":"1","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"file_date_updated":"2019-02-13T09:04:46Z","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"access_level":"closed","date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","success":1,"relation":"main_file","date_updated":"2019-02-13T09:04:46Z","content_type":"application/pdf","creator":"fossie","file_id":"7638","file_size":2148787}],"has_accepted_license":"1","status":"public","date_created":"2018-03-29T15:04:25Z","abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"ddc":["000"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:13Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"date_updated":"2023-09-26T13:42:26Z","doi":"10.1109/ReConFig.2012.6416745","language":[{"iso":"eng"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"615","type":"conference","year":"2012","citation":{"chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745."},"page":"1-8","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"user_id":"15278","ddc":["040"],"file":[{"content_type":"application/pdf","date_updated":"2018-03-15T06:48:32Z","relation":"main_file","success":1,"file_size":730144,"creator":"florida","file_id":"1246","access_level":"closed","file_name":"615-ReConFig12_01.pdf","date_created":"2018-03-15T06:48:32Z"}],"author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Hangmann","first_name":"Hendrik","full_name":"Hangmann, Hendrik"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z"},{"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","language":[{"iso":"eng"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"_id":"591","page":"1-8","type":"conference","citation":{"ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773"},"year":"2012","ddc":["040"],"user_id":"15278","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"date_created":"2017-10-17T12:42:47Z","has_accepted_license":"1","status":"public","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"}],"publisher":"IEEE","quality_controlled":"1","file":[{"access_level":"closed","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","date_created":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","date_updated":"2018-03-15T08:33:18Z","content_type":"application/pdf","creator":"florida","file_id":"1257","file_size":371235}]},{"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:50Z","quality_controlled":"1","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"file_date_updated":"2018-03-15T08:14:17Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file":[{"access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_created":"2018-03-15T08:14:17Z","relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z","creator":"florida","file_id":"1249","file_size":146789}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method.","lang":"eng"}],"type":"conference","citation":{"mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9."},"year":"2012","page":"8-9","_id":"609","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","grant_number":"257906","_id":"31"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z"},{"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"doi":"10.1109/HPCSim.2012.6266973","date_updated":"2023-09-26T13:42:54Z","language":[{"iso":"eng"}],"user_id":"15278","ddc":["040"],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:42Z","file":[{"file_name":"567-ba-ca-12a.pdf","date_created":"2018-03-15T10:20:24Z","access_level":"closed","file_size":288508,"creator":"florida","file_id":"1275","date_updated":"2018-03-15T10:20:24Z","content_type":"application/pdf","relation":"main_file","success":1}],"author":[{"full_name":"Barrio, Pablo","first_name":"Pablo","last_name":"Barrio"},{"first_name":"Carlos","full_name":"Carreras, Carlos","last_name":"Carreras"},{"full_name":"Sierra, Roberto","first_name":"Roberto","last_name":"Sierra"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","publisher":"IEEE","file_date_updated":"2018-03-15T10:20:24Z","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","_id":"567","citation":{"short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }"},"type":"conference","year":"2012","page":"559-565"},{"page":"559-562","type":"conference","year":"2012","citation":{"mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562."},"_id":"612","publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","author":[{"first_name":"Christoph","full_name":"Rüthing, Christoph","last_name":"Rüthing"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"publisher":"IEEE","quality_controlled":"1","file":[{"date_created":"2018-03-15T06:49:03Z","file_name":"612-ruething_fpl12.pdf","access_level":"closed","file_size":202923,"creator":"florida","file_id":"1247","content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z","success":1,"relation":"main_file"}],"date_created":"2017-10-17T12:42:51Z","has_accepted_license":"1","status":"public","abstract":[{"text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA.","lang":"eng"}],"ddc":["040"],"user_id":"15278","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012."},"year":"2012","date_updated":"2023-09-26T13:40:17Z","_id":"2180","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["funding-enhance"],"publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"quality_controlled":"1","date_created":"2018-04-03T09:18:33Z","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"status":"public","user_id":"15278","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux"},{"abstract":[{"text":"Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.","lang":"eng"}],"user_id":"15274","title":"Rule Based Mapping of Virtual Machines in Clouds","author":[{"full_name":"Kleineweber, Christoph","first_name":"Christoph","last_name":"Kleineweber"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"publication":"Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-29T11:21:05Z","publication_status":"published","_id":"1968","date_updated":"2022-01-06T06:54:10Z","doi":"10.1109/PDP.2011.69","language":[{"iso":"eng"}],"year":"2011","citation":{"chicago":"Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69.","ama":"Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69","apa":"Kleineweber, C., Keller, A., Niehörster, O., & Brinkmann, A. (2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69","mla":"Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011, doi:10.1109/PDP.2011.69.","bibtex":"@inproceedings{Kleineweber_Keller_Niehörster_Brinkmann_2011, title={Rule Based Mapping of Virtual Machines in Clouds}, DOI={10.1109/PDP.2011.69}, booktitle={Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)}, author={Kleineweber, Christoph and Keller, Axel and Niehörster, Oliver and Brinkmann, André}, year={2011} }","short":"C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011.","ieee":"C. Kleineweber, A. Keller, O. Niehörster, and A. Brinkmann, “Rule Based Mapping of Virtual Machines in Clouds,” in Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011."},"type":"conference"},{"publication_status":"published","status":"public","date_created":"2018-03-29T11:23:22Z","author":[{"last_name":"Niehörster","first_name":"Oliver","full_name":"Niehörster, Oliver"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publication":"Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","department":[{"_id":"27"}],"title":"An Energy-Aware SaaS Stack","user_id":"15274","abstract":[{"lang":"eng","text":"We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds."}],"type":"conference","citation":{"short":"O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","ieee":"O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","chicago":"Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011. https://doi.org/10.1109/MASCOTS.2011.52.","ama":"Niehörster O, Keller A, Brinkmann A. An Energy-Aware SaaS Stack. In: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). ; 2011. doi:10.1109/MASCOTS.2011.52","apa":"Niehörster, O., Keller, A., & Brinkmann, A. (2011). An Energy-Aware SaaS Stack. In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). https://doi.org/10.1109/MASCOTS.2011.52","mla":"Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.","bibtex":"@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster, Oliver and Keller, Axel and Brinkmann, André}, year={2011} }"},"year":"2011","language":[{"iso":"eng"}],"doi":"10.1109/MASCOTS.2011.52","_id":"1972","date_updated":"2022-01-06T06:54:10Z"},{"publisher":"IEEE Computer Society","author":[{"first_name":"Alberto","full_name":"Miranda, Alberto","last_name":"Miranda"},{"last_name":"Effert","first_name":"Sascha","full_name":"Effert, Sascha"},{"last_name":"Kang","first_name":"Yangwook","full_name":"Kang, Yangwook"},{"full_name":"Miller, Ethan","first_name":"Ethan","last_name":"Miller"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Cortes","first_name":"Toni","full_name":"Cortes, Toni"}],"publication":"Proc. Int. Conf. on High Performance Computing (HIPC)","department":[{"_id":"27"}],"status":"public","date_created":"2018-04-03T14:30:39Z","place":"Washington, DC","title":"Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems","user_id":"24135","year":"2011","citation":{"short":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, Washington, DC, 2011, pp. 1–10.","ieee":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, and T. Cortes, “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems,” in Proc. Int. Conf. on High Performance Computing (HIPC), 2011, pp. 1–10.","ama":"Miranda A, Effert S, Kang Y, Miller E, Brinkmann A, Cortes T. Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In: Proc. Int. Conf. on High Performance Computing (HIPC). Washington, DC: IEEE Computer Society; 2011:1-10. doi:10.1109/HiPC.2011.6152745","apa":"Miranda, A., Effert, S., Kang, Y., Miller, E., Brinkmann, A., & Cortes, T. (2011). Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In Proc. Int. Conf. on High Performance Computing (HIPC) (pp. 1–10). Washington, DC: IEEE Computer Society. https://doi.org/10.1109/HiPC.2011.6152745","chicago":"Miranda, Alberto, Sascha Effert, Yangwook Kang, Ethan Miller, André Brinkmann, and Toni Cortes. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” In Proc. Int. Conf. on High Performance Computing (HIPC), 1–10. Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745.","mla":"Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745.","bibtex":"@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }"},"type":"conference","page":"1-10","_id":"2188","date_updated":"2022-01-06T06:55:18Z","doi":"10.1109/HiPC.2011.6152745"},{"year":"2011","citation":{"ieee":"M. Grawinkel, M. Pargmann, H. Dömer, and A. Brinkmann, “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2011, pp. 380–387.","short":"M. Grawinkel, M. Pargmann, H. Dömer, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–387.","bibtex":"@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }","mla":"Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77.","chicago":"Grawinkel, Matthias, Markus Pargmann, Hubert Dömer, and André Brinkmann. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 380–87. IEEE, 2011. https://doi.org/10.1109/ICPADS.2011.77.","apa":"Grawinkel, M., Pargmann, M., Dömer, H., & Brinkmann, A. (2011). Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 380–387). IEEE. https://doi.org/10.1109/ICPADS.2011.77","ama":"Grawinkel M, Pargmann M, Dömer H, Brinkmann A. Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77"},"type":"conference","page":"380-387","date_updated":"2022-01-06T06:55:18Z","_id":"2189","doi":"10.1109/ICPADS.2011.77","author":[{"last_name":"Grawinkel","full_name":"Grawinkel, Matthias","first_name":"Matthias"},{"first_name":"Markus","full_name":"Pargmann, Markus","last_name":"Pargmann"},{"last_name":"Dömer","full_name":"Dömer, Hubert","first_name":"Hubert"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publisher":"IEEE","department":[{"_id":"27"}],"publication":"Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)","status":"public","date_created":"2018-04-03T14:32:23Z","title":"Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System","user_id":"24135"},{"place":"Washington DC, USA","user_id":"24135","title":"Autonomic Resource Management Handling Delayed Configuration Effects","publisher":"IEEE Computer Society","author":[{"full_name":"Niehörster, Oliver","first_name":"Oliver","last_name":"Niehörster"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"publication":"Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)","department":[{"_id":"27"}],"status":"public","date_created":"2018-04-03T14:33:50Z","_id":"2190","date_updated":"2022-01-06T06:55:19Z","doi":"10.1109/CloudCom.2011.28","citation":{"apa":"Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) (pp. 138–145). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/CloudCom.2011.28","ama":"Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145. doi:10.1109/CloudCom.2011.28","chicago":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.","bibtex":"@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }","mla":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.","short":"O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA, 2011, pp. 138–145.","ieee":"O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed Configuration Effects,” in Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 2011, pp. 138–145."},"year":"2011","type":"conference","page":"138-145"},{"_id":"2191","date_updated":"2022-01-06T06:55:19Z","citation":{"short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011.","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.","apa":"Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }"},"year":"2011","type":"conference","user_id":"24135","title":"Estimation and Partitioning for CPU-Accelerator Architectures","date_created":"2018-04-03T14:34:57Z","status":"public","publication":"Intel European Research and Innovation Conference","keyword":["funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"last_name":"Kauschke","full_name":"Kauschke, Michael","first_name":"Michael"}]},{"page":"297-306","type":"conference","citation":{"mla":"Grawinkel, Matthias, et al. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306, doi:10.1109/mascots.2011.13.","bibtex":"@inproceedings{Grawinkel_Schäfer_Brinkmann_Hagemeyer_Porrmann_2011, title={Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability}, DOI={10.1109/mascots.2011.13}, booktitle={Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, publisher={IEEE Computer Society}, author={Grawinkel, Matthias and Schäfer, Thorsten and Brinkmann, André and Hagemeyer, Jens and Porrmann, Mario}, year={2011}, pages={297–306} }","ama":"Grawinkel M, Schäfer T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society; 2011:297-306. doi:10.1109/mascots.2011.13","apa":"Grawinkel, M., Schäfer, T., Brinkmann, A., Hagemeyer, J., & Porrmann, M. (2011). Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) (pp. 297–306). IEEE Computer Society. https://doi.org/10.1109/mascots.2011.13","chicago":"Grawinkel, Matthias, Thorsten Schäfer, André Brinkmann, Jens Hagemeyer, and Mario Porrmann. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 297–306. IEEE Computer Society, 2011. https://doi.org/10.1109/mascots.2011.13.","ieee":"M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, and M. Porrmann, “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability,” in Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, pp. 297–306.","short":"M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, M. Porrmann, in: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306."},"year":"2011","_id":"2195","date_updated":"2022-01-06T06:55:21Z","doi":"10.1109/mascots.2011.13","department":[{"_id":"27"}],"publication":"Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)","author":[{"last_name":"Grawinkel","full_name":"Grawinkel, Matthias","first_name":"Matthias"},{"last_name":"Schäfer","first_name":"Thorsten","full_name":"Schäfer, Thorsten"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Hagemeyer","full_name":"Hagemeyer, Jens","first_name":"Jens"},{"last_name":"Porrmann","first_name":"Mario","full_name":"Porrmann, Mario"}],"publisher":"IEEE Computer Society","date_created":"2018-04-03T15:01:31Z","status":"public","user_id":"24135","title":"Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability"},{"citation":{"ieee":"A. Brinkmann, Y. Gao, M. Korzeniowski, and D. Meister, “Request Load Balancing for Highly Skewed Traffic in P2P Networks,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2011, pp. 53–62.","short":"A. Brinkmann, Y. Gao, M. Korzeniowski, D. Meister, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62.","bibtex":"@inproceedings{Brinkmann_Gao_Korzeniowski_Meister_2011, title={Request Load Balancing for Highly Skewed Traffic in P2P Networks}, DOI={10.1109/NAS.2011.25}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE}, author={Brinkmann, André and Gao, Yan and Korzeniowski, Miroslaw and Meister, Dirk}, year={2011}, pages={53–62} }","mla":"Brinkmann, André, et al. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62, doi:10.1109/NAS.2011.25.","chicago":"Brinkmann, André, Yan Gao, Miroslaw Korzeniowski, and Dirk Meister. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 53–62. IEEE, 2011. https://doi.org/10.1109/NAS.2011.25.","ama":"Brinkmann A, Gao Y, Korzeniowski M, Meister D. Request Load Balancing for Highly Skewed Traffic in P2P Networks. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). IEEE; 2011:53-62. doi:10.1109/NAS.2011.25","apa":"Brinkmann, A., Gao, Y., Korzeniowski, M., & Meister, D. (2011). Request Load Balancing for Highly Skewed Traffic in P2P Networks. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 53–62). IEEE. https://doi.org/10.1109/NAS.2011.25"},"type":"conference","year":"2011","page":"53-62","doi":"10.1109/NAS.2011.25","_id":"2196","date_updated":"2022-01-06T06:55:21Z","status":"public","date_created":"2018-04-03T15:03:17Z","publisher":"IEEE","author":[{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"last_name":"Gao","first_name":"Yan","full_name":"Gao, Yan"},{"first_name":"Miroslaw","full_name":"Korzeniowski, Miroslaw","last_name":"Korzeniowski"},{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"}],"publication":"Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)","department":[{"_id":"27"}],"user_id":"24135","title":"Request Load Balancing for Highly Skewed Traffic in P2P Networks"},{"date_updated":"2022-01-06T06:55:21Z","_id":"2197","year":"2011","type":"conference","citation":{"ieee":"S. Gesing et al., “Granular Security for a Science Gateway in Structural Bioinformatics,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2011.","short":"S. Gesing, R. Grunzke, Á. Balaskó, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Herres-Pawlis, P. Kacsuk, M. Kozlovszky, J. Krüger, L. Packschies, P. Schäfer, B. Schuller, J. Schuster, T. Steinke, A. Szikszay Fabri, M. Wewior, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011.","mla":"Gesing, Sandra, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011.","bibtex":"@inproceedings{Gesing_Grunzke_Balaskó_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Herres-Pawlis_Kacsuk_et al._2011, title={Granular Security for a Science Gateway in Structural Bioinformatics}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Grunzke, Richard and Balaskó, Ákos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Herres-Pawlis, Sonja and Kacsuk, Peter and et al.}, year={2011} }","ama":"Gesing S, Grunzke R, Balaskó Á, et al. Granular Security for a Science Gateway in Structural Bioinformatics. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2011.","apa":"Gesing, S., Grunzke, R., Balaskó, Á., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). Granular Security for a Science Gateway in Structural Bioinformatics. In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA.","chicago":"Gesing, Sandra, Richard Grunzke, Ákos Balaskó, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA, 2011."},"title":"Granular Security for a Science Gateway in Structural Bioinformatics","user_id":"24135","department":[{"_id":"27"}],"publication":"Proc. Int. Workshop on Scientific Gateways (IWSG)","publisher":"Consorzio COMETA","author":[{"last_name":"Gesing","first_name":"Sandra","full_name":"Gesing, Sandra"},{"full_name":"Grunzke, Richard","first_name":"Richard","last_name":"Grunzke"},{"full_name":"Balaskó, Ákos","first_name":"Ákos","last_name":"Balaskó"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"full_name":"Breuers, Sebastian","first_name":"Sebastian","last_name":"Breuers"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"},{"first_name":"Gregor","full_name":"Fels, Gregor","last_name":"Fels"},{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"full_name":"Kacsuk, Peter","first_name":"Peter","last_name":"Kacsuk"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"},{"full_name":"Krüger, Jens","first_name":"Jens","last_name":"Krüger"},{"last_name":"Packschies","first_name":"Lars","full_name":"Packschies, Lars"},{"first_name":"Patrick","full_name":"Schäfer, Patrick","last_name":"Schäfer"},{"last_name":"Schuller","full_name":"Schuller, Bernd","first_name":"Bernd"},{"last_name":"Schuster","full_name":"Schuster, Johannes","first_name":"Johannes"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"},{"first_name":"Anna","full_name":"Szikszay Fabri, Anna","last_name":"Szikszay Fabri"},{"full_name":"Wewior, Martin","first_name":"Martin","last_name":"Wewior"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"}],"date_created":"2018-04-03T15:04:04Z","status":"public"},{"page":"94-95","citation":{"apa":"Gesing, S., Kacsuk, P., Kozlovszky, M., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). A Science Gateway for Molecular Simulations. In Proc. EGI User Forum (pp. 94–95).","ama":"Gesing S, Kacsuk P, Kozlovszky M, et al. A Science Gateway for Molecular Simulations. In: Proc. EGI User Forum. ; 2011:94-95.","chicago":"Gesing, Sandra, Peter Kacsuk, Miklos Kozlovszky, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “A Science Gateway for Molecular Simulations.” In Proc. EGI User Forum, 94–95, 2011.","bibtex":"@inproceedings{Gesing_Kacsuk_Kozlovszky_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Grunzke_Herres-Pawlis_et al._2011, title={A Science Gateway for Molecular Simulations}, booktitle={Proc. EGI User Forum}, author={Gesing, Sandra and Kacsuk, Peter and Kozlovszky, Miklos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Grunzke, Richard and Herres-Pawlis, Sonja and et al.}, year={2011}, pages={94–95} }","mla":"Gesing, Sandra, et al. “A Science Gateway for Molecular Simulations.” Proc. EGI User Forum, 2011, pp. 94–95.","short":"S. Gesing, P. Kacsuk, M. Kozlovszky, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, R. Grunzke, S. Herres-Pawlis, J. Krüger, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, A. Szikszay Fabri, K.-D. Warzecha, M. Wewior, O. Kohlbacher, in: Proc. EGI User Forum, 2011, pp. 94–95.","ieee":"S. Gesing et al., “A Science Gateway for Molecular Simulations,” in Proc. EGI User Forum, 2011, pp. 94–95."},"year":"2011","type":"conference","date_updated":"2022-01-06T06:55:22Z","_id":"2199","department":[{"_id":"27"}],"publication":"Proc. EGI User Forum","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"last_name":"Kacsuk","full_name":"Kacsuk, Peter","first_name":"Peter"},{"full_name":"Kozlovszky, Miklos","first_name":"Miklos","last_name":"Kozlovszky"},{"last_name":"Birkenheuer","full_name":"Birkenheuer, Georg","first_name":"Georg"},{"last_name":"Blunk","full_name":"Blunk, Dirk","first_name":"Dirk"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"full_name":"Fels, Gregor","first_name":"Gregor","last_name":"Fels"},{"last_name":"Grunzke","full_name":"Grunzke, Richard","first_name":"Richard"},{"full_name":"Herres-Pawlis, Sonja","first_name":"Sonja","last_name":"Herres-Pawlis"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"full_name":"Packschies, Lars","first_name":"Lars","last_name":"Packschies"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"last_name":"Schäfer","first_name":"Patrick","full_name":"Schäfer, Patrick"},{"last_name":"Steinke","first_name":"Thomas","full_name":"Steinke, Thomas"},{"last_name":"Szikszay Fabri","full_name":"Szikszay Fabri, Anna","first_name":"Anna"},{"full_name":"Warzecha, Klaus-Dieter","first_name":"Klaus-Dieter","last_name":"Warzecha"},{"last_name":"Wewior","first_name":"Martin","full_name":"Wewior, Martin"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"}],"date_created":"2018-04-03T15:07:11Z","status":"public","title":"A Science Gateway for Molecular Simulations","user_id":"24135"},{"title":"Autonomic Resource Management with Support Vector Machines","user_id":"24135","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-0-7695-4572-1"]},"date_created":"2018-04-03T15:13:42Z","status":"public","department":[{"_id":"27"}],"publication":"Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)","publisher":"IEEE Computer Society","author":[{"last_name":"Niehörster","full_name":"Niehörster, Oliver","first_name":"Oliver"},{"first_name":"Jens","full_name":"Simon, Jens","last_name":"Simon","id":"15273"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Krieger","first_name":"Alexaner","full_name":"Krieger, Alexaner"}],"doi":"10.1109/Grid.2011.28","_id":"2203","date_updated":"2022-01-06T06:55:23Z","page":"157-164","citation":{"short":"O. Niehörster, J. Simon, A. Brinkmann, A. Krieger, in: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, Washington, DC, USA, 2011, pp. 157–164.","ieee":"O. Niehörster, J. Simon, A. Brinkmann, and A. Krieger, “Autonomic Resource Management with Support Vector Machines,” in Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 2011, pp. 157–164.","ama":"Niehörster O, Simon J, Brinkmann A, Krieger A. Autonomic Resource Management with Support Vector Machines. In: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID). Washington, DC, USA: IEEE Computer Society; 2011:157-164. doi:10.1109/Grid.2011.28","apa":"Niehörster, O., Simon, J., Brinkmann, A., & Krieger, A. (2011). Autonomic Resource Management with Support Vector Machines. In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) (pp. 157–164). Washington, DC, USA: IEEE Computer Society. https://doi.org/10.1109/Grid.2011.28","chicago":"Niehörster, Oliver, Jens Simon, André Brinkmann, and Alexaner Krieger. “Autonomic Resource Management with Support Vector Machines.” In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 157–64. Washington, DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/Grid.2011.28.","mla":"Niehörster, Oliver, et al. “Autonomic Resource Management with Support Vector Machines.” Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, 2011, pp. 157–64, doi:10.1109/Grid.2011.28.","bibtex":"@inproceedings{Niehörster_Simon_Brinkmann_Krieger_2011, place={Washington, DC, USA}, title={Autonomic Resource Management with Support Vector Machines}, DOI={10.1109/Grid.2011.28}, booktitle={Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Krieger, Alexaner}, year={2011}, pages={157–164} }"},"year":"2011","type":"conference"},{"type":"conference","citation":{"ieee":"T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in Proc. European Conf. on Parallel Processing (Euro-Par), 2011, vol. 6853.","short":"T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.","mla":"Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36.","bibtex":"@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={10.1007/978-3-642-23397-5_36}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }","chicago":"Graf, Tobias, Ulf Lorenz, Marco Platzner, and Lars Schaefers. “Parallel Monte-Carlo Tree Search for HPC Systems.” In Proc. European Conf. on Parallel Processing (Euro-Par), Vol. 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2011. https://doi.org/10.1007/978-3-642-23397-5_36.","apa":"Graf, T., Lorenz, U., Platzner, M., & Schaefers, L. (2011). Parallel Monte-Carlo Tree Search for HPC Systems. In Proc. European Conf. on Parallel Processing (Euro-Par) (Vol. 6853). Berlin / Heidelberg: Springer. https://doi.org/10.1007/978-3-642-23397-5_36","ama":"Graf T, Lorenz U, Platzner M, Schaefers L. Parallel Monte-Carlo Tree Search for HPC Systems. In: Proc. European Conf. on Parallel Processing (Euro-Par). Vol 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2011. doi:10.1007/978-3-642-23397-5_36"},"year":"2011","series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/978-3-642-23397-5_36","intvolume":" 6853","_id":"2204","date_updated":"2022-01-06T06:55:23Z","volume":6853,"status":"public","date_created":"2018-04-03T15:14:56Z","author":[{"last_name":"Graf","first_name":"Tobias","full_name":"Graf, Tobias"},{"first_name":"Ulf","full_name":"Lorenz, Ulf","last_name":"Lorenz"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"},{"last_name":"Schaefers","full_name":"Schaefers, Lars","first_name":"Lars"}],"publisher":"Springer","publication":"Proc. European Conf. on Parallel Processing (Euro-Par)","department":[{"_id":"27"},{"_id":"78"}],"title":"Parallel Monte-Carlo Tree Search for HPC Systems","user_id":"24135","place":"Berlin / Heidelberg"},{"volume":829,"status":"public","date_created":"2018-04-04T09:34:24Z","author":[{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"last_name":"Breuers","first_name":"Sebastian","full_name":"Breuers, Sebastian"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"full_name":"Fels, Gregor","first_name":"Gregor","last_name":"Fels"},{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"last_name":"Grunzke","full_name":"Grunzke, Richard","first_name":"Richard"},{"first_name":"Sonja","full_name":"Herres-Pawlis, Sonja","last_name":"Herres-Pawlis"},{"last_name":"Kohlbacher","full_name":"Kohlbacher, Oliver","first_name":"Oliver"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"full_name":"Lang, Ulrich","first_name":"Ulrich","last_name":"Lang"},{"first_name":"Lars","full_name":"Packschies, Lars","last_name":"Packschies"},{"full_name":"Müller-Pfefferkorn, Ralph","first_name":"Ralph","last_name":"Müller-Pfefferkorn"},{"full_name":"Schäfer, Patrick","first_name":"Patrick","last_name":"Schäfer"},{"last_name":"Schuster","first_name":"Johannes","full_name":"Schuster, Johannes"},{"last_name":"Steinke","full_name":"Steinke, Thomas","first_name":"Thomas"},{"first_name":"Klaus-Dieter","full_name":"Warzecha, Klaus-Dieter","last_name":"Warzecha"},{"first_name":"Martin","full_name":"Wewior, Martin","last_name":"Wewior"}],"department":[{"_id":"27"}],"publication":"Proc. of Grid Workflow Workshop (GWW)","title":"MoSGrid: Progress of Workflow driven Chemical Simulations","user_id":"24135","citation":{"ieee":"G. Birkenheuer et al., “MoSGrid: Progress of Workflow driven Chemical Simulations,” in Proc. of Grid Workflow Workshop (GWW), 2011, vol. 829.","short":"G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Gesing, R. Grunzke, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, U. Lang, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, J. Schuster, T. Steinke, K.-D. Warzecha, M. Wewior, in: Proc. of Grid Workflow Workshop (GWW), 2011.","bibtex":"@inproceedings{Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Gesing_Grunzke_Herres-Pawlis_Kohlbacher_Krüger_et al._2011, series={CEUR Workshop Proceedings}, title={MoSGrid: Progress of Workflow driven Chemical Simulations}, volume={829}, booktitle={Proc. of Grid Workflow Workshop (GWW)}, author={Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Gesing, Sandra and Grunzke, Richard and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and et al.}, year={2011}, collection={CEUR Workshop Proceedings} }","mla":"Birkenheuer, Georg, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” Proc. of Grid Workflow Workshop (GWW), vol. 829, 2011.","chicago":"Birkenheuer, Georg, Dirk Blunk, Sebastian Breuers, André Brinkmann, Gregor Fels, Sandra Gesing, Richard Grunzke, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” In Proc. of Grid Workflow Workshop (GWW), Vol. 829. CEUR Workshop Proceedings, 2011.","ama":"Birkenheuer G, Blunk D, Breuers S, et al. MoSGrid: Progress of Workflow driven Chemical Simulations. In: Proc. of Grid Workflow Workshop (GWW). Vol 829. CEUR Workshop Proceedings. ; 2011.","apa":"Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Fels, G., Gesing, S., … Wewior, M. (2011). MoSGrid: Progress of Workflow driven Chemical Simulations. In Proc. of Grid Workflow Workshop (GWW) (Vol. 829)."},"type":"conference","year":"2011","series_title":"CEUR Workshop Proceedings","date_updated":"2022-01-06T06:55:23Z","_id":"2205","intvolume":" 829"},{"doi":"10.1109/SAAHPC.2011.12","date_updated":"2023-09-26T13:44:11Z","_id":"2194","year":"2011","type":"conference","citation":{"bibtex":"@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }","mla":"Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.","apa":"Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12","ama":"Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12","chicago":"Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.","ieee":"B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.","short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63."},"page":"60-63","language":[{"iso":"eng"}],"title":"Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend","user_id":"15278","status":"public","date_created":"2018-04-03T14:55:57Z","project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"}],"publication":"Symp. on Application Accelerators in High Performance Computing (SAAHPC)","keyword":["tet_topic_hpc"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}]}]