TY - GEN AB - This preprint makes the claim of having computed the $9^{th}$ Dedekind Number. This was done by building an efficient FPGA Accelerator for the core operation of the process, and parallelizing it on the Noctua 2 Supercluster at Paderborn University. The resulting value is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. AU - Van Hirtum, Lennart AU - De Causmaecker, Patrick AU - Goemaere, Jens AU - Kenter, Tobias AU - Riebler, Heinrich AU - Lass, Michael AU - Plessl, Christian ID - 43439 T2 - arXiv:2304.03039 TI - A computation of D(9) using FPGA Supercomputing ER - TY - CONF AB - The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be computed for every time step. In this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence relations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our best knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far. Our evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \times 10^9$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x. AU - Wu, Xin AU - Kenter, Tobias AU - Schade, Robert AU - Kühne, Thomas AU - Plessl, Christian ID - 43228 T2 - 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) TI - Computing and Compressing Electron Repulsion Integrals on FPGAs ER - TY - CONF AU - Prouveur, Charles AU - Haefele, Matthieu AU - Kenter, Tobias AU - Voss, Nils ID - 46189 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - FPGA Acceleration for HPC Supercapacitor Simulations ER - TY - GEN AB - Viscous hydrodynamics serves as a successful mesoscopic description of the Quark-Gluon Plasma produced in relativistic heavy-ion collisions. In order to investigate, how such an effective description emerges from the underlying microscopic dynamics we calculate the hydrodynamic and non-hydrodynamic modes of linear response in the sound channel from a first-principle calculation in kinetic theory. We do this with a new approach wherein we discretize the collision kernel to directly calculate eigenvalues and eigenmodes of the evolution operator. This allows us to study the Green's functions at any point in the complex frequency space. Our study focuses on scalar theory with quartic interaction and we find that the analytic structure of Green's functions in the complex plane is far more complicated than just poles or cuts which is a first step towards an equivalent study in QCD kinetic theory. AU - Ochsenfeld, Stephan AU - Schlichting, Sören ID - 50172 T2 - arXiv:2308.04491 TI - Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A Numerical Analysis in Scalar Field Theory ER - TY - GEN AB - Memory Gym presents a suite of 2D partially observable environments, namely Mortar Mayhem, Mystery Path, and Searing Spotlights, designed to benchmark memory capabilities in decision-making agents. These environments, originally with finite tasks, are expanded into innovative, endless formats, mirroring the escalating challenges of cumulative memory games such as ``I packed my bag''. This progression in task design shifts the focus from merely assessing sample efficiency to also probing the levels of memory effectiveness in dynamic, prolonged scenarios. To address the gap in available memory-based Deep Reinforcement Learning baselines, we introduce an implementation that integrates Transformer-XL (TrXL) with Proximal Policy Optimization. This approach utilizes TrXL as a form of episodic memory, employing a sliding window technique. Our comparative study between the Gated Recurrent Unit (GRU) and TrXL reveals varied performances across different settings. TrXL, on the finite environments, demonstrates superior sample efficiency in Mystery Path and outperforms in Mortar Mayhem. However, GRU is more efficient on Searing Spotlights. Most notably, in all endless tasks, GRU makes a remarkable resurgence, consistently outperforming TrXL by significant margins. Website and Source Code: https://github.com/MarcoMeter/endless-memory-gym/ AU - Pleines, Marco AU - Pallasch, Matthias AU - Zimmer, Frank AU - Preuss, Mike ID - 50221 T2 - arXiv:2309.17207 TI - Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of Agents ER - TY - CONF AU - Opdenhövel, Jan-Oliver AU - Plessl, Christian AU - Kenter, Tobias ID - 46190 T2 - Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation ER - TY - CONF AU - Faj, Jennifer AU - Kenter, Tobias AU - Faghih-Naini, Sara AU - Plessl, Christian AU - Aizinger, Vadym ID - 46188 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Kenter, Tobias AU - Jansson, Niclas AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 46193 T2 - International Conference on High Performance Computing in Asia-Pacific Region TI - A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges ER - TY - GEN AB - The Julia programming language has evolved into a modern alternative to fill existing gaps in scientific computing and data science applications. Julia leverages a unified and coordinated single-language and ecosystem paradigm and has a proven track record of achieving high performance without sacrificing user productivity. These aspects make Julia a viable alternative to high-performance computing's (HPC's) existing and increasingly costly many-body workflow composition strategy in which traditional HPC languages (e.g., Fortran, C, C++) are used for simulations, and higher-level languages (e.g., Python, R, MATLAB) are used for data analysis and interactive computing. Julia's rapid growth in language capabilities, package ecosystem, and community make it a promising universal language for HPC. This paper presents the views of a multidisciplinary group of researchers from academia, government, and industry that advocate for an HPC software development paradigm that emphasizes developer productivity, workflow portability, and low barriers for entry. We believe that the Julia programming language, its ecosystem, and its community provide modern and powerful capabilities that enable this group's objectives. Crucially, we believe that Julia can provide a feasible and less costly approach to programming scientific applications and workflows that target HPC facilities. In this work, we examine the current practice and role of Julia as a common, end-to-end programming model to address major challenges in scientific reproducibility, data-driven AI/machine learning, co-design and workflows, scalability and performance portability in heterogeneous computing, network communication, data management, and community education. As a result, the diversification of current investments to fulfill the needs of the upcoming decade is crucial as more supercomputing centers prepare for the exascale era. AU - Churavy, Valentin AU - Godoy, William F AU - Bauer, Carsten AU - Ranocha, Hendrik AU - Schlottke-Lakemper, Michael AU - Räss, Ludovic AU - Blaschke, Johannes AU - Giordano, Mosè AU - Schnetter, Erik AU - Omlin, Samuel AU - Vetter, Jeffrey S AU - Edelman, Alan ID - 36879 TI - Bridging HPC Communities through the Julia Programming Language ER - TY - GEN AB - The CP2K program package, which can be considered as the swiss army knife of atomistic simulations, is presented with a special emphasis on ab-initio molecular dynamics using the second-generation Car-Parrinello method. After outlining current and near-term development efforts with regards to massively parallel low-scaling post-Hartree-Fock and eigenvalue solvers, novel approaches on how we plan to take full advantage of future low-precision hardware architectures are introduced. Our focus here is on combining our submatrix method with the approximate computing paradigm to address the immanent exascale era. AU - Kühne, Thomas AU - Plessl, Christian AU - Schade, Robert AU - Schütt, Ole ID - 32404 T2 - arXiv:2205.14741 TI - CP2K on the road to exascale ER - TY - GEN AB - We investigate the early time development of the anisotropic transverse flow and spatial eccentricities of a fireball with various particle-based transport approaches using a fixed initial condition. In numerical simulations ranging from the quasi-collisionless case to the hydrodynamic regime, we find that the onset of $v_n$ and of related measures of anisotropic flow can be described with a simple power-law ansatz, with an exponent that depends on the amount of rescatterings in the system. In the few-rescatterings regime we perform semi-analytical calculations, based on a systematic expansion in powers of time and the cross section, which can reproduce the numerical findings. AU - Borghini, Nicolas AU - Borrell, Marc AU - Roch, Hendrik ID - 32177 T2 - arXiv:2201.13294 TI - Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers ER - TY - GEN AB - We test the ability of the "escape mechanism" to create the anisotropic flow observed in high-energy nuclear collisions. We compare the flow harmonics $v_n$ in the few-rescatterings regime from two types of transport simulations, with $2\to 2$ and $2\to 0$ collision kernels respectively, and from analytical calculations neglecting the gain term of the Boltzmann equation. We find that the even flow harmonics are similar in the three approaches, while the odd harmonics differ significantly. AU - Bachmann, Benedikt AU - Borghini, Nicolas AU - Feld, Nina AU - Roch, Hendrik ID - 32178 T2 - arXiv:2203.13306 TI - Even anisotropic-flow harmonics are from Venus, odd ones are from Mars ER - TY - GEN AB - Electronic structure calculations have been instrumental in providing many important insights into a range of physical and chemical properties of various molecular and solid-state systems. Their importance to various fields, including materials science, chemical sciences, computational chemistry and device physics, is underscored by the large fraction of available public supercomputing resources devoted to these calculations. As we enter the exascale era, exciting new opportunities to increase simulation numbers, sizes, and accuracies present themselves. In order to realize these promises, the community of electronic structure software developers will however first have to tackle a number of challenges pertaining to the efficient use of new architectures that will rely heavily on massive parallelism and hardware accelerators. This roadmap provides a broad overview of the state-of-the-art in electronic structure calculations and of the various new directions being pursued by the community. It covers 14 electronic structure codes, presenting their current status, their development priorities over the next five years, and their plans towards tackling the challenges and leveraging the opportunities presented by the advent of exascale computing. AU - Gavini, Vikram AU - Baroni, Stefano AU - Blum, Volker AU - Bowler, David R. AU - Buccheri, Alexander AU - Chelikowsky, James R. AU - Das, Sambit AU - Dawson, William AU - Delugas, Pietro AU - Dogan, Mehmet AU - Draxl, Claudia AU - Galli, Giulia AU - Genovese, Luigi AU - Giannozzi, Paolo AU - Giantomassi, Matteo AU - Gonze, Xavier AU - Govoni, Marco AU - Gulans, Andris AU - Gygi, François AU - Herbert, John M. AU - Kokott, Sebastian AU - Kühne, Thomas AU - Liou, Kai-Hsin AU - Miyazaki, Tsuyoshi AU - Motamarri, Phani AU - Nakata, Ayako AU - Pask, John E. AU - Plessl, Christian AU - Ratcliff, Laura E. AU - Richard, Ryan M. AU - Rossi, Mariana AU - Schade, Robert AU - Scheffler, Matthias AU - Schütt, Ole AU - Suryanarayana, Phanish AU - Torrent, Marc AU - Truflandier, Lionel AU - Windus, Theresa L. AU - Xu, Qimen AU - Yu, Victor W. -Z. AU - Perez, Danny ID - 33493 T2 - arXiv:2209.12747 TI - Roadmap on Electronic Structure Codes in the Exascale Era ER - TY - GEN AB - Electronic structure calculations have been instrumental in providing many important insights into a range of physical and chemical properties of various molecular and solid-state systems. Their importance to various fields, including materials science, chemical sciences, computational chemistry and device physics, is underscored by the large fraction of available public supercomputing resources devoted to these calculations. As we enter the exascale era, exciting new opportunities to increase simulation numbers, sizes, and accuracies present themselves. In order to realize these promises, the community of electronic structure software developers will however first have to tackle a number of challenges pertaining to the efficient use of new architectures that will rely heavily on massive parallelism and hardware accelerators. This roadmap provides a broad overview of the state-of-the-art in electronic structure calculations and of the various new directions being pursued by the community. It covers 14 electronic structure codes, presenting their current status, their development priorities over the next five years, and their plans towards tackling the challenges and leveraging the opportunities presented by the advent of exascale computing. AU - Gavini, Vikram AU - Baroni, Stefano AU - Blum, Volker AU - Bowler, David R. AU - Buccheri, Alexander AU - Chelikowsky, James R. AU - Das, Sambit AU - Dawson, William AU - Delugas, Pietro AU - Dogan, Mehmet AU - Draxl, Claudia AU - Galli, Giulia AU - Genovese, Luigi AU - Giannozzi, Paolo AU - Giantomassi, Matteo AU - Gonze, Xavier AU - Govoni, Marco AU - Gulans, Andris AU - Gygi, François AU - Herbert, John M. AU - Kokott, Sebastian AU - Kühne, Thomas AU - Liou, Kai-Hsin AU - Miyazaki, Tsuyoshi AU - Motamarri, Phani AU - Nakata, Ayako AU - Pask, John E. AU - Plessl, Christian AU - Ratcliff, Laura E. AU - Richard, Ryan M. AU - Rossi, Mariana AU - Schade, Robert AU - Scheffler, Matthias AU - Schütt, Ole AU - Suryanarayana, Phanish AU - Torrent, Marc AU - Truflandier, Lionel AU - Windus, Theresa L. AU - Xu, Qimen AU - Yu, Victor W. -Z. AU - Perez, Danny ID - 46275 T2 - arXiv:2209.12747 TI - Roadmap on Electronic Structure Codes in the Exascale Era ER - TY - CONF AU - Kenter, Tobias AU - Shambhu, Adesh AU - Faghih-Naini, Sara AU - Aizinger, Vadym ID - 46194 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA ER - TY - CONF AU - Nickchen, Tobias AU - Heindorf, Stefan AU - Engels, Gregor ID - 20886 T2 - Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision TI - Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Jansson, Niclas AU - Kenter, Tobias AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 46195 T2 - 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) TI - High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Jansson, Niclas AU - Kenter, Tobias AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 29937 T2 - 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) TI - High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection ER - TY - GEN AB - Optical travelling wave antennas offer unique opportunities to control and selectively guide light into a specific direction which renders them as excellent candidates for optical communication and sensing. These applications require state of the art engineering to reach optimized functionalities such as high directivity and radiation efficiency, low side lobe level, broadband and tunable capabilities, and compact design. In this work we report on the numerical optimization of the directivity of optical travelling wave antennas made from low-loss dielectric materials using full-wave numerical simulations in conjunction with a particle swarm optimization algorithm. The antennas are composed of a reflector and a director deposited on a glass substrate and an emitter placed in the feed gap between them serves as an internal source of excitation. In particular, we analysed antennas with rectangular- and horn-shaped directors made of either Hafnium dioxide or Silicon. The optimized antennas produce highly directional emission due to the presence of two dominant guided TE modes in the director in addition to leaky modes. These guided modes dominate the far-field emission pattern and govern the direction of the main lobe emission which predominately originates from the end facet of the director. Our work also provides a comprehensive analysis of the modes, radiation patterns, parametric influences, and bandwidths of the antennas that highlights their robust nature. AU - Farheen, Henna AU - Leuteritz, Till AU - Linden, Stefan AU - Myroshnychenko, Viktor AU - Förstner, Jens ID - 32245 T2 - arXiv:2106.02468 TI - Optimization of optical waveguide antennas for directive emission of light ER - TY - GEN AB - The interaction between quantum light and matter is being intensively studied for systems that are enclosed in high-$Q$ cavities which strongly enhance the light-matter coupling. However, for many applications, cavities with lower $Q$-factors are preferred due to the increased spectral width of the cavity mode. Here, we investigate the interaction between quantum light and matter represented by a $\Lambda$-type three-level system in lossy cavities, assuming that cavity losses are the dominant loss mechanism. We demonstrate that cavity losses lead to non-trivial steady states of the electronic occupations that can be controlled by the loss rate and the initial statistics of the quantum fields. The mechanism of formation of such steady states can be understood on the basis of the equations of motion. Analytical expressions for steady states and their numerical simulations are presented and discussed. AU - Rose, H. AU - Tikhonova, O. V. AU - Meier, T. AU - Sharapova, P. ID - 32236 T2 - arXiv:2109.00842 TI - Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities ER - TY - GEN AB - We push the boundaries of electronic structure-based \textit{ab-initio} molecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise barely reachable with classical force-field methods or novel neural network and machine learning potentials. We achieve this breakthrough by combining innovations in linear-scaling AIMD, efficient and approximate sparse linear algebra, low and mixed-precision floating-point computation on GPUs, and a compensation scheme for the errors introduced by numerical approximations. The core of our work is the non-orthogonalized local submatrix method (NOLSM), which scales very favorably to massively parallel computing systems and translates large sparse matrix operations into highly parallel, dense matrix operations that are ideally suited to hardware accelerators. We demonstrate that the NOLSM method, which is at the center point of each AIMD step, is able to achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision corresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs. AU - Schade, Robert AU - Kenter, Tobias AU - Elgabarty, Hossam AU - Lass, Michael AU - Schütt, Ole AU - Lazzaro, Alfio AU - Pabst, Hans AU - Mohr, Stephan AU - Hutter, Jürg AU - Kühne, Thomas D. AU - Plessl, Christian ID - 32244 T2 - arXiv:2104.08245 TI - Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms ER - TY - CONF AU - Meyer, Marius ID - 27365 T2 - Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks ER - TY - CONF AB - Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on complex large-scale systems, so-called linear scaling methods instead of conventional cubic scaling methods are required. In this work, we take up the idea of the submatrix method and apply it to the DFT computations in the software package CP2K. For that purpose, we transform the underlying numeric operations on distributed, large, sparse matrices into computations on local, much smaller and nearly dense matrices. This allows us to exploit the full floating-point performance of modern CPUs and to make use of dedicated accelerator hardware, where performance has been limited by memory bandwidth before. We demonstrate both functionality and performance of our implementation and show how it can be accelerated with GPUs and FPGAs. AU - Lass, Michael AU - Schade, Robert AU - Kühne, Thomas AU - Plessl, Christian ID - 16898 T2 - Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC) TI - A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K ER - TY - CONF AB - FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. AU - Meyer, Marius AU - Kenter, Tobias AU - Plessl, Christian ID - 21632 KW - FPGA KW - OpenCL KW - High Level Synthesis KW - HPC benchmarking SN - 9781665415927 T2 - 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) TI - Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite ER - TY - GEN AB - We consider a resource-aware variant of the classical multi-armed bandit problem: In each round, the learner selects an arm and determines a resource limit. It then observes a corresponding (random) reward, provided the (random) amount of consumed resources remains below the limit. Otherwise, the observation is censored, i.e., no reward is obtained. For this problem setting, we introduce a measure of regret, which incorporates the actual amount of allocated resources of each learning round as well as the optimality of realizable rewards. Thus, to minimize regret, the learner needs to set a resource limit and choose an arm in such a way that the chance to realize a high reward within the predefined resource limit is high, while the resource limit itself should be kept as low as possible. We derive the theoretical lower bound on the cumulative regret and propose a learning algorithm having a regret upper bound that matches the lower bound. In a simulation study, we show that our learning algorithm outperforms straightforward extensions of standard multi-armed bandit algorithms. AU - Bengs, Viktor AU - Hüllermeier, Eyke ID - 32242 T2 - arXiv:2011.00813 TI - Multi-Armed Bandits with Censored Consumption of Resources ER - TY - CONF AB - Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS. AU - Gorlani, Paolo AU - Kenter, Tobias AU - Plessl, Christian ID - 15478 T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs ER - TY - CONF AB - This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation. AU - Keller, Axel ED - Klusáček, D. ED - Cirne, W. ED - Desai, N. ID - 22 KW - Scheduling Planning Mapping Workload management SN - 978-3-319-77398-8 T2 - Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) TI - A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems VL - 10773 ER - TY - CONF AB - We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures. We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution. AU - Lass, Michael AU - Mohr, Stephan AU - Wiebeler, Hendrik AU - Kühne, Thomas AU - Plessl, Christian ID - 1590 KW - approximate computing KW - linear algebra KW - matrix inversion KW - matrix p-th roots KW - numeric algorithm KW - parallel computing SN - 978-1-4503-5891-0/18/07 T2 - Proc. Platform for Advanced Scientific Computing (PASC) Conference TI - A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices ER - TY - CONF AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Kenter, Tobias AU - Plessl, Christian ID - 1204 KW - htrop SN - 9781450349826 T2 - Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) TI - Automated Code Acceleration Targeting Heterogeneous OpenCL Devices ER - TY - CONF AB - The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x. AU - Kenter, Tobias AU - Mahale, Gopinath AU - Alhaddad, Samer AU - Grynko, Yevgen AU - Schmitt, Christian AU - Afzal, Ayesha AU - Hannig, Frank AU - Förstner, Jens AU - Plessl, Christian ID - 1588 KW - tet_topic_hpc T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes ER - TY - CONF AB - Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures. AU - Kenter, Tobias AU - Förstner, Jens AU - Plessl, Christian ID - 1592 KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Flexible FPGA design for FDTD using OpenCL ER - TY - CONF AB - Version Control Systems (VCS) are a valuable tool for software development and document management. Both client/server and distributed (Peer-to-Peer) models exist, with the latter (e.g., Git and Mercurial) becoming increasingly popular. Their distributed nature introduces complications, especially concerning security: it is hard to control the dissemination of contents stored in distributed VCS as they rely on replication of complete repositories to any involved user. We overcome this issue by designing and implementing a concept for cryptography-enforced access control which is transparent to the user. Use of field-tested schemes (end-to-end encryption, digital signatures) allows for strong security, while adoption of convergent encryption and content-defined chunking retains storage efficiency. The concept is seamlessly integrated into Mercurial---respecting its distributed storage concept---to ensure practical usability and compatibility to existing deployments. AU - Lass, Michael AU - Leibenger, Dominik AU - Sorge, Christoph ID - 19 KW - access control KW - distributed version control systems KW - mercurial KW - peer-to-peer KW - convergent encryption KW - confidentiality KW - authenticity SN - 978-1-5090-2054-6 T2 - Proc. 41st Conference on Local Computer Networks (LCN) TI - Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian ID - 24 T2 - Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) TI - Microdisk Cavity FDTD Simulation on FPGA using OpenCL ER - TY - CONF AU - Dellnitz, Michael AU - Eckstein, Julian AU - Flaßkamp, Kathrin AU - Friedel, Patrick AU - Horenkamp, Christian AU - Köhler, Ulrich AU - Ober-Blöbaum, Sina AU - Peitz, Sebastian AU - Tiemeyer, Sebastian ID - 34 SN - 2212-0173 T2 - Progress in Industrial Mathematics at ECMI TI - Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control VL - 22 ER - TY - CONF AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Plessl, Christian ID - 171 T2 - Workshop on Reconfigurable Computing (WRC) TI - Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AU - Lass, Michael AU - Kühne, Thomas AU - Plessl, Christian ID - 25 T2 - Workshop on Approximate Computing (AC) TI - Using Approximate Computing in Scientific Codes ER - TY - CONF AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian AU - Trainiti, Ettore M. G. AU - Durelli, Gianluca C. AU - Bolchini, Cristiana ID - 31 T2 - Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) TI - Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems ER - TY - CONF AB - Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian AU - Trainiti, Ettore M. G. AU - Durelli, Gianluca C. AU - Del Sozzo, Emanuele AU - Santambrogio, Marco D. AU - Bolchini, Christina ID - 138 T2 - Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) TI - Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems ER - TY - CONF AB - This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. AU - Damschen, Marvin AU - Plessl, Christian ID - 303 T2 - Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) TI - Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores ER - TY - CONF AU - Schumacher, Jörn AU - T. Anderson, J. AU - Borga, A. AU - Boterenbrood, H. AU - Chen, H. AU - Chen, K. AU - Drake, G. AU - Francis, D. AU - Gorini, B. AU - Lanni, F. AU - Lehmann-Miotto, Giovanna AU - Levinson, L. AU - Narevicius, J. AU - Plessl, Christian AU - Roich, A. AU - Ryu, S. AU - P. Schreuder, F. AU - Vandelli, Wainer AU - Vermeulen, J. AU - Zhang, J. ID - 1773 T2 - Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) TI - Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm ER - TY - CONF AB - In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. AU - Damschen, Marvin AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 238 T2 - Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) TI - Transparent offloading of computational hotspots from binary code to Xeon Phi ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AB - In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment. AU - Steinle, Tobias AU - Vrabec, Jadran AU - Walther, Andrea ED - Bock, Hans Georg ED - Hoang, Xuan Phu ED - Rannacher, Rolf ED - Schlöder, Johannes P. ID - 1781 SN - 978-3-319-09063-4 T2 - Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) TI - Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres ER - TY - CONF AU - Graf, Tobias AU - Schaefers, Lars AU - Platzner, Marco ID - 1782 IS - 8427 T2 - Proc. Conf. on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go ER - TY - CONF AB - In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 388 T2 - Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC) TI - Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer VL - 8405 ER - TY - CONF AB - In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian AU - Sorge, Christoph ID - 377 KW - coldboot T2 - Proceedings of Field-Programmable Custom Computing Machines (FCCM) TI - Reconstructing AES Key Schedules from Decayed Memory with FPGAs ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Meister, Dirk AU - Nagel, Lars ID - 1788 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Distributing Storage in Cloud Environments ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André AU - Süß, Tim ID - 1793 T2 - Proc. USENIX Conference on File and Storage Technologies (FAST) TI - File Recipe Compression in Data Deduplication Systems ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Gottfried, Viktor AU - Brinkmann, André ID - 1784 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - MCD: Overcoming the Data Download Bottleneck in Data Centers ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Grunzke, Richard AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Kruse, Martin AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuller, Bernd AU - Steinke, Thomas AU - Zink, Andreas ID - 2107 T2 - Proc. UNICORE Summit TI - A Data Driven Science Gateway for Computational Workflows ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2178 T2 - Proceedings of Science TI - A Science Gateway Getting Ready for Serving the International Molecular Simulation Community VL - PoS(EGICF12-EMITC2)050 ER - TY - CONF AU - Meister, Dirk AU - Kaiser, Jürgen AU - Brinkmann, André AU - Kuhn, Michael AU - Kunkel, Julian AU - Cortes, Toni ID - 2099 T2 - Proc. Int. Conf. on Supercomputing (SC) TI - A Study on Data Deduplication in HPC Storage Systems ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Brinkmann, André AU - Effert, Sascha ID - 1789 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - Design of an exact data deduplication cluster ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Schlemmer, Tobias AU - Grunzke, Richard AU - Gesing, Sandra AU - Krüger, Jens AU - Birkenheuer, Georg AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2104 T2 - Proc. EGI Technical Forum TI - Generic User Management for Science Gateways via Virtual Organizations ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AU - Congiu, Giuseppe AU - Grawinkel, Matthias AU - Narasimhamurthy, Sai AU - Brinkmann, André ID - 2105 T2 - Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) TI - One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2171 T2 - Proc. EGI Community Forum TI - The MoSGrid Community From National to International Scale ER - TY - CONF AU - Grawinkel, Matthias AU - Süß, Tim AU - Best, Georg AU - Popov, Ivan AU - Brinkmann, André ID - 2101 T2 - Proc. Parallel Data Storage Workshop (PDSW) TI - Towards Dynamic Scripted pNFS Layouts ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AU - Gesing, Sandra AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Warzecha, Klaus-Dieter AU - Wewior, Martin AU - Kohlbacher, Oliver ID - 2199 T2 - Proc. EGI User Forum TI - A Science Gateway for Molecular Simulations ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André ID - 2190 T2 - Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) TI - Autonomic Resource Management Handling Delayed Configuration Effects ER - TY - CONF AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Krieger, Alexaner ID - 2203 SN - 978-0-7695-4572-1 T2 - Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) TI - Autonomic Resource Management with Support Vector Machines ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CONF AU - Grawinkel, Matthias AU - Schäfer, Thorsten AU - Brinkmann, André AU - Hagemeyer, Jens AU - Porrmann, Mario ID - 2195 T2 - Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability ER - TY - CONF AU - Gesing, Sandra AU - Grunzke, Richard AU - Balaskó, Ákos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Herres-Pawlis, Sonja AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Packschies, Lars AU - Schäfer, Patrick AU - Schuller, Bernd AU - Schuster, Johannes AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Wewior, Martin AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2197 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Granular Security for a Science Gateway in Structural Bioinformatics ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Grawinkel, Matthias AU - Pargmann, Markus AU - Dömer, Hubert AU - Brinkmann, André ID - 2189 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Gesing, Sandra AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Lang, Ulrich AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuster, Johannes AU - Steinke, Thomas AU - Warzecha, Klaus-Dieter AU - Wewior, Martin ID - 2205 T2 - Proc. of Grid Workflow Workshop (GWW) TI - MoSGrid: Progress of Workflow driven Chemical Simulations VL - 829 ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Miranda, Alberto AU - Effert, Sascha AU - Kang, Yangwook AU - Miller, Ethan AU - Brinkmann, André AU - Cortes, Toni ID - 2188 T2 - Proc. Int. Conf. on High Performance Computing (HIPC) TI - Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems ER - TY - CONF AU - Brinkmann, André AU - Gao, Yan AU - Korzeniowski, Miroslaw AU - Meister, Dirk ID - 2196 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Request Load Balancing for Highly Skewed Traffic in P2P Networks ER - TY - CONF AB - Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments. AU - Kleineweber, Christoph AU - Keller, Axel AU - Niehörster, Oliver AU - Brinkmann, André ID - 1968 T2 - Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) TI - Rule Based Mapping of Virtual Machines in Clouds ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2229 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Balls into Bins with Related Random Choices ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2232 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - Balls into Non-uniform Bins ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2230 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD) ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André AU - Fels, Gregor AU - Krüger, Jens AU - Simon, Jens ID - 2237 SN - 1552-5244 T2 - Proc. Int. Conf. on Cluster Computing (CLUSTER) TI - Enforcing SLAs in Scientific Clouds ER -