TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Gottfried, Viktor AU - Brinkmann, André ID - 1784 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - MCD: Overcoming the Data Download Bottleneck in Data Centers ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Meister, Dirk AU - Nagel, Lars ID - 1788 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Distributing Storage in Cloud Environments ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André AU - Süß, Tim ID - 1793 T2 - Proc. USENIX Conference on File and Storage Technologies (FAST) TI - File Recipe Compression in Data Deduplication Systems ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AU - Meister, Dirk AU - Kaiser, Jürgen AU - Brinkmann, André AU - Kuhn, Michael AU - Kunkel, Julian AU - Cortes, Toni ID - 2099 T2 - Proc. Int. Conf. on Supercomputing (SC) TI - A Study on Data Deduplication in HPC Storage Systems ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Grawinkel, Matthias AU - Süß, Tim AU - Best, Georg AU - Popov, Ivan AU - Brinkmann, André ID - 2101 T2 - Proc. Parallel Data Storage Workshop (PDSW) TI - Towards Dynamic Scripted pNFS Layouts ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - CONF AU - Schlemmer, Tobias AU - Grunzke, Richard AU - Gesing, Sandra AU - Krüger, Jens AU - Birkenheuer, Georg AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2104 T2 - Proc. EGI Technical Forum TI - Generic User Management for Science Gateways via Virtual Organizations ER - TY - CONF AU - Congiu, Giuseppe AU - Grawinkel, Matthias AU - Narasimhamurthy, Sai AU - Brinkmann, André ID - 2105 T2 - Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) TI - One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services ER - TY - CONF AU - Grunzke, Richard AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Kruse, Martin AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuller, Bernd AU - Steinke, Thomas AU - Zink, Andreas ID - 2107 T2 - Proc. UNICORE Summit TI - A Data Driven Science Gateway for Computational Workflows ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Brinkmann, André AU - Effert, Sascha ID - 1789 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - Design of an exact data deduplication cluster ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2171 T2 - Proc. EGI Community Forum TI - The MoSGrid Community From National to International Scale ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2178 T2 - Proceedings of Science TI - A Science Gateway Getting Ready for Serving the International Molecular Simulation Community VL - PoS(EGICF12-EMITC2)050 ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AB - Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments. AU - Kleineweber, Christoph AU - Keller, Axel AU - Niehörster, Oliver AU - Brinkmann, André ID - 1968 T2 - Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) TI - Rule Based Mapping of Virtual Machines in Clouds ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Miranda, Alberto AU - Effert, Sascha AU - Kang, Yangwook AU - Miller, Ethan AU - Brinkmann, André AU - Cortes, Toni ID - 2188 T2 - Proc. Int. Conf. on High Performance Computing (HIPC) TI - Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems ER - TY - CONF AU - Grawinkel, Matthias AU - Pargmann, Markus AU - Dömer, Hubert AU - Brinkmann, André ID - 2189 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André ID - 2190 T2 - Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) TI - Autonomic Resource Management Handling Delayed Configuration Effects ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CONF AU - Grawinkel, Matthias AU - Schäfer, Thorsten AU - Brinkmann, André AU - Hagemeyer, Jens AU - Porrmann, Mario ID - 2195 T2 - Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability ER - TY - CONF AU - Brinkmann, André AU - Gao, Yan AU - Korzeniowski, Miroslaw AU - Meister, Dirk ID - 2196 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Request Load Balancing for Highly Skewed Traffic in P2P Networks ER - TY - CONF AU - Gesing, Sandra AU - Grunzke, Richard AU - Balaskó, Ákos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Herres-Pawlis, Sonja AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Packschies, Lars AU - Schäfer, Patrick AU - Schuller, Bernd AU - Schuster, Johannes AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Wewior, Martin AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2197 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Granular Security for a Science Gateway in Structural Bioinformatics ER - TY - CONF AU - Gesing, Sandra AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Warzecha, Klaus-Dieter AU - Wewior, Martin AU - Kohlbacher, Oliver ID - 2199 T2 - Proc. EGI User Forum TI - A Science Gateway for Molecular Simulations ER - TY - CONF AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Krieger, Alexaner ID - 2203 SN - 978-0-7695-4572-1 T2 - Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) TI - Autonomic Resource Management with Support Vector Machines ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Gesing, Sandra AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Lang, Ulrich AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuster, Johannes AU - Steinke, Thomas AU - Warzecha, Klaus-Dieter AU - Wewior, Martin ID - 2205 T2 - Proc. of Grid Workflow Workshop (GWW) TI - MoSGrid: Progress of Workflow driven Chemical Simulations VL - 829 ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Klonowski, Marek AU - Korzeniowski, Miroslaw ID - 2217 T2 - Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) TI - SkewCCC+: A Heterogeneous Distributed Hash Table VL - 6490 ER - TY - CONF AU - Wewior, Martin AU - Packschies, Lars AU - Blunk, Dirk AU - Wickeroth, Daniel AU - Warzecha, Klaus-Dieter AU - Herres-Pawlis, Sonja AU - Gesing, Sandra AU - Breuers, Sebastian AU - Krüger, Jens AU - Birkenheuer, Georg AU - Lang, Ulrich ID - 2218 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations ER - TY - CONF AU - Gesing, Sandra AU - Marton, Istvan AU - Birkenheuer, Georg AU - Schuller, Bernd AU - Grunzke, Richard AU - Krüger, Jens AU - Breuers, Sebastian AU - Blunk, Dirk AU - Fels, Gregor AU - Packschies, Lars AU - Brinkmann, André AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos ID - 2219 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Workflow Interoperability in a Grid Portal for Molecular Simulations ER - TY - CONF AU - Gao, Yan AU - Meister, Dirk AU - Brinkmann, André ID - 2225 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2229 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Balls into Bins with Related Random Choices ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2230 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD) ER - TY - CONF AU - Lensing, Paul Hermann AU - Meister, Dirk AU - Brinkmann, André ID - 2231 T2 - Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI) TI - hashFS: Applying Hashing to Optimized File Systems for Small File Reads ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2232 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - Balls into Non-uniform Bins ER - TY - CONF AU - Bolte, Matthias AU - Sievers, Michael AU - Birkenheuer, Georg AU - Niehörster, Oliver AU - Brinkmann, André ID - 2234 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Non-intrusive Virtualization Management Using libvirt ER - TY - CONF AU - Birkenheuer, Georg AU - Breuers, Sebastian AU - Brinkmann, André AU - Blunk, Dirk AU - Fels, Gregor AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Packschies, Lars ID - 2236 T2 - Proc. of Grid Workflow Workshop (GWW) TI - Grid-Workflows in Molecular Science ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André AU - Fels, Gregor AU - Krüger, Jens AU - Simon, Jens ID - 2237 SN - 1552-5244 T2 - Proc. Int. Conf. on Cluster Computing (CLUSTER) TI - Enforcing SLAs in Scientific Clouds ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 809 T2 - Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers TI - Risk Aware Overbooking for Commercial Grids ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2227 SN - 978-1-4244-7911-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Höing, Andre AU - Scherp, Guido AU - Gudenkauf, Stefan AU - Meister, Dirk AU - Brinkmann, André ID - 2239 T2 - Proc. Int. Conf. on Service Oriented Computing (ICSOC) TI - An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL VL - 5900 ER - TY - CONF AU - Niehörster, Oliver AU - Birkenheuer, Georg AU - Brinkmann, André AU - Blunk, Dirk AU - Elsässer, Brigitta AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Niehörster, Julia AU - Packschies, Lars AU - Fels, Gregor ID - 2240 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Providing Scientific Software as a Service in Consideration of Service Level Agreements ER - TY - CONF AU - Birkenheuer, Georg AU - Carlson, Arthur AU - Fölling, Alexander AU - Högqvist, Mikael AU - Hoheisel, Andreas AU - Papaspyrou, Alexander AU - Rieger, Klaus AU - Schott, Bernhard AU - Ziegler, Wolfgang ID - 2260 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2264 T2 - Proc. of the Israeli Experimental Systems Conference (SYSTOR) TI - Multi-Level Comparison of Data Deduplication in a Backup Scenario ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 818 T2 - Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers TI - The Gain of Overbooking ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Beutel, Jan AU - Gruber, Stephan AU - Hasler, Andi AU - Lim, Roman AU - Meier, Andreas AU - Plessl, Christian AU - Talzi, Igor AU - Thiele, Lothar AU - Tschudin, Christian AU - Woehrle, Matthias AU - Yuecel, Mustafa ID - 2352 KW - WSN KW - PermaSense SN - 978-1-4244-5108-1 T2 - Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN) TI - PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1974 T2 - Proc. Int. Conf. on Risks and Security of Internet and Systems TI - Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures ER - TY - CONF AB - Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1975 T2 - Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies TI - Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems ER - TY - CONF AB - Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1976 T2 - Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems TI - Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1978 T2 - Proc. Int. Conf. on Grid Computing and Applications (GCA) TI - Germany, Belgium, France, and Back Again: Job Migration using Globus ER - TY - CONF AB - OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1980 T2 - Proc. Int. Conf. on Services Computing (SCC) TI - Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids ER - TY - CONF AB - Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1981 SN - 978-0-7695-3177-9 T2 - Proc. Int. Conf. on Grid and Pervasive Computing (GPC) TI - Job Migration and Fault Tolerance in SLA-aware Resource Management Systems ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ED - Gonzalez, T. F. ID - 1983 SN - 978-0-88986-773-4 T2 - Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS) TI - Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2355 T2 - Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS) TI - Redundant Data Placement Strategies for Cluster Storage Environments ER - TY - CONF AU - Brinkmann, André AU - Gudenkauf, Stefan AU - Hasselbring, Wilhelm AU - Höing, André AU - Karl, Holger AU - Kao, Odej AU - Nitsche, Holger AU - Scherp, Guido ID - 2356 T2 - Proc. Cracow Grid Workshop (CGW) TI - Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, André AU - Dömer, Hubert AU - Effert, Sascha AU - Konersmann, Christoph AU - Niehörster, Oliver AU - Simon, Jens ID - 2357 T2 - Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management TI - Virtual Supercomputer for HPC and HTC ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Battré, Dominic AU - Birkenheuer, Georg AU - Deora, Vikas AU - Hovestadt, Matthias AU - Rana, Omer AU - Wäldrich, Oliver ID - 2359 T2 - Proc. Cracow Grid Workshop (CGW) TI - Guarantee and Penalty Clauses for Service Level Agreements ER - TY - CONF AU - Richert, Willi AU - Niehörster, Oliver AU - Koch, Markus ID - 2360 T2 - Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS) TI - Layered understanding for sporadic imitation in a multi-robot scenario ER - TY - CONF AU - Lietsch, Stefan AU - Zabel, Henning AU - Laroque, Christoph ID - 2363 T2 - Proc. ASME Computers and Information in Engineering Conference (CIE) TI - Computational Steering Of Interactive Material Flow Simulations ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER - TY - CONF AU - Lietsch, Stefan AU - Hermann Lensing, Paul ID - 2368 SN - 978-84-9830-164-9 T2 - Proc. Int. Symp. on Image/Video Communications over fixed and mobile networks (ISVC) TI - CUDA-based, parallel JPEG Compression for Remote Rendering ER - TY - CONF AU - Birkenheuer, Georg AU - Hovestadt, Matthias AU - Kao, Odej AU - Voß, Kerstin ID - 2369 T2 - Proc. Int. Conf. on Grid Computing & Applications (GCA) TI - Overbooking in Planning Based Scheduling Systems ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2371 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Data Replication in P2P Environments ER - TY - CONF AU - Griese, Björn AU - Brinkmann, André AU - Porrmann, Mario ID - 2374 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - SelfS – A Real-Time Protocol for Virtual Ring Topologies ER - TY - CONF AU - Voss, Kerstin ID - 2375 T2 - Proc. Int. Conf. on Networking and Services (ICNS) TI - Recursive Evaluation of Fault Tolerance Mechanisms for SLA Management ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2380 T2 - Proc. of the GI/ITG KuVS Fachgespr ̈ach Virtualisierung TI - Storage Cluster Architectures ER - TY - CONF AU - Richert, Willi AU - Klompmaker, Florian AU - Niehörster, Oliver ID - 2382 T2 - Proc. IFIP Conf. on Biologically Inspired Cooperative Computing (BICC) TI - Guiding exploration by combining individual learning and imitation in societies of autonomous robots ER - TY - CONF AU - Lietsch, Stefan AU - Hermann Lensing, Paul ID - 2383 T2 - Proc. Int. Symp. on Visual Computing (ISVC) TI - GPU-Supported Image Compression for Remote Visualization - Realization and Benchmarking VL - 5358 ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Korzeniowski, Miroslaw ID - 2386 T2 - Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS) TI - Degree 3 Suffices: A Large-Scale Overlay for P2P Networks ER - TY - CONF AU - Battre, Dominic AU - Birkenheuer, Georg AU - Hovestadt, Matthias AU - Kao, Odej AU - Voss, Kerstin ID - 2387 T2 - Proc. Cracow Grid Workshop (CGW) TI - Applying Risk Management to Support SLA Provisioning ER -