@inproceedings{2193, author = {{Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, pages = {{223--226}}, publisher = {{IEEE Computer Society}}, title = {{{Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}}}, doi = {{10.1109/ASAP.2011.6043273}}, year = {{2011}}, } @inproceedings{656, abstract = {{In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.}}, author = {{Happe, Markus and Agne, Andreas and Plessl, Christian}}, booktitle = {{Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}}, pages = {{55--60}}, publisher = {{IEEE}}, title = {{{Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}}}, doi = {{10.1109/ReConFig.2011.59}}, year = {{2011}}, } @inproceedings{2200, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}}, isbn = {{978-1-4503-0554-9}}, keywords = {{design space exploration, LLVM, partitioning, performance, estimation, funding-intel}}, pages = {{177--180}}, publisher = {{ACM}}, title = {{{Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}}}, doi = {{10.1145/1950413.1950448}}, year = {{2011}}, } @inproceedings{2198, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Reconfigurable Architectures Workshop (RAW)}}, pages = {{278--285}}, publisher = {{IEEE Computer Society}}, title = {{{Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}}}, doi = {{10.1109/IPDPS.2011.153}}, year = {{2011}}, } @inproceedings{2217, author = {{Bienkowski, Marcin and Brinkmann, André and Klonowski, Marek and Korzeniowski, Miroslaw}}, booktitle = {{Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)}}, publisher = {{Springer}}, title = {{{SkewCCC+: A Heterogeneous Distributed Hash Table}}}, doi = {{10.1007/978-3-642-17653-1_18}}, volume = {{6490}}, year = {{2010}}, } @inproceedings{2218, author = {{Wewior, Martin and Packschies, Lars and Blunk, Dirk and Wickeroth, Daniel and Warzecha, Klaus-Dieter and Herres-Pawlis, Sonja and Gesing, Sandra and Breuers, Sebastian and Krüger, Jens and Birkenheuer, Georg and Lang, Ulrich}}, booktitle = {{Proc. Int. Workshop on Scientific Gateways (IWSG)}}, pages = {{39--43}}, publisher = {{Consorzio COMETA}}, title = {{{The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations}}}, year = {{2010}}, } @inproceedings{2219, author = {{Gesing, Sandra and Marton, Istvan and Birkenheuer, Georg and Schuller, Bernd and Grunzke, Richard and Krüger, Jens and Breuers, Sebastian and Blunk, Dirk and Fels, Gregor and Packschies, Lars and Brinkmann, André and Kohlbacher, Oliver and Kozlovszky, Miklos}}, booktitle = {{Proc. Int. Workshop on Scientific Gateways (IWSG)}}, pages = {{44--48}}, publisher = {{Consorzio COMETA}}, title = {{{Workflow Interoperability in a Grid Portal for Molecular Simulations}}}, year = {{2010}}, } @inproceedings{2225, author = {{Gao, Yan and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}}, pages = {{126--134}}, publisher = {{IEEE}}, title = {{{Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors}}}, doi = {{10.1109/NAS.2010.11}}, year = {{2010}}, } @inproceedings{2229, author = {{Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}}, booktitle = {{Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA)}}, pages = {{100--105}}, publisher = {{ACM}}, title = {{{Balls into Bins with Related Random Choices}}}, doi = {{10.1145/1810479.1810500}}, year = {{2010}}, } @inproceedings{2230, author = {{Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. Symp. on Mass Storage Systems and Technologies (MSST)}}, pages = {{1--6}}, publisher = {{IEEE Computer Society}}, title = {{{dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)}}}, doi = {{10.1109/MSST.2010.5496992}}, year = {{2010}}, } @inproceedings{2231, author = {{Lensing, Paul Hermann and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI)}}, pages = {{33--42}}, publisher = {{IEEE}}, title = {{{hashFS: Applying Hashing to Optimized File Systems for Small File Reads}}}, doi = {{10.1109/SNAPI.2010.12}}, year = {{2010}}, } @inproceedings{2232, author = {{Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS)}}, pages = {{1--10}}, publisher = {{IEEE}}, title = {{{Balls into Non-uniform Bins}}}, doi = {{10.1109/IPDPS.2010.5470355}}, year = {{2010}}, } @inproceedings{2234, author = {{Bolte, Matthias and Sievers, Michael and Birkenheuer, Georg and Niehörster, Oliver and Brinkmann, André}}, booktitle = {{Proc. Design, Automation and Test in Europe Conf. (DATE)}}, publisher = {{EDA Consortium}}, title = {{{Non-intrusive Virtualization Management Using libvirt}}}, year = {{2010}}, } @inproceedings{2236, author = {{Birkenheuer, Georg and Breuers, Sebastian and Brinkmann, André and Blunk, Dirk and Fels, Gregor and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Packschies, Lars}}, booktitle = {{Proc. of Grid Workflow Workshop (GWW)}}, pages = {{177--184}}, publisher = {{Gesellschaft für Informatik (GI)}}, title = {{{Grid-Workflows in Molecular Science}}}, year = {{2010}}, } @inproceedings{2237, author = {{Niehörster, Oliver and Brinkmann, André and Fels, Gregor and Krüger, Jens and Simon, Jens}}, booktitle = {{Proc. Int. Conf. on Cluster Computing (CLUSTER)}}, issn = {{1552-5244}}, pages = {{178--187}}, publisher = {{IEEE}}, title = {{{Enforcing SLAs in Scientific Clouds}}}, doi = {{10.1109/CLUSTER.2010.42}}, year = {{2010}}, } @inproceedings{809, author = {{Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}}, booktitle = {{Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers}}, pages = {{51--76}}, title = {{{Risk Aware Overbooking for Commercial Grids}}}, doi = {{10.1007/978-3-642-16505-4_4}}, year = {{2010}}, } @inproceedings{2223, author = {{Lübbers, Enno and Platzner, Marco and Plessl, Christian and Keller, Ariane and Plattner, Bernhard}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{225--231}}, publisher = {{CSREA Press}}, title = {{{Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware}}}, year = {{2010}}, } @inproceedings{2216, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, pages = {{67--72}}, publisher = {{IEEE Computer Society}}, title = {{{Pruning the Design Space for Just-In-Time Processor Customization}}}, doi = {{10.1109/ReConFig.2010.19}}, year = {{2010}}, } @inproceedings{2224, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{144--150}}, publisher = {{CSREA Press}}, title = {{{An Open Source Circuit Library with Benchmarking Facilities}}}, year = {{2010}}, } @inproceedings{2220, author = {{Andrews, David and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-140-6}}, pages = {{165}}, publisher = {{CSREA Press}}, title = {{{Configurable Processor Architectures: History and Trends}}}, year = {{2010}}, } @inproceedings{2226, author = {{Beisel, Tobias and Niekamp, Manuel and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}}, isbn = {{978-1-4244-6965-9}}, pages = {{65--72}}, publisher = {{IEEE Computer Society}}, title = {{{Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators}}}, doi = {{10.1109/ASAP.2010.5540798}}, year = {{2010}}, } @inproceedings{2206, author = {{Keller, Ariane and Plattner, Bernhard and Lübbers, Enno and Platzner, Marco and Plessl, Christian}}, booktitle = {{Proc. IEEE Globecom Workshop on Network of the Future (FutureNet)}}, isbn = {{978-1-4244-8864-3}}, pages = {{372--376}}, publisher = {{IEEE}}, title = {{{Reconfigurable Nodes for Future Networks}}}, doi = {{10.1109/GLOCOMW.2010.5700341}}, year = {{2010}}, } @inproceedings{2227, author = {{Woehrle, Matthias and Plessl, Christian and Thiele, Lothar}}, booktitle = {{Proc. Int. Conf. Networked Sensing Systems (INSS)}}, isbn = {{978-1-4244-7911-5}}, pages = {{245--248}}, publisher = {{IEEE}}, title = {{{Rupeas: Ruby Powered Event Analysis DSL}}}, doi = {{10.1109/INSS.2010.5572211}}, year = {{2010}}, } @inproceedings{2228, author = {{Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}}, booktitle = {{Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA)}}, editor = {{Hammami, Omar and Larrabee, Sandra}}, title = {{{Performance Estimation for the Exploration of CPU-Accelerator Architectures}}}, year = {{2010}}, } @inproceedings{2239, author = {{Höing, Andre and Scherp, Guido and Gudenkauf, Stefan and Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. Int. Conf. on Service Oriented Computing (ICSOC)}}, pages = {{301--315}}, publisher = {{Springer}}, title = {{{An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL}}}, doi = {{0.1007/978-3-642-10383-4_20}}, volume = {{5900}}, year = {{2009}}, } @inproceedings{2240, author = {{Niehörster, Oliver and Birkenheuer, Georg and Brinkmann, André and Blunk, Dirk and Elsässer, Brigitta and Herres-Pawlis, Sonja and Krüger, Jens and Niehörster, Julia and Packschies, Lars and Fels, Gregor}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, isbn = {{978-83-61433-01-9}}, pages = {{55--63}}, title = {{{Providing Scientific Software as a Service in Consideration of Service Level Agreements}}}, year = {{2009}}, } @inproceedings{2260, author = {{Birkenheuer, Georg and Carlson, Arthur and Fölling, Alexander and Högqvist, Mikael and Hoheisel, Andreas and Papaspyrou, Alexander and Rieger, Klaus and Schott, Bernhard and Ziegler, Wolfgang}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, isbn = {{978-83-61433-01-9}}, pages = {{96--103}}, title = {{{Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!}}}, year = {{2009}}, } @inproceedings{2264, author = {{Meister, Dirk and Brinkmann, André}}, booktitle = {{Proc. of the Israeli Experimental Systems Conference (SYSTOR)}}, pages = {{8:1--8:12}}, publisher = {{ACM}}, title = {{{Multi-Level Comparison of Data Deduplication in a Backup Scenario}}}, doi = {{10.1145/1534530.1534541}}, year = {{2009}}, } @inproceedings{818, author = {{Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}}, booktitle = {{Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers}}, pages = {{80--100}}, title = {{{The Gain of Overbooking}}}, doi = {{10.1007/978-3-642-04633-9_5}}, year = {{2009}}, } @inproceedings{2350, abstract = {{Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. }}, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}}, isbn = {{978-1-4244-4450-2}}, keywords = {{IMORC, interconnect, performance}}, pages = {{275--278}}, publisher = {{IEEE Computer Society}}, title = {{{IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}}}, doi = {{10.1109/FCCM.2009.25}}, year = {{2009}}, } @inproceedings{2262, abstract = {{In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. }}, author = {{Kaufmann, Paul and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}}, keywords = {{EvoCache, evolvable hardware, computer architecture}}, pages = {{11--18}}, publisher = {{IEEE Computer Society}}, title = {{{EvoCaches: Application-specific Adaptation of Cache Mapping}}}, year = {{2009}}, } @inproceedings{2352, author = {{Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and Yuecel, Mustafa}}, booktitle = {{Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}}, isbn = {{978-1-4244-5108-1}}, keywords = {{WSN, PermaSense}}, pages = {{265--276}}, publisher = {{IEEE Computer Society}}, title = {{{PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}}}, year = {{2009}}, } @inproceedings{2238, author = {{Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}}, isbn = {{978-0-7695-3917-1}}, keywords = {{IMORC, graphics}}, pages = {{119--124}}, publisher = {{IEEE Computer Society}}, title = {{{Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}}}, doi = {{10.1109/ReConFig.2009.32}}, year = {{2009}}, } @inproceedings{2261, author = {{Schumacher, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}}, isbn = {{978-1-4244-3892-1}}, issn = {{1946-1488}}, keywords = {{IMORC, NOC, KNN, accelerator}}, pages = {{338--344}}, publisher = {{IEEE}}, title = {{{An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}}}, year = {{2009}}, } @inproceedings{2263, abstract = {{In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. }}, author = {{Grad, Mariusz and Plessl, Christian}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-101-5}}, pages = {{319--322}}, publisher = {{CSREA Press}}, title = {{{Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}}}, year = {{2009}}, } @inproceedings{1974, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Risks and Security of Internet and Systems}}, title = {{{Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures}}}, year = {{2008}}, } @inproceedings{1975, abstract = {{Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies}}, title = {{{Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems}}}, doi = {{10.1007/978-3-540-88708-9_1}}, year = {{2008}}, } @inproceedings{1976, abstract = {{Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems}}, title = {{{Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids}}}, doi = {{10.1109/ICPP-W.2008.40}}, year = {{2008}}, } @inproceedings{1978, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Grid Computing and Applications (GCA)}}, title = {{{Germany, Belgium, France, and Back Again: Job Migration using Globus}}}, year = {{2008}}, } @inproceedings{1980, abstract = {{OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Services Computing (SCC)}}, title = {{{Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids}}}, doi = {{10.1109/SCC.2008.106}}, year = {{2008}}, } @inproceedings{1981, abstract = {{Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution.}}, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Grid and Pervasive Computing (GPC)}}, isbn = {{978-0-7695-3177-9}}, pages = {{43--48}}, title = {{{Job Migration and Fault Tolerance in SLA-aware Resource Management Systems}}}, doi = {{10.1109/GPC.WORKSHOPS.2008.71}}, year = {{2008}}, } @inproceedings{1983, author = {{Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}}, booktitle = {{Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS)}}, editor = {{Gonzalez, T. F.}}, isbn = {{978-0-88986-773-4}}, pages = {{212--218}}, title = {{{Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance}}}, year = {{2008}}, } @inproceedings{2355, author = {{Brinkmann, André and Effert, Sascha}}, booktitle = {{Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS)}}, pages = {{551--554}}, publisher = {{Springer}}, title = {{{Redundant Data Placement Strategies for Cluster Storage Environments}}}, doi = {{10.1007/978-3-540-92221-6_38}}, year = {{2008}}, } @inproceedings{2356, author = {{Brinkmann, André and Gudenkauf, Stefan and Hasselbring, Wilhelm and Höing, André and Karl, Holger and Kao, Odej and Nitsche, Holger and Scherp, Guido}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, pages = {{103--110}}, title = {{{Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware}}}, year = {{2008}}, } @inproceedings{2357, author = {{Birkenheuer, Georg and Brinkmann, André and Dömer, Hubert and Effert, Sascha and Konersmann, Christoph and Niehörster, Oliver and Simon, Jens}}, booktitle = {{Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management}}, pages = {{37--49}}, publisher = {{Leibniz-Rechenzentrum}}, title = {{{Virtual Supercomputer for HPC and HTC}}}, year = {{2008}}, } @inproceedings{2358, author = {{Beisel, Tobias and Lietsch, Stefan and Thielemans, Kris}}, booktitle = {{IEEE Nuclear Science Symposium Conference Record (NSS)}}, pages = {{4161--4168}}, publisher = {{IEEE}}, title = {{{A method for OSEM PET reconstruction on parallel architectures using STIR}}}, doi = {{10.1109/NSSMIC.2008.4774198}}, year = {{2008}}, } @inproceedings{2359, author = {{Battré, Dominic and Birkenheuer, Georg and Deora, Vikas and Hovestadt, Matthias and Rana, Omer and Wäldrich, Oliver}}, booktitle = {{Proc. Cracow Grid Workshop (CGW)}}, pages = {{213--220}}, title = {{{Guarantee and Penalty Clauses for Service Level Agreements}}}, year = {{2008}}, } @inproceedings{2360, author = {{Richert, Willi and Niehörster, Oliver and Koch, Markus}}, booktitle = {{Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS)}}, publisher = {{IEEE}}, title = {{{Layered understanding for sporadic imitation in a multi-robot scenario}}}, doi = {{10.1109/IROS.2008.4650817}}, year = {{2008}}, } @inproceedings{2363, author = {{Lietsch, Stefan and Zabel, Henning and Laroque, Christoph}}, booktitle = {{Proc. ASME Computers and Information in Engineering Conference (CIE)}}, pages = {{1493--1502}}, publisher = {{ASME}}, title = {{{Computational Steering Of Interactive Material Flow Simulations}}}, doi = {{10.1115/DETC2008-49405}}, year = {{2008}}, } @inproceedings{2365, author = {{Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-60132-064-7}}, pages = {{245--251}}, publisher = {{CSREA Press}}, title = {{{The GOmputer: Accelerating GO with FPGAs}}}, year = {{2008}}, }