[{"user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","status":"public","date_created":"2023-07-28T12:04:27Z","publication_status":"published","quality_controlled":"1","author":[{"last_name":"Karp","full_name":"Karp, Martin","first_name":"Martin"},{"last_name":"Podobas","full_name":"Podobas, Artur","first_name":"Artur"},{"first_name":"Niclas","full_name":"Jansson, Niclas","last_name":"Jansson"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Schlatter, Philipp","first_name":"Philipp","last_name":"Schlatter"},{"last_name":"Markidis","full_name":"Markidis, Stefano","first_name":"Stefano"}],"publisher":"IEEE","publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"doi":"10.1109/ipdps49936.2021.00116","_id":"46195","date_updated":"2023-07-28T12:05:15Z","language":[{"iso":"eng"}],"type":"conference","year":"2021","citation":{"ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116."}},{"publication":"2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)","department":[{"_id":"27"},{"_id":"518"}],"publisher":"IEEE","quality_controlled":"1","author":[{"full_name":"Karp, Martin","first_name":"Martin","last_name":"Karp"},{"last_name":"Podobas","full_name":"Podobas, Artur","first_name":"Artur"},{"last_name":"Jansson","full_name":"Jansson, Niclas","first_name":"Niclas"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"last_name":"Schlatter","full_name":"Schlatter, Philipp","first_name":"Philipp"},{"first_name":"Stefano","full_name":"Markidis, Stefano","last_name":"Markidis"}],"date_created":"2022-02-21T14:26:37Z","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"status":"public","publication_status":"published","user_id":"3145","title":"High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection","language":[{"iso":"eng"}],"type":"conference","year":"2021","citation":{"bibtex":"@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }","mla":"Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.","apa":"Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116","ama":"Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116","chicago":"Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.","ieee":"M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.","short":"M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021."},"date_updated":"2024-01-22T09:59:13Z","_id":"29937","doi":"10.1109/ipdps49936.2021.00116"},{"_id":"32242","date_updated":"2022-06-28T07:27:19Z","year":"2020","type":"preprint","citation":{"short":"V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020).","ieee":"V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020.","chicago":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","ama":"Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020.","apa":"Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813.","mla":"Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020.","bibtex":"@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }"},"language":[{"iso":"eng"}],"title":"Multi-Armed Bandits with Censored Consumption of Resources","user_id":"15278","abstract":[{"lang":"eng","text":"We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms."}],"external_id":{"arxiv":["2011.00813"]},"date_created":"2022-06-28T07:26:54Z","project":[{"_id":"52","name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"status":"public","department":[{"_id":"27"}],"publication":"arXiv:2011.00813","author":[{"first_name":"Viktor","full_name":"Bengs, Viktor","last_name":"Bengs"},{"full_name":"Hüllermeier, Eyke","first_name":"Eyke","last_name":"Hüllermeier"}]},{"main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9355245"}],"type":"conference","year":"2020","citation":{"chicago":"Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.","apa":"Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084","ama":"Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084","bibtex":"@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }","mla":"Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.","short":"M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.","ieee":"M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084."},"page":"1127-1140","_id":"16898","conference":{"name":"SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","location":"Atlanta, GA, US"},"author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"orcid":"0000-0002-6268-539","full_name":"Schade, Robert","first_name":"Robert","id":"75963","last_name":"Schade"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"}],"quality_controlled":"1","publisher":"IEEE Computer Society","publication":"Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)","status":"public","date_created":"2020-04-28T14:44:21Z","abstract":[{"lang":"eng","text":"Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs."}],"user_id":"75963","language":[{"iso":"eng"}],"date_updated":"2023-08-02T14:55:59Z","doi":"10.1109/SC41405.2020.00084","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"},{"grant_number":"PL 595/2-1 / 320898746","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"place":"Los Alamitos, CA, USA","external_id":{"arxiv":["2004.10811"]},"title":"A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K"},{"date_created":"2021-04-16T10:17:22Z","status":"public","keyword":["FPGA","OpenCL","High Level Synthesis","HPC benchmarking"],"publication":"2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)","quality_controlled":"1","author":[{"first_name":"Marius","full_name":"Meyer, Marius","last_name":"Meyer","id":"40778"},{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"user_id":"15278","abstract":[{"lang":"eng","text":"FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community."}],"type":"conference","citation":{"ama":"Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007","apa":"Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007","chicago":"Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.","mla":"Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.","bibtex":"@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }","short":"M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.","ieee":"M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007."},"year":"2020","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9306963"}],"_id":"21632","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication_identifier":{"isbn":["9781665415927"]},"publication_status":"published","department":[{"_id":"27"},{"_id":"518"}],"related_material":{"link":[{"url":"https://github.com/pc2/HPCC_FPGA","description":"Official repository of the benchmark suite on GitHub","relation":"supplementary_material"}]},"title":"Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite","language":[{"iso":"eng"}],"doi":"10.1109/h2rc51942.2020.00007","date_updated":"2023-09-26T11:42:53Z"},{"date_updated":"2022-01-06T06:52:26Z","doi":"10.1109/ICFPT47387.2019.00020","language":[{"iso":"eng"}],"title":"OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs","department":[{"_id":"27"},{"_id":"518"}],"project":[{"_id":"33","grant_number":"01|H16005","name":"HighPerMeshes"},{"grant_number":"PL 595/2-1","name":"Performance and Efficiency in HPC with Custom Computing","_id":"32"}],"conference":{"name":"International Conference on Field-Programmable Technology (FPT)"},"_id":"15478","type":"conference","year":"2019","citation":{"apa":"Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020","ama":"Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020","chicago":"Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020.","mla":"Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.","bibtex":"@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }","short":"P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.","ieee":"P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019."},"abstract":[{"text":"Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.","lang":"eng"}],"user_id":"3145","ddc":["004"],"file":[{"file_id":"15479","creator":"plessl","file_size":250559,"relation":"main_file","success":1,"date_updated":"2020-01-09T12:53:57Z","content_type":"application/pdf","date_created":"2020-01-09T12:53:57Z","file_name":"gorlani19_fpt.pdf","access_level":"closed"}],"file_date_updated":"2020-01-09T12:53:57Z","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","author":[{"full_name":"Gorlani, Paolo","first_name":"Paolo","id":"72045","last_name":"Gorlani"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE","date_created":"2020-01-09T12:54:48Z","status":"public","has_accepted_license":"1"},{"publication":"Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)","keyword":["Scheduling Planning Mapping Workload management"],"author":[{"first_name":"Axel","full_name":"Keller, Axel","last_name":"Keller","id":"15274"}],"publisher":"Springer","volume":10773,"date_created":"2017-07-25T14:54:08Z","status":"public","abstract":[{"lang":"eng","text":"This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\\(^2\\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation."}],"user_id":"15274","page":"132-151","year":"2018","citation":{"ieee":"A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.","short":"A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.","bibtex":"@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }","mla":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8.","chicago":"Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8.","ama":"Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8","apa":"Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8"},"type":"conference","conference":{"end_date":"2017-06-02","start_date":"2017-06-02","name":"21st Workshop on Job Scheduling Strategies for Parallel Processing","location":"Orlando, FL, USA"},"_id":"22","intvolume":" 10773","department":[{"_id":"27"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-319-77398-8","978-3-319-77397-1"]},"editor":[{"last_name":"Klusáček","full_name":"Klusáček, D.","first_name":"D."},{"full_name":"Cirne, W.","first_name":"W.","last_name":"Cirne"},{"full_name":"Desai, N.","first_name":"N.","last_name":"Desai"}],"title":"A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems","series_title":"Lecture Notes in Computer Science","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:55:22Z","doi":"10.1007/978-3-319-77398-8_8"},{"abstract":[{"lang":"eng","text":"The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x."}],"ddc":["000"],"user_id":"15278","author":[{"id":"3145","last_name":"Kenter","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Gopinath","full_name":"Mahale, Gopinath","last_name":"Mahale"},{"first_name":"Samer","full_name":"Alhaddad, Samer","last_name":"Alhaddad","id":"42456"},{"id":"26059","last_name":"Grynko","full_name":"Grynko, Yevgen","first_name":"Yevgen"},{"first_name":"Christian","full_name":"Schmitt, Christian","last_name":"Schmitt"},{"last_name":"Afzal","first_name":"Ayesha","full_name":"Afzal, Ayesha"},{"last_name":"Hannig","full_name":"Hannig, Frank","first_name":"Frank"},{"last_name":"Förstner","id":"158","first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","keyword":["tet_topic_hpc"],"file_date_updated":"2018-11-02T14:45:05Z","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","file":[{"file_name":"08457652.pdf","date_created":"2018-11-02T14:45:05Z","access_level":"closed","creator":"ups","file_id":"5282","file_size":269130,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-11-02T14:45:05Z"}],"status":"public","has_accepted_license":"1","date_created":"2018-03-22T10:48:01Z","_id":"1588","conference":{"name":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)"},"year":"2018","type":"conference","citation":{"ieee":"T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.","short":"T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.","bibtex":"@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }","mla":"Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.","chicago":"Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.","apa":"Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037","ama":"Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037"},"title":"OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"}],"project":[{"grant_number":"01|H16005A","name":"HighPerMeshes","_id":"33"},{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"date_updated":"2023-09-26T11:47:52Z","doi":"10.1109/FCCM.2018.00037","language":[{"iso":"eng"}]},{"place":"New York, NY, USA","external_id":{"arxiv":["1710.10899"]},"title":"A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices","department":[{"_id":"27"},{"_id":"518"},{"_id":"304"}],"project":[{"name":"Performance and Efficiency in HPC with Custom Computing","grant_number":"PL 595/2-1 / 320898746","_id":"32"},{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"isbn":["978-1-4503-5891-0/18/07"]},"date_updated":"2023-09-26T11:48:12Z","doi":"10.1145/3218176.3218231","language":[{"iso":"eng"}],"abstract":[{"text":"We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.","lang":"eng"}],"user_id":"15278","quality_controlled":"1","publisher":"ACM","author":[{"first_name":"Michael","orcid":"0000-0002-5708-7632","full_name":"Lass, Michael","last_name":"Lass","id":"24135"},{"full_name":"Mohr, Stephan","first_name":"Stephan","last_name":"Mohr"},{"last_name":"Wiebeler","full_name":"Wiebeler, Hendrik","first_name":"Hendrik"},{"full_name":"Kühne, Thomas","first_name":"Thomas","id":"49079","last_name":"Kühne"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"publication":"Proc. Platform for Advanced Scientific Computing (PASC) Conference","keyword":["approximate computing","linear algebra","matrix inversion","matrix p-th roots","numeric algorithm","parallel computing"],"status":"public","date_created":"2018-03-22T10:53:01Z","_id":"1590","conference":{"location":"Basel, Switzerland","start_date":"2018-07-02","name":"Platform for Advanced Scientific Computing Conference (PASC)","end_date":"2018-07-04"},"type":"conference","citation":{"ieee":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.","short":"M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.","mla":"Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.","bibtex":"@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }","chicago":"Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.","ama":"Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231","apa":"Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231"},"year":"2018"},{"publisher":"ACM","quality_controlled":"1","author":[{"id":"8961","last_name":"Riebler","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","last_name":"Vaz","id":"30332"},{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"file_date_updated":"2018-11-02T14:43:37Z","keyword":["htrop"],"publication":"Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)","file":[{"file_size":447769,"file_id":"5281","creator":"ups","date_updated":"2018-11-02T14:43:37Z","content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-11-02T14:43:37Z","file_name":"p417-riebler.pdf","access_level":"closed"}],"has_accepted_license":"1","status":"public","date_created":"2018-03-08T14:45:18Z","ddc":["000"],"user_id":"15278","citation":{"apa":"Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534","ama":"Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534.","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","short":"H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534."},"type":"conference","year":"2018","_id":"1204","department":[{"_id":"27"},{"_id":"518"}],"publication_status":"published","publication_identifier":{"isbn":["9781450349826"]},"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - Subproject C2","grant_number":"160364472"}],"title":"Automated Code Acceleration Targeting Heterogeneous OpenCL Devices","language":[{"iso":"eng"}],"date_updated":"2023-09-26T11:47:23Z","doi":"10.1145/3178487.3178534"}]