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Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }"},"type":"conference","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:43:48Z","_id":"2193","doi":"10.1109/ASAP.2011.6043273","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"last_name":"Wiersema","id":"3118","first_name":"Tobias","full_name":"Wiersema, Tobias"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"}],"publisher":"IEEE Computer Society","date_created":"2018-04-03T14:37:14Z","project":[{"_id":"30","grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"status":"public","title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","user_id":"15278"},{"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:46:08Z","doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time."}],"user_id":"15278","ddc":["040"],"file":[{"date_created":"2018-03-14T13:49:39Z","file_name":"656-2011_happe_reconfig.pdf","access_level":"closed","file_size":502244,"file_id":"1220","creator":"florida","date_updated":"2018-03-14T13:49:39Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","file_date_updated":"2018-03-14T13:49:39Z","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:59Z","_id":"656","year":"2011","citation":{"short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). 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Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). 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Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. 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Int. 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Int. Workshop on Scientific Gateways (IWSG), 39–43. Consorzio COMETA, 2010.","ama":"Wewior M, Packschies L, Blunk D, et al. The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2010:39-43.","apa":"Wewior, M., Packschies, L., Blunk, D., Wickeroth, D., Warzecha, K.-D., Herres-Pawlis, S., … Lang, U. (2010). The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 39–43). Consorzio COMETA.","mla":"Wewior, Martin, et al. “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43.","bibtex":"@inproceedings{Wewior_Packschies_Blunk_Wickeroth_Warzecha_Herres-Pawlis_Gesing_Breuers_Krüger_Birkenheuer_et al._2010, title={The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Wewior, Martin and Packschies, Lars and Blunk, Dirk and Wickeroth, Daniel and Warzecha, Klaus-Dieter and Herres-Pawlis, Sonja and Gesing, Sandra and Breuers, Sebastian and Krüger, Jens and Birkenheuer, Georg and et al.}, year={2010}, pages={39–43} }","short":"M. Wewior, L. Packschies, D. Blunk, D. Wickeroth, K.-D. Warzecha, S. Herres-Pawlis, S. Gesing, S. Breuers, J. Krüger, G. Birkenheuer, U. Lang, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43.","ieee":"M. Wewior et al., “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 39–43."},"year":"2010","type":"conference"},{"year":"2010","citation":{"ieee":"S. Gesing et al., “Workflow Interoperability in a Grid Portal for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 44–48.","short":"S. Gesing, I. Marton, G. Birkenheuer, B. Schuller, R. Grunzke, J. Krüger, S. Breuers, D. Blunk, G. Fels, L. Packschies, A. Brinkmann, O. Kohlbacher, M. Kozlovszky, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","bibtex":"@inproceedings{Gesing_Marton_Birkenheuer_Schuller_Grunzke_Krüger_Breuers_Blunk_Fels_Packschies_et al._2010, title={Workflow Interoperability in a Grid Portal for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Marton, Istvan and Birkenheuer, Georg and Schuller, Bernd and Grunzke, Richard and Krüger, Jens and Breuers, Sebastian and Blunk, Dirk and Fels, Gregor and Packschies, Lars and et al.}, year={2010}, pages={44–48} }","mla":"Gesing, Sandra, et al. “Workflow Interoperability in a Grid Portal for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","ama":"Gesing S, Marton I, Birkenheuer G, et al. Workflow Interoperability in a Grid Portal for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2010:44-48.","apa":"Gesing, S., Marton, I., Birkenheuer, G., Schuller, B., Grunzke, R., Krüger, J., … Kozlovszky, M. (2010). Workflow Interoperability in a Grid Portal for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 44–48). Consorzio COMETA.","chicago":"Gesing, Sandra, Istvan Marton, Georg Birkenheuer, Bernd Schuller, Richard Grunzke, Jens Krüger, Sebastian Breuers, et al. “Workflow Interoperability in a Grid Portal for Molecular Simulations.” In Proc. Int. Workshop on Scientific Gateways (IWSG), 44–48. Consorzio COMETA, 2010."},"type":"conference","page":"44-48","_id":"2219","date_updated":"2022-01-06T06:55:28Z","status":"public","date_created":"2018-04-05T14:55:48Z","author":[{"last_name":"Gesing","full_name":"Gesing, Sandra","first_name":"Sandra"},{"first_name":"Istvan","full_name":"Marton, Istvan","last_name":"Marton"},{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"first_name":"Bernd","full_name":"Schuller, Bernd","last_name":"Schuller"},{"last_name":"Grunzke","full_name":"Grunzke, Richard","first_name":"Richard"},{"full_name":"Krüger, Jens","first_name":"Jens","last_name":"Krüger"},{"full_name":"Breuers, Sebastian","first_name":"Sebastian","last_name":"Breuers"},{"last_name":"Blunk","first_name":"Dirk","full_name":"Blunk, Dirk"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"first_name":"Lars","full_name":"Packschies, Lars","last_name":"Packschies"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"}],"publisher":"Consorzio COMETA","department":[{"_id":"27"}],"publication":"Proc. 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