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Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }","mla":"Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.","chicago":"Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.","apa":"Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/NAS.2013.18","ama":"Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97. doi:10.1109/NAS.2013.18","ieee":"J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2013, pp. 88–97.","short":"J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97."},"type":"conference","page":"88-97"},{"publisher":"IEEE","author":[{"first_name":"Server","full_name":"Kasap, Server","last_name":"Kasap"},{"last_name":"Redif","full_name":"Redif, Soydan","first_name":"Soydan"}],"department":[{"_id":"27"},{"_id":"78"}],"publication":"Proc. IEEE Signal Processing and Communications Conf. (SUI)","status":"public","date_created":"2018-03-26T14:48:53Z","title":"FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm","user_id":"24135","year":"2013","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.","ama":"Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530","apa":"Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530","bibtex":"@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }","mla":"Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.","short":"S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.","ieee":"S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013."},"type":"conference","_id":"1786","date_updated":"2022-01-06T06:53:20Z","doi":"10.1109/SIU.2013.6531530"},{"citation":{"ieee":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013.","short":"P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.","bibtex":"@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }","mla":"Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148.","ama":"Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148","apa":"Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148","chicago":"Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148."},"year":"2013","type":"conference","date_updated":"2022-01-06T06:53:22Z","_id":"1788","doi":"10.1109/IPDPSW.2013.148","publisher":"IEEE","author":[{"last_name":"Berenbrink","first_name":"Petra","full_name":"Berenbrink, Petra"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"first_name":"Tom","full_name":"Friedetzky, Tom","last_name":"Friedetzky"},{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"last_name":"Nagel","first_name":"Lars","full_name":"Nagel, Lars"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-26T14:52:56Z","title":"Distributing Storage in Cloud Environments","user_id":"24135"},{"date_updated":"2022-01-06T06:53:23Z","_id":"1793","citation":{"short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182.","apa":"Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013.","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82.","bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }"},"year":"2013","type":"conference","page":"175-182","title":"File Recipe Compression in Data Deduplication Systems","user_id":"24135","author":[{"last_name":"Meister","first_name":"Dirk","full_name":"Meister, Dirk"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Süß","first_name":"Tim","full_name":"Süß, Tim"}],"publisher":"USENIX Association","department":[{"_id":"27"}],"publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","status":"public","date_created":"2018-03-26T15:16:03Z"},{"_id":"528","page":"386-389","type":"conference","year":"2013","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.","apa":"Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389."},"user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES."}],"date_created":"2017-10-17T12:42:35Z","has_accepted_license":"1","status":"public","file":[{"file_name":"528-plessl13_fpt.pdf","date_created":"2018-03-15T10:36:08Z","access_level":"closed","file_size":822680,"creator":"florida","file_id":"1294","date_updated":"2018-03-15T10:36:08Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"file_date_updated":"2018-03-15T10:36:08Z","keyword":["coldboot"],"publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","author":[{"last_name":"Riebler","id":"8961","first_name":"Heinrich","full_name":"Riebler, Heinrich"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Christoph","full_name":"Sorge, Christoph","last_name":"Sorge"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"IEEE","quality_controlled":"1","doi":"10.1109/FPT.2013.6718394","date_updated":"2023-09-26T13:37:35Z","language":[{"iso":"eng"}],"title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"13","name":"SFB 901 - Subproject C1"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"language":[{"iso":"eng"}],"doi":"10.1109/ISORC.2013.6913232","date_updated":"2023-09-26T13:38:20Z","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","year":"2013","type":"conference","citation":{"short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.","ama":"Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232","apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232","bibtex":"@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }","mla":"Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232."},"_id":"505","status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:30Z","file":[{"content_type":"application/pdf","date_updated":"2018-03-15T13:38:56Z","relation":"main_file","success":1,"file_size":1040834,"creator":"florida","file_id":"1308","access_level":"closed","file_name":"505-Plessl13_seus.pdf","date_created":"2018-03-15T13:38:56Z"}],"publisher":"IEEE","quality_controlled":"1","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"first_name":"Peter","full_name":"Kling, Peter","last_name":"Kling"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Meyer auf der Heide, Friedhelm","first_name":"Friedhelm","id":"15523","last_name":"Meyer auf der Heide"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","file_date_updated":"2018-03-15T13:38:56Z","user_id":"15278","ddc":["040"],"abstract":[{"lang":"eng","text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas."}]},{"title":"Parallel Macro Pipelining on the Intel SCC Many-Core Computer","user_id":"15278","place":"Washington, DC, USA","publication_identifier":{"isbn":["978-0-7695-4979-8"]},"status":"public","date_created":"2018-03-26T14:51:05Z","project":[{"grant_number":"01|H11004A","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Suess","first_name":"Tim","full_name":"Suess, Tim"},{"last_name":"Schoenrock","first_name":"Andrew","full_name":"Schoenrock, Andrew"},{"full_name":"Meisner, Sebastian","first_name":"Sebastian","last_name":"Meisner"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"},{"_id":"63"}],"publication":"Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)","doi":"10.1109/IPDPSW.2013.136","_id":"1787","date_updated":"2023-09-26T13:38:05Z","type":"conference","year":"2013","citation":{"bibtex":"@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }","mla":"Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.","ama":"Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136","apa":"Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136","chicago":"Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.","ieee":"T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.","short":"T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73."},"page":"64-73","language":[{"iso":"eng"}]},{"page":"135-140","citation":{"chicago":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125.","ama":"Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125","apa":"Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125","bibtex":"@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }","mla":"Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.","short":"S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.","ieee":"S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140."},"type":"conference","year":"2012","doi":"10.1109/FPT.2012.6412125","_id":"2097","date_updated":"2022-01-06T06:54:42Z","date_created":"2018-03-29T14:34:48Z","status":"public","publication":"Proc. Int. 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EGI Community Forum, 2012.","bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={The MoSGrid Community From National to International Scale}, booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012.","ieee":"S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012."},"year":"2012","type":"conference"},{"title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","user_id":"24135","volume":"PoS(EGICF12-EMITC2)050","status":"public","date_created":"2018-04-03T09:15:35Z","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"last_name":"Birkenheuer","first_name":"Georg","full_name":"Birkenheuer, Georg"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"first_name":"Richard","full_name":"Grunzke, Richard","last_name":"Grunzke"},{"first_name":"Peter","full_name":"Kacsuk, Peter","last_name":"Kacsuk"},{"last_name":"Kohlbacher","first_name":"Oliver","full_name":"Kohlbacher, Oliver"},{"last_name":"Kozlovszky","first_name":"Miklos","full_name":"Kozlovszky, Miklos"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"last_name":"Müller-Pfefferkorn","first_name":"Ralph","full_name":"Müller-Pfefferkorn, Ralph"},{"first_name":"Patrick","full_name":"Schäfer, Patrick","last_name":"Schäfer"},{"first_name":"Thomas","full_name":"Steinke, Thomas","last_name":"Steinke"}],"department":[{"_id":"27"}],"publication":"Proceedings of Science","date_updated":"2022-01-06T06:55:13Z","_id":"2178","type":"conference","citation":{"bibtex":"@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }","mla":"Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012.","ama":"Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.","apa":"Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050).","chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.","ieee":"S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050.","short":"S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012."},"year":"2012"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:39:13Z","doi":"10.1109/FPL.2012.6339370","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?","year":"2012","citation":{"mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370","apa":"Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196."},"type":"conference","page":"189-196","_id":"2106","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"author":[{"last_name":"Meyer","first_name":"Björn","full_name":"Meyer, Björn"},{"full_name":"Schumacher, Jörn","first_name":"Jörn","last_name":"Schumacher"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian"},{"first_name":"Jens","orcid":"0000-0001-7059-9862","full_name":"Förstner, Jens","last_name":"Förstner","id":"158"}],"publisher":"IEEE","quality_controlled":"1","file_date_updated":"2019-02-13T09:04:46Z","keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2019-02-13T09:04:46Z","creator":"fossie","file_id":"7638","file_size":2148787,"access_level":"closed","date_created":"2019-02-13T09:04:46Z","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf"}],"status":"public","has_accepted_license":"1","date_created":"2018-03-29T15:04:25Z","abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"ddc":["000"],"user_id":"15278"},{"type":"conference","year":"2012","citation":{"ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745","apa":"Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745."},"page":"1-8","_id":"615","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:51Z","quality_controlled":"1","publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Hangmann, Hendrik","first_name":"Hendrik","last_name":"Hangmann"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T06:48:32Z","file":[{"date_created":"2018-03-15T06:48:32Z","file_name":"615-ReConFig12_01.pdf","access_level":"closed","file_size":730144,"creator":"florida","file_id":"1246","date_updated":"2018-03-15T06:48:32Z","content_type":"application/pdf","relation":"main_file","success":1}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators"},{"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2012.6416773","date_updated":"2023-09-26T13:41:08Z","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","citation":{"mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773","apa":"Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.","short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8."},"type":"conference","year":"2012","page":"1-8","_id":"591","has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:47Z","quality_controlled":"1","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","id":"3145","last_name":"Kenter"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Schmitz, Henning","first_name":"Henning","last_name":"Schmitz"}],"publisher":"IEEE","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-15T08:33:18Z","file":[{"file_size":371235,"file_id":"1257","creator":"florida","content_type":"application/pdf","date_updated":"2018-03-15T08:33:18Z","success":1,"relation":"main_file","date_created":"2018-03-15T08:33:18Z","file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed"}],"ddc":["040"],"user_id":"15278","abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}]},{"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","grant_number":"257906","name":"Engineering Proprioception in Computing Systems"}],"title":"Hardware/Software Platform for Self-aware Compute Nodes","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:41:36Z","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","file_date_updated":"2018-03-15T08:14:17Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"quality_controlled":"1","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T08:14:17Z","creator":"florida","file_id":"1249","file_size":146789,"access_level":"closed","date_created":"2018-03-15T08:14:17Z","file_name":"609-happe12_fpl_awareness.pdf"}],"date_created":"2017-10-17T12:42:50Z","status":"public","has_accepted_license":"1","abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"ddc":["040"],"user_id":"15278","page":"8-9","citation":{"ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.","apa":"Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012."},"year":"2012","type":"conference","_id":"609"},{"language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:42:54Z","doi":"10.1109/HPCSim.2012.6266973","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"}],"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","year":"2012","type":"conference","citation":{"chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.","ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973."},"page":"559-565","_id":"567","author":[{"first_name":"Pablo","full_name":"Barrio, Pablo","last_name":"Barrio"},{"last_name":"Carreras","full_name":"Carreras, Carlos","first_name":"Carlos"},{"last_name":"Sierra","full_name":"Sierra, Roberto","first_name":"Roberto"},{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publisher":"IEEE","quality_controlled":"1","publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","file_date_updated":"2018-03-15T10:20:24Z","file":[{"date_created":"2018-03-15T10:20:24Z","file_name":"567-ba-ca-12a.pdf","access_level":"closed","file_size":288508,"creator":"florida","file_id":"1275","content_type":"application/pdf","date_updated":"2018-03-15T10:20:24Z","relation":"main_file","success":1}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:42Z","abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"ddc":["040"],"user_id":"15278"},{"title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","name":"Engineering Proprioception in Computing Systems","_id":"31"}],"date_updated":"2023-09-26T13:42:03Z","doi":"10.1109/FPL.2012.6339370","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"user_id":"15278","ddc":["040"],"file":[{"file_name":"612-ruething_fpl12.pdf","date_created":"2018-03-15T06:49:03Z","access_level":"closed","creator":"florida","file_id":"1247","file_size":202923,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T06:49:03Z"}],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","file_date_updated":"2018-03-15T06:49:03Z","quality_controlled":"1","publisher":"IEEE","author":[{"last_name":"Rüthing","full_name":"Rüthing, Christoph","first_name":"Christoph"},{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"last_name":"Agne","first_name":"Andreas","full_name":"Agne, Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"}],"date_created":"2017-10-17T12:42:51Z","status":"public","has_accepted_license":"1","_id":"612","page":"559-562","citation":{"apa":"Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370","ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370."},"type":"conference","year":"2012"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS).","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. 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(2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69","ama":"Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69","chicago":"Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69.","mla":"Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. 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Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments."}],"title":"Rule Based Mapping of Virtual Machines in Clouds","user_id":"15274","author":[{"last_name":"Kleineweber","full_name":"Kleineweber, Christoph","first_name":"Christoph"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publication":"Proc. Int. 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Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds.","lang":"eng"}],"language":[{"iso":"eng"}],"citation":{"ieee":"O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","short":"O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.","bibtex":"@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster, Oliver and Keller, Axel and Brinkmann, André}, year={2011} }","mla":"Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.","chicago":"Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. 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Washington, DC: IEEE Computer Society. https://doi.org/10.1109/HiPC.2011.6152745","chicago":"Miranda, Alberto, Sascha Effert, Yangwook Kang, Ethan Miller, André Brinkmann, and Toni Cortes. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” In Proc. Int. Conf. on High Performance Computing (HIPC), 1–10. Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745.","bibtex":"@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }","mla":"Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745.","short":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, Washington, DC, 2011, pp. 1–10.","ieee":"A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, and T. Cortes, “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems,” in Proc. Int. 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Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.","apa":"Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) (pp. 138–145). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/CloudCom.2011.28","ama":"Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145. doi:10.1109/CloudCom.2011.28","bibtex":"@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }","mla":"Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.","short":"O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA, 2011, pp. 138–145.","ieee":"O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed Configuration Effects,” in Proc. IEEE Int. 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Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.","short":"B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63."},"page":"60-63"},{"date_updated":"2023-09-26T13:43:48Z","_id":"2193","doi":"10.1109/ASAP.2011.6043273","citation":{"mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. 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Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"has_accepted_license":"1","status":"public","date_created":"2017-10-17T12:42:59Z","file":[{"file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z","access_level":"closed","file_id":"1220","creator":"florida","file_size":502244,"relation":"main_file","success":1,"content_type":"application/pdf","date_updated":"2018-03-14T13:49:39Z"}],"publisher":"IEEE","quality_controlled":"1","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"first_name":"Andreas","full_name":"Agne, Andreas","last_name":"Agne"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-14T13:49:39Z","_id":"656","citation":{"bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. 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Korzeniowski, “SkewCCC+: A Heterogeneous Distributed Hash Table,” in Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), 2010, vol. 6490.","short":"M. Bienkowski, A. Brinkmann, M. Klonowski, M. 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Revised Papers, 2009, pp. 80–100, doi:10.1007/978-3-642-04633-9_5.","bibtex":"@inproceedings{Birkenheuer_Brinkmann_Karl_2009, title={The Gain of Overbooking}, DOI={10.1007/978-3-642-04633-9_5}, booktitle={Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers}, author={Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}, year={2009}, pages={80–100} }","short":"G. Birkenheuer, A. Brinkmann, H. Karl, in: Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100.","ieee":"G. Birkenheuer, A. Brinkmann, and H. Karl, “The Gain of Overbooking,” in Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100."},"user_id":"24135","title":"The Gain of Overbooking","date_created":"2017-11-27T10:22:26Z","status":"public","department":[{"_id":"75"},{"_id":"27"}],"publication":"Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers","author":[{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Brinkmann, Andre","first_name":"Andre","last_name":"Brinkmann"},{"first_name":"Holger","full_name":"Karl, Holger","last_name":"Karl","id":"126"}]},{"date_updated":"2023-09-26T13:51:44Z","doi":"10.1109/FCCM.2009.25","language":[{"iso":"eng"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]},"_id":"2350","page":"275-278","year":"2009","citation":{"apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25."},"type":"conference","abstract":[{"lang":"eng","text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. "}],"user_id":"15278","publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","keyword":["IMORC","interconnect","performance"],"author":[{"last_name":"Schumacher","first_name":"Tobias","full_name":"Schumacher, Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"quality_controlled":"1","publisher":"IEEE Computer Society","date_created":"2018-04-16T15:05:52Z","status":"public"},{"abstract":[{"text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. ","lang":"eng"}],"place":"Los Alamitos, CA, USA","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","user_id":"15278","publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","keyword":["EvoCache","evolvable hardware","computer architecture"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publisher":"IEEE Computer Society","quality_controlled":"1","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"16153","last_name":"Plessl","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2018-04-06T15:18:24Z","status":"public","date_updated":"2023-09-26T13:53:11Z","_id":"2262","page":"11-18","citation":{"chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18."},"year":"2009","type":"conference","language":[{"iso":"eng"}]},{"author":[{"last_name":"Beutel","first_name":"Jan","full_name":"Beutel, Jan"},{"full_name":"Gruber, Stephan","first_name":"Stephan","last_name":"Gruber"},{"last_name":"Hasler","full_name":"Hasler, Andi","first_name":"Andi"},{"last_name":"Lim","first_name":"Roman","full_name":"Lim, Roman"},{"last_name":"Meier","full_name":"Meier, Andreas","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"last_name":"Talzi","full_name":"Talzi, Igor","first_name":"Igor"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"},{"last_name":"Tschudin","full_name":"Tschudin, Christian","first_name":"Christian"},{"first_name":"Matthias","full_name":"Woehrle, Matthias","last_name":"Woehrle"},{"full_name":"Yuecel, Mustafa","first_name":"Mustafa","last_name":"Yuecel"}],"publisher":"IEEE Computer Society","quality_controlled":"1","publication":"Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)","keyword":["WSN","PermaSense"],"department":[{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["978-1-4244-5108-1"]},"status":"public","date_created":"2018-04-16T15:08:07Z","extern":"1","place":"Washington, DC, USA","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","user_id":"15278","type":"conference","year":"2009","citation":{"bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.","ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","ieee":"J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276.","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276."},"page":"265-276","language":[{"iso":"eng"}],"_id":"2352","date_updated":"2023-09-26T13:52:01Z"},{"date_updated":"2023-09-26T13:52:32Z","_id":"2238","doi":"10.1109/ReConFig.2009.32","page":"119-124","type":"conference","year":"2009","citation":{"ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124.","bibtex":"@inproceedings{Schumacher_Süß_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000}, DOI={10.1109/ReConFig.2009.32}, booktitle={Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32."},"language":[{"iso":"eng"}],"place":"Los Alamitos, CA, USA","title":"Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)","keyword":["IMORC","graphics"],"quality_controlled":"1","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"publisher":"IEEE Computer Society","publication_identifier":{"isbn":["978-0-7695-3917-1"]},"date_created":"2018-04-05T17:11:28Z","status":"public"},{"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","user_id":"15278","publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"date_created":"2018-04-06T15:15:47Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["IMORC","NOC","KNN","accelerator"],"author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","quality_controlled":"1","_id":"2261","date_updated":"2023-09-26T13:52:52Z","page":"338-344","citation":{"mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–344."},"year":"2009","type":"conference","language":[{"iso":"eng"}]},{"publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","author":[{"first_name":"Mariusz","full_name":"Grad, Mariusz","last_name":"Grad"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"}],"publisher":"CSREA Press","publication_identifier":{"isbn":["1-60132-101-5"]},"date_created":"2018-04-06T15:19:51Z","status":"public","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}],"place":"USA","title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","page":"319-322","year":"2009","citation":{"chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322."},"type":"conference","language":[{"iso":"eng"}],"_id":"2263","date_updated":"2023-09-26T13:53:30Z"},{"user_id":"15274","title":"Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures","author":[{"full_name":"Battré, Dominic","first_name":"Dominic","last_name":"Battré"},{"full_name":"Hovestadt, Matthias","first_name":"Matthias","last_name":"Hovestadt"},{"last_name":"Kao","full_name":"Kao, Odej","first_name":"Odej"},{"id":"15274","last_name":"Keller","full_name":"Keller, Axel","first_name":"Axel"},{"last_name":"Voss","full_name":"Voss, Kerstin","first_name":"Kerstin"}],"publication":"Proc. Int. Conf. on Risks and Security of Internet and Systems","department":[{"_id":"27"}],"status":"public","date_created":"2018-03-29T11:23:57Z","publication_status":"published","date_updated":"2022-01-06T06:54:11Z","_id":"1974","language":[{"iso":"eng"}],"type":"conference","year":"2008","citation":{"ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures,” in Proc. Int. Conf. on Risks and Security of Internet and Systems, 2008.","short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Risks and Security of Internet and Systems, 2008.","mla":"Battré, Dominic, et al. “Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures.” Proc. Int. Conf. on Risks and Security of Internet and Systems, 2008.","bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, title={Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures}, booktitle={Proc. Int. Conf. on Risks and Security of Internet and Systems}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008} }","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures. In: Proc. Int. Conf. on Risks and Security of Internet and Systems. ; 2008.","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures. In Proc. Int. Conf. on Risks and Security of Internet and Systems.","chicago":"Battré, Dominic, Matthias Hovestadt, Odej Kao, Axel Keller, and Kerstin Voss. “Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures.” In Proc. Int. Conf. on Risks and Security of Internet and Systems, 2008."}},{"publication":"Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies","department":[{"_id":"27"}],"author":[{"last_name":"Battré","first_name":"Dominic","full_name":"Battré, Dominic"},{"first_name":"Matthias","full_name":"Hovestadt, Matthias","last_name":"Hovestadt"},{"last_name":"Kao","full_name":"Kao, Odej","first_name":"Odej"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"last_name":"Voss","first_name":"Kerstin","full_name":"Voss, Kerstin"}],"publication_status":"published","date_created":"2018-03-29T11:24:29Z","status":"public","abstract":[{"lang":"eng","text":"Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects."}],"title":"Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems","user_id":"15274","citation":{"chicago":"Battré, Dominic, Matthias Hovestadt, Odej Kao, Axel Keller, and Kerstin Voss. “Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems.” In Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies, 2008. https://doi.org/10.1007/978-3-540-88708-9_1.","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems. In: Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies. ; 2008. doi:10.1007/978-3-540-88708-9_1","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems. In Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies. https://doi.org/10.1007/978-3-540-88708-9_1","mla":"Battré, Dominic, et al. “Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems.” Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies, 2008, doi:10.1007/978-3-540-88708-9_1.","bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, title={Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems}, DOI={10.1007/978-3-540-88708-9_1}, booktitle={Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008} }","short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies, 2008.","ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems,” in Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies, 2008."},"type":"conference","year":"2008","language":[{"iso":"eng"}],"_id":"1975","date_updated":"2022-01-06T06:54:12Z","doi":"10.1007/978-3-540-88708-9_1"},{"_id":"1976","date_updated":"2022-01-06T06:54:12Z","doi":"10.1109/ICPP-W.2008.40","language":[{"iso":"eng"}],"year":"2008","citation":{"short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, Portland, Oregon USA, 2008.","ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids,” in Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, 2008.","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids. In Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Portland, Oregon USA. https://doi.org/10.1109/ICPP-W.2008.40","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids. In: Proc. Int. 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However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system.","lang":"eng"}],"place":"Portland, Oregon USA","user_id":"15274","title":"Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids","department":[{"_id":"27"}],"publication":"Proc. Int. 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It will also outline an implementation within OpenCCS.","lang":"eng"}],"user_id":"15274","title":"Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids","author":[{"full_name":"Battré, Dominic","first_name":"Dominic","last_name":"Battré"},{"full_name":"Hovestadt, Matthias","first_name":"Matthias","last_name":"Hovestadt"},{"last_name":"Kao","first_name":"Odej","full_name":"Kao, Odej"},{"last_name":"Keller","id":"15274","first_name":"Axel","full_name":"Keller, Axel"},{"full_name":"Voss, Kerstin","first_name":"Kerstin","last_name":"Voss"}],"publication":"Proc. Int. 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