[{"page":"223-226","type":"conference","year":"2011","citation":{"bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }","mla":"Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273.","apa":"Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273","ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226."},"language":[{"iso":"eng"}],"doi":"10.1109/ASAP.2011.6043273","date_updated":"2023-09-26T13:43:48Z","_id":"2193","date_created":"2018-04-03T14:37:14Z","project":[{"name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A","_id":"30"}],"status":"public","publication":"Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"},{"id":"3118","last_name":"Wiersema","full_name":"Wiersema, Tobias","first_name":"Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"}],"title":"Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler","user_id":"15278"},{"date_updated":"2023-09-26T13:46:08Z","doi":"10.1109/ReConFig.2011.59","language":[{"iso":"eng"}],"title":"Measuring and Predicting Temperature Distributions on FPGAs at Run-Time","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"656","type":"conference","year":"2011","citation":{"ieee":"M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.","short":"M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.","bibtex":"@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }","mla":"Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59.","chicago":"Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59.","apa":"Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59","ama":"Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59"},"page":"55-60","abstract":[{"text":"In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time.","lang":"eng"}],"ddc":["040"],"user_id":"15278","publisher":"IEEE","author":[{"full_name":"Happe, Markus","first_name":"Markus","last_name":"Happe"},{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)","file_date_updated":"2018-03-14T13:49:39Z","file":[{"file_name":"656-2011_happe_reconfig.pdf","date_created":"2018-03-14T13:49:39Z","access_level":"closed","file_size":502244,"creator":"florida","file_id":"1220","date_updated":"2018-03-14T13:49:39Z","content_type":"application/pdf","relation":"main_file","success":1}],"status":"public","has_accepted_license":"1","date_created":"2017-10-17T12:42:59Z"},{"year":"2011","type":"conference","citation":{"short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.","apa":"Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448."},"page":"177-180","language":[{"iso":"eng"}],"date_updated":"2023-09-26T13:45:04Z","_id":"2200","doi":"10.1145/1950413.1950448","publisher":"ACM","quality_controlled":"1","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","last_name":"Kenter","id":"3145"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"full_name":"Kauschke, Michael","first_name":"Michael","last_name":"Kauschke"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"publication_identifier":{"isbn":["978-1-4503-0554-9"]},"status":"public","date_created":"2018-04-03T15:08:13Z","place":"New York, NY, USA","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","user_id":"15278"},{"user_id":"15278","title":"Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture","date_created":"2018-04-03T15:05:52Z","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proc. Reconfigurable Architectures Workshop (RAW)","author":[{"last_name":"Grad","full_name":"Grad, Mariusz","first_name":"Mariusz"},{"orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publisher":"IEEE Computer Society","doi":"10.1109/IPDPS.2011.153","_id":"2198","date_updated":"2023-09-26T13:44:39Z","language":[{"iso":"eng"}],"page":"278-285","type":"conference","year":"2011","citation":{"ieee":"M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.","short":"M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.","mla":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153.","bibtex":"@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }","chicago":"Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153.","ama":"Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153","apa":"Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153"}},{"publication":"Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)","department":[{"_id":"27"}],"author":[{"last_name":"Bienkowski","full_name":"Bienkowski, Marcin","first_name":"Marcin"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"},{"last_name":"Klonowski","first_name":"Marek","full_name":"Klonowski, Marek"},{"full_name":"Korzeniowski, Miroslaw","first_name":"Miroslaw","last_name":"Korzeniowski"}],"publisher":"Springer","date_created":"2018-04-05T14:49:51Z","status":"public","volume":6490,"place":"Berlin / Heidelberg","user_id":"24135","title":"SkewCCC+: A Heterogeneous Distributed Hash Table","series_title":"Lecture Notes in Computer Science (LNCS)","citation":{"bibtex":"@inproceedings{Bienkowski_Brinkmann_Klonowski_Korzeniowski_2010, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={SkewCCC+: A Heterogeneous Distributed Hash Table}, volume={6490}, DOI={10.1007/978-3-642-17653-1_18}, booktitle={Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis)}, publisher={Springer}, author={Bienkowski, Marcin and Brinkmann, André and Klonowski, Marek and Korzeniowski, Miroslaw}, year={2010}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Bienkowski, Marcin, et al. “SkewCCC+: A Heterogeneous Distributed Hash Table.” Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), vol. 6490, Springer, 2010, doi:10.1007/978-3-642-17653-1_18.","ama":"Bienkowski M, Brinkmann A, Klonowski M, Korzeniowski M. SkewCCC+: A Heterogeneous Distributed Hash Table. In: Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis). Vol 6490. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2010. doi:10.1007/978-3-642-17653-1_18","apa":"Bienkowski, M., Brinkmann, A., Klonowski, M., & Korzeniowski, M. (2010). SkewCCC+: A Heterogeneous Distributed Hash Table. In Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) (Vol. 6490). Berlin / Heidelberg: Springer. https://doi.org/10.1007/978-3-642-17653-1_18","chicago":"Bienkowski, Marcin, André Brinkmann, Marek Klonowski, and Miroslaw Korzeniowski. “SkewCCC+: A Heterogeneous Distributed Hash Table.” In Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), Vol. 6490. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2010. https://doi.org/10.1007/978-3-642-17653-1_18.","ieee":"M. Bienkowski, A. Brinkmann, M. Klonowski, and M. Korzeniowski, “SkewCCC+: A Heterogeneous Distributed Hash Table,” in Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), 2010, vol. 6490.","short":"M. Bienkowski, A. Brinkmann, M. Klonowski, M. Korzeniowski, in: Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis), Springer, Berlin / Heidelberg, 2010."},"type":"conference","year":"2010","intvolume":" 6490","_id":"2217","date_updated":"2022-01-06T06:55:28Z","doi":"10.1007/978-3-642-17653-1_18"},{"publisher":"Consorzio COMETA","author":[{"last_name":"Wewior","full_name":"Wewior, Martin","first_name":"Martin"},{"last_name":"Packschies","full_name":"Packschies, Lars","first_name":"Lars"},{"first_name":"Dirk","full_name":"Blunk, Dirk","last_name":"Blunk"},{"last_name":"Wickeroth","first_name":"Daniel","full_name":"Wickeroth, Daniel"},{"last_name":"Warzecha","full_name":"Warzecha, Klaus-Dieter","first_name":"Klaus-Dieter"},{"first_name":"Sonja","full_name":"Herres-Pawlis, Sonja","last_name":"Herres-Pawlis"},{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"full_name":"Breuers, Sebastian","first_name":"Sebastian","last_name":"Breuers"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"last_name":"Lang","full_name":"Lang, Ulrich","first_name":"Ulrich"}],"publication":"Proc. Int. Workshop on Scientific Gateways (IWSG)","department":[{"_id":"27"}],"status":"public","date_created":"2018-04-05T14:53:40Z","title":"The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations","user_id":"24135","year":"2010","type":"conference","citation":{"apa":"Wewior, M., Packschies, L., Blunk, D., Wickeroth, D., Warzecha, K.-D., Herres-Pawlis, S., … Lang, U. (2010). The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 39–43). Consorzio COMETA.","ama":"Wewior M, Packschies L, Blunk D, et al. The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2010:39-43.","chicago":"Wewior, Martin, Lars Packschies, Dirk Blunk, Daniel Wickeroth, Klaus-Dieter Warzecha, Sonja Herres-Pawlis, Sandra Gesing, et al. “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations.” In Proc. Int. Workshop on Scientific Gateways (IWSG), 39–43. Consorzio COMETA, 2010.","bibtex":"@inproceedings{Wewior_Packschies_Blunk_Wickeroth_Warzecha_Herres-Pawlis_Gesing_Breuers_Krüger_Birkenheuer_et al._2010, title={The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Wewior, Martin and Packschies, Lars and Blunk, Dirk and Wickeroth, Daniel and Warzecha, Klaus-Dieter and Herres-Pawlis, Sonja and Gesing, Sandra and Breuers, Sebastian and Krüger, Jens and Birkenheuer, Georg and et al.}, year={2010}, pages={39–43} }","mla":"Wewior, Martin, et al. “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43.","short":"M. Wewior, L. Packschies, D. Blunk, D. Wickeroth, K.-D. Warzecha, S. Herres-Pawlis, S. Gesing, S. Breuers, J. Krüger, G. Birkenheuer, U. Lang, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 39–43.","ieee":"M. Wewior et al., “The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 39–43."},"page":"39-43","date_updated":"2022-01-06T06:55:28Z","_id":"2218"},{"user_id":"24135","title":"Workflow Interoperability in a Grid Portal for Molecular Simulations","date_created":"2018-04-05T14:55:48Z","status":"public","publication":"Proc. Int. Workshop on Scientific Gateways (IWSG)","department":[{"_id":"27"}],"publisher":"Consorzio COMETA","author":[{"full_name":"Gesing, Sandra","first_name":"Sandra","last_name":"Gesing"},{"first_name":"Istvan","full_name":"Marton, Istvan","last_name":"Marton"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"first_name":"Bernd","full_name":"Schuller, Bernd","last_name":"Schuller"},{"last_name":"Grunzke","first_name":"Richard","full_name":"Grunzke, Richard"},{"first_name":"Jens","full_name":"Krüger, Jens","last_name":"Krüger"},{"first_name":"Sebastian","full_name":"Breuers, Sebastian","last_name":"Breuers"},{"full_name":"Blunk, Dirk","first_name":"Dirk","last_name":"Blunk"},{"last_name":"Fels","full_name":"Fels, Gregor","first_name":"Gregor"},{"last_name":"Packschies","full_name":"Packschies, Lars","first_name":"Lars"},{"last_name":"Brinkmann","first_name":"André","full_name":"Brinkmann, André"},{"full_name":"Kohlbacher, Oliver","first_name":"Oliver","last_name":"Kohlbacher"},{"full_name":"Kozlovszky, Miklos","first_name":"Miklos","last_name":"Kozlovszky"}],"_id":"2219","date_updated":"2022-01-06T06:55:28Z","page":"44-48","type":"conference","citation":{"ieee":"S. Gesing et al., “Workflow Interoperability in a Grid Portal for Molecular Simulations,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2010, pp. 44–48.","short":"S. Gesing, I. Marton, G. Birkenheuer, B. Schuller, R. Grunzke, J. Krüger, S. Breuers, D. Blunk, G. Fels, L. Packschies, A. Brinkmann, O. Kohlbacher, M. Kozlovszky, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","bibtex":"@inproceedings{Gesing_Marton_Birkenheuer_Schuller_Grunzke_Krüger_Breuers_Blunk_Fels_Packschies_et al._2010, title={Workflow Interoperability in a Grid Portal for Molecular Simulations}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Marton, Istvan and Birkenheuer, Georg and Schuller, Bernd and Grunzke, Richard and Krüger, Jens and Breuers, Sebastian and Blunk, Dirk and Fels, Gregor and Packschies, Lars and et al.}, year={2010}, pages={44–48} }","mla":"Gesing, Sandra, et al. “Workflow Interoperability in a Grid Portal for Molecular Simulations.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2010, pp. 44–48.","apa":"Gesing, S., Marton, I., Birkenheuer, G., Schuller, B., Grunzke, R., Krüger, J., … Kozlovszky, M. (2010). Workflow Interoperability in a Grid Portal for Molecular Simulations. In Proc. Int. Workshop on Scientific Gateways (IWSG) (pp. 44–48). Consorzio COMETA.","ama":"Gesing S, Marton I, Birkenheuer G, et al. Workflow Interoperability in a Grid Portal for Molecular Simulations. In: Proc. Int. Workshop on Scientific Gateways (IWSG). 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Cracow Grid Workshop (CGW)}, author={Niehörster, Oliver and Birkenheuer, Georg and Brinkmann, André and Blunk, Dirk and Elsässer, Brigitta and Herres-Pawlis, Sonja and Krüger, Jens and Niehörster, Julia and Packschies, Lars and Fels, Gregor}, year={2009}, pages={55–63} }","apa":"Niehörster, O., Birkenheuer, G., Brinkmann, A., Blunk, D., Elsässer, B., Herres-Pawlis, S., … Fels, G. (2009). Providing Scientific Software as a Service in Consideration of Service Level Agreements. In Proc. Cracow Grid Workshop (CGW) (pp. 55–63).","ama":"Niehörster O, Birkenheuer G, Brinkmann A, et al. Providing Scientific Software as a Service in Consideration of Service Level Agreements. In: Proc. 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Cracow Grid Workshop (CGW)","author":[{"first_name":"Oliver","full_name":"Niehörster, Oliver","last_name":"Niehörster"},{"first_name":"Georg","full_name":"Birkenheuer, Georg","last_name":"Birkenheuer"},{"full_name":"Brinkmann, André","first_name":"André","last_name":"Brinkmann"},{"last_name":"Blunk","first_name":"Dirk","full_name":"Blunk, Dirk"},{"first_name":"Brigitta","full_name":"Elsässer, Brigitta","last_name":"Elsässer"},{"last_name":"Herres-Pawlis","first_name":"Sonja","full_name":"Herres-Pawlis, Sonja"},{"last_name":"Krüger","first_name":"Jens","full_name":"Krüger, Jens"},{"last_name":"Niehörster","full_name":"Niehörster, Julia","first_name":"Julia"},{"full_name":"Packschies, Lars","first_name":"Lars","last_name":"Packschies"},{"last_name":"Fels","first_name":"Gregor","full_name":"Fels, Gregor"}],"publication_identifier":{"isbn":["978-83-61433-01-9"]},"date_created":"2018-04-05T17:14:52Z","status":"public","title":"Providing Scientific Software as a Service in Consideration of Service Level Agreements","user_id":"24135"},{"date_created":"2018-04-06T15:14:46Z","status":"public","publication_identifier":{"isbn":["978-83-61433-01-9"]},"publication":"Proc. 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Cracow Grid Workshop (CGW), 96–103, 2009.","apa":"Birkenheuer, G., Carlson, A., Fölling, A., Högqvist, M., Hoheisel, A., Papaspyrou, A., … Ziegler, W. (2009). Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In Proc. Cracow Grid Workshop (CGW) (pp. 96–103).","ama":"Birkenheuer G, Carlson A, Fölling A, et al. Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! In: Proc. Cracow Grid Workshop (CGW). ; 2009:96-103.","bibtex":"@inproceedings{Birkenheuer_Carlson_Fölling_Högqvist_Hoheisel_Papaspyrou_Rieger_Schott_Ziegler_2009, title={Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!}, booktitle={Proc. Cracow Grid Workshop (CGW)}, author={Birkenheuer, Georg and Carlson, Arthur and Fölling, Alexander and Högqvist, Mikael and Hoheisel, Andreas and Papaspyrou, Alexander and Rieger, Klaus and Schott, Bernhard and Ziegler, Wolfgang}, year={2009}, pages={96–103} }","mla":"Birkenheuer, Georg, et al. “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!” Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","short":"G. Birkenheuer, A. Carlson, A. Fölling, M. Högqvist, A. Hoheisel, A. Papaspyrou, K. Rieger, B. Schott, W. Ziegler, in: Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103.","ieee":"G. Birkenheuer et al., “Connecting Communities on the Meta-Scheduling Level: The DGSI Approach!,” in Proc. Cracow Grid Workshop (CGW), 2009, pp. 96–103."},"date_updated":"2022-01-06T06:55:37Z","_id":"2260"},{"page":"8:1-8:12","citation":{"bibtex":"@inproceedings{Meister_Brinkmann_2009, place={New York}, title={Multi-Level Comparison of Data Deduplication in a Backup Scenario}, DOI={10.1145/1534530.1534541}, booktitle={Proc. of the Israeli Experimental Systems Conference (SYSTOR)}, publisher={ACM}, author={Meister, Dirk and Brinkmann, André}, year={2009}, pages={8:1-8:12} }","mla":"Meister, Dirk, and André Brinkmann. “Multi-Level Comparison of Data Deduplication in a Backup Scenario.” Proc. of the Israeli Experimental Systems Conference (SYSTOR), ACM, 2009, pp. 8:1-8:12, doi:10.1145/1534530.1534541.","apa":"Meister, D., & Brinkmann, A. (2009). Multi-Level Comparison of Data Deduplication in a Backup Scenario. In Proc. of the Israeli Experimental Systems Conference (SYSTOR) (pp. 8:1-8:12). New York: ACM. https://doi.org/10.1145/1534530.1534541","ama":"Meister D, Brinkmann A. Multi-Level Comparison of Data Deduplication in a Backup Scenario. In: Proc. of the Israeli Experimental Systems Conference (SYSTOR). New York: ACM; 2009:8:1-8:12. doi:10.1145/1534530.1534541","chicago":"Meister, Dirk, and André Brinkmann. “Multi-Level Comparison of Data Deduplication in a Backup Scenario.” In Proc. of the Israeli Experimental Systems Conference (SYSTOR), 8:1-8:12. New York: ACM, 2009. https://doi.org/10.1145/1534530.1534541.","ieee":"D. Meister and A. Brinkmann, “Multi-Level Comparison of Data Deduplication in a Backup Scenario,” in Proc. of the Israeli Experimental Systems Conference (SYSTOR), 2009, pp. 8:1-8:12.","short":"D. Meister, A. Brinkmann, in: Proc. of the Israeli Experimental Systems Conference (SYSTOR), ACM, New York, 2009, pp. 8:1-8:12."},"type":"conference","year":"2009","_id":"2264","date_updated":"2022-01-06T06:55:37Z","doi":"10.1145/1534530.1534541","department":[{"_id":"27"}],"publication":"Proc. of the Israeli Experimental Systems Conference (SYSTOR)","author":[{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"},{"last_name":"Brinkmann","full_name":"Brinkmann, André","first_name":"André"}],"publisher":"ACM","date_created":"2018-04-06T15:21:25Z","status":"public","place":"New York","user_id":"24135","title":"Multi-Level Comparison of Data Deduplication in a Backup Scenario"},{"doi":"10.1007/978-3-642-04633-9_5","date_updated":"2022-01-06T07:03:51Z","_id":"818","page":"80-100","year":"2009","citation":{"bibtex":"@inproceedings{Birkenheuer_Brinkmann_Karl_2009, title={The Gain of Overbooking}, DOI={10.1007/978-3-642-04633-9_5}, booktitle={Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers}, author={Birkenheuer, Georg and Brinkmann, Andre and Karl, Holger}, year={2009}, pages={80–100} }","mla":"Birkenheuer, Georg, et al. “The Gain of Overbooking.” Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers, 2009, pp. 80–100, doi:10.1007/978-3-642-04633-9_5.","apa":"Birkenheuer, G., Brinkmann, A., & Karl, H. (2009). The Gain of Overbooking. In Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers (pp. 80–100). https://doi.org/10.1007/978-3-642-04633-9_5","ama":"Birkenheuer G, Brinkmann A, Karl H. The Gain of Overbooking. In: Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. 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Revised Papers, 2009, pp. 80–100."},"type":"conference","title":"The Gain of Overbooking","user_id":"24135","date_created":"2017-11-27T10:22:26Z","status":"public","department":[{"_id":"75"},{"_id":"27"}],"publication":"Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers","author":[{"full_name":"Birkenheuer, Georg","first_name":"Georg","last_name":"Birkenheuer"},{"full_name":"Brinkmann, Andre","first_name":"Andre","last_name":"Brinkmann"},{"first_name":"Holger","full_name":"Karl, Holger","last_name":"Karl","id":"126"}]},{"_id":"2350","page":"275-278","year":"2009","citation":{"short":"T. Schumacher, C. Plessl, M. Platzner, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–278.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing,” in Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2009, pp. 275–278, doi: 10.1109/FCCM.2009.25.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–78. IEEE Computer Society, 2009. https://doi.org/10.1109/FCCM.2009.25.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE Computer Society; 2009:275-278. doi:10.1109/FCCM.2009.25","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 275–278. https://doi.org/10.1109/FCCM.2009.25","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing}, DOI={10.1109/FCCM.2009.25}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={275–278} }","mla":"Schumacher, Tobias, et al. “IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE Computer Society, 2009, pp. 275–78, doi:10.1109/FCCM.2009.25."},"type":"conference","abstract":[{"text":"Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. ","lang":"eng"}],"user_id":"15278","keyword":["IMORC","interconnect","performance"],"publication":"Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)","author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"quality_controlled":"1","publisher":"IEEE Computer Society","date_created":"2018-04-16T15:05:52Z","status":"public","date_updated":"2023-09-26T13:51:44Z","doi":"10.1109/FCCM.2009.25","language":[{"iso":"eng"}],"title":"IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"isbn":["978-1-4244-4450-2"]}},{"status":"public","date_created":"2018-04-06T15:18:24Z","quality_controlled":"1","publisher":"IEEE Computer Society","author":[{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"last_name":"Plessl","id":"16153","first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["EvoCache","evolvable hardware","computer architecture"],"user_id":"15278","title":"EvoCaches: Application-specific Adaptation of Cache Mapping","place":"Los Alamitos, CA, USA","abstract":[{"lang":"eng","text":"In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. "}],"language":[{"iso":"eng"}],"type":"conference","year":"2009","citation":{"apa":"Kaufmann, P., Plessl, C., & Platzner, M. (2009). EvoCaches: Application-specific Adaptation of Cache Mapping. Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18.","ama":"Kaufmann P, Plessl C, Platzner M. EvoCaches: Application-specific Adaptation of Cache Mapping. In: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS). IEEE Computer Society; 2009:11-18.","chicago":"Kaufmann, Paul, Christian Plessl, and Marco Platzner. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” In Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 11–18. Los Alamitos, CA, USA: IEEE Computer Society, 2009.","mla":"Kaufmann, Paul, et al. “EvoCaches: Application-Specific Adaptation of Cache Mapping.” Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, 2009, pp. 11–18.","bibtex":"@inproceedings{Kaufmann_Plessl_Platzner_2009, place={Los Alamitos, CA, USA}, title={EvoCaches: Application-specific Adaptation of Cache Mapping}, booktitle={Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS)}, publisher={IEEE Computer Society}, author={Kaufmann, Paul and Plessl, Christian and Platzner, Marco}, year={2009}, pages={11–18} }","short":"P. Kaufmann, C. Plessl, M. Platzner, in: Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 11–18.","ieee":"P. Kaufmann, C. Plessl, and M. Platzner, “EvoCaches: Application-specific Adaptation of Cache Mapping,” in Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2009, pp. 11–18."},"page":"11-18","_id":"2262","date_updated":"2023-09-26T13:53:11Z"},{"date_updated":"2023-09-26T13:52:01Z","_id":"2352","language":[{"iso":"eng"}],"page":"265-276","citation":{"ama":"Beutel J, Gruber S, Hasler A, et al. PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. In: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN). IEEE Computer Society; 2009:265-276.","apa":"Beutel, J., Gruber, S., Hasler, A., Lim, R., Meier, A., Plessl, C., Talzi, I., Thiele, L., Tschudin, C., Woehrle, M., & Yuecel, M. (2009). PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes. Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–276.","chicago":"Beutel, Jan, Stephan Gruber, Andi Hasler, Roman Lim, Andreas Meier, Christian Plessl, Igor Talzi, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” In Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 265–76. Washington, DC, USA: IEEE Computer Society, 2009.","mla":"Beutel, Jan, et al. “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes.” Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, 2009, pp. 265–76.","bibtex":"@inproceedings{Beutel_Gruber_Hasler_Lim_Meier_Plessl_Talzi_Thiele_Tschudin_Woehrle_et al._2009, place={Washington, DC, USA}, title={PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes}, booktitle={Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN)}, publisher={IEEE Computer Society}, author={Beutel, Jan and Gruber, Stephan and Hasler, Andi and Lim, Roman and Meier, Andreas and Plessl, Christian and Talzi, Igor and Thiele, Lothar and Tschudin, Christian and Woehrle, Matthias and et al.}, year={2009}, pages={265–276} }","short":"J. Beutel, S. Gruber, A. Hasler, R. Lim, A. Meier, C. Plessl, I. Talzi, L. Thiele, C. Tschudin, M. Woehrle, M. Yuecel, in: Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), IEEE Computer Society, Washington, DC, USA, 2009, pp. 265–276.","ieee":"J. Beutel et al., “PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes,” in Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN), 2009, pp. 265–276."},"year":"2009","type":"conference","place":"Washington, DC, USA","extern":"1","user_id":"15278","title":"PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes","department":[{"_id":"27"},{"_id":"518"}],"publication":"Proc. Int. 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Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE Computer Society}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2009}, pages={119–124} }","mla":"Schumacher, Tobias, et al. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, 2009, pp. 119–24, doi:10.1109/ReConFig.2009.32.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. In: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig). IEEE Computer Society; 2009:119-124. doi:10.1109/ReConFig.2009.32","apa":"Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2009). Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000. Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–124. https://doi.org/10.1109/ReConFig.2009.32","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000.” In Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 119–24. Los Alamitos, CA, USA: IEEE Computer Society, 2009. https://doi.org/10.1109/ReConFig.2009.32.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000,” in Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), 2009, pp. 119–124, doi: 10.1109/ReConFig.2009.32.","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, in: Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig), IEEE Computer Society, Los Alamitos, CA, USA, 2009, pp. 119–124."},"type":"conference","year":"2009","_id":"2238","date_updated":"2023-09-26T13:52:32Z","doi":"10.1109/ReConFig.2009.32","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["IMORC","graphics"],"publication":"Proc. Int. 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Plessl, and M. Platzner, “An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2009, pp. 338–344.","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–44. IEEE, 2009.","apa":"Schumacher, T., Plessl, C., & Platzner, M. (2009). An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 338–344.","ama":"Schumacher T, Plessl C, Platzner M. An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2009:338-344.","mla":"Schumacher, Tobias, et al. “An Accelerator for K-Th Nearest Neighbor Thinning Based on the IMORC Infrastructure.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2009, pp. 338–44.","bibtex":"@inproceedings{Schumacher_Plessl_Platzner_2009, title={An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2009}, pages={338–344} }"},"year":"2009","type":"conference","page":"338-344","language":[{"iso":"eng"}],"title":"An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure","user_id":"15278","author":[{"full_name":"Schumacher, Tobias","first_name":"Tobias","last_name":"Schumacher"},{"first_name":"Christian","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"quality_controlled":"1","publisher":"IEEE","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","keyword":["IMORC","NOC","KNN","accelerator"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication_identifier":{"issn":["1946-1488"],"isbn":["978-1-4244-3892-1"]},"status":"public","date_created":"2018-04-06T15:15:47Z"},{"citation":{"short":"M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, USA, 2009, pp. 319–322.","ieee":"M. Grad and C. Plessl, “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2009, pp. 319–322.","chicago":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–22. USA: CSREA Press, 2009.","apa":"Grad, M., & Plessl, C. (2009). Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 319–322.","ama":"Grad M, Plessl C. Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2009:319-322.","bibtex":"@inproceedings{Grad_Plessl_2009, place={USA}, title={Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2009}, pages={319–322} }","mla":"Grad, Mariusz, and Christian Plessl. “Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2009, pp. 319–22."},"year":"2009","type":"conference","page":"319-322","language":[{"iso":"eng"}],"_id":"2263","date_updated":"2023-09-26T13:53:30Z","publication_identifier":{"isbn":["1-60132-101-5"]},"status":"public","date_created":"2018-04-06T15:19:51Z","publisher":"CSREA Press","author":[{"last_name":"Grad","first_name":"Mariusz","full_name":"Grad, Mariusz"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153","last_name":"Plessl"}],"quality_controlled":"1","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX","user_id":"15278","place":"USA","abstract":[{"lang":"eng","text":"In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. "}]},{"user_id":"15274","title":"Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures","status":"public","date_created":"2018-03-29T11:23:57Z","publication_status":"published","author":[{"first_name":"Dominic","full_name":"Battré, Dominic","last_name":"Battré"},{"first_name":"Matthias","full_name":"Hovestadt, Matthias","last_name":"Hovestadt"},{"first_name":"Odej","full_name":"Kao, Odej","last_name":"Kao"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"full_name":"Voss, Kerstin","first_name":"Kerstin","last_name":"Voss"}],"publication":"Proc. Int. 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DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies","status":"public","date_created":"2018-03-29T11:24:29Z","publication_status":"published","abstract":[{"text":"Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects.","lang":"eng"}],"user_id":"15274","title":"Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems"},{"language":[{"iso":"eng"}],"type":"conference","citation":{"ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids,” in Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, 2008.","short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, Portland, Oregon USA, 2008.","bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, place={Portland, Oregon USA}, title={Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids}, DOI={10.1109/ICPP-W.2008.40}, booktitle={Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008} }","mla":"Battré, Dominic, et al. “Implementation of Virtual Execution Environments for Improving SLA-Compliant Job Migration in Grids.” Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems, 2008, doi:10.1109/ICPP-W.2008.40.","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids. In Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems. Portland, Oregon USA. https://doi.org/10.1109/ICPP-W.2008.40","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids. In: Proc. Int. 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It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system.","lang":"eng"}],"place":"Portland, Oregon USA","user_id":"15274","title":"Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids"},{"title":"Germany, Belgium, France, and Back Again: Job Migration using Globus","user_id":"15274","department":[{"_id":"27"}],"publication":"Proc. Int. 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Conf. on Grid Computing and Applications (GCA), 2008.","chicago":"Battré, Dominic, Matthias Hovestadt, Odej Kao, Axel Keller, and Kerstin Voss. “Germany, Belgium, France, and Back Again: Job Migration Using Globus.” In Proc. Int. Conf. on Grid Computing and Applications (GCA), 2008.","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Germany, Belgium, France, and Back Again: Job Migration using Globus. In: Proc. Int. Conf. on Grid Computing and Applications (GCA). ; 2008.","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Germany, Belgium, France, and Back Again: Job Migration using Globus. In Proc. Int. Conf. on Grid Computing and Applications (GCA).","mla":"Battré, Dominic, et al. “Germany, Belgium, France, and Back Again: Job Migration Using Globus.” Proc. Int. Conf. on Grid Computing and Applications (GCA), 2008.","bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, title={Germany, Belgium, France, and Back Again: Job Migration using Globus}, booktitle={Proc. Int. Conf. on Grid Computing and Applications (GCA)}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008} }"},"language":[{"iso":"eng"}]},{"year":"2008","type":"conference","citation":{"mla":"Battré, Dominic, et al. “Virtual Execution Environments for Ensuring SLA-Compliant Job Migration in Grids.” Proc. Int. Conf. on Services Computing (SCC), 2008, doi:10.1109/SCC.2008.106.","bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, title={Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids}, DOI={10.1109/SCC.2008.106}, booktitle={Proc. Int. Conf. on Services Computing (SCC)}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008} }","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids. In Proc. Int. Conf. on Services Computing (SCC). https://doi.org/10.1109/SCC.2008.106","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids. In: Proc. Int. Conf. on Services Computing (SCC). ; 2008. doi:10.1109/SCC.2008.106","chicago":"Battré, Dominic, Matthias Hovestadt, Odej Kao, Axel Keller, and Kerstin Voss. “Virtual Execution Environments for Ensuring SLA-Compliant Job Migration in Grids.” In Proc. Int. Conf. on Services Computing (SCC), 2008. https://doi.org/10.1109/SCC.2008.106.","ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids,” in Proc. Int. Conf. on Services Computing (SCC), 2008.","short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. Conf. on Services Computing (SCC), 2008."},"language":[{"iso":"eng"}],"doi":"10.1109/SCC.2008.106","date_updated":"2022-01-06T06:54:13Z","_id":"1980","publication_status":"published","status":"public","date_created":"2018-03-29T11:28:27Z","author":[{"full_name":"Battré, Dominic","first_name":"Dominic","last_name":"Battré"},{"last_name":"Hovestadt","first_name":"Matthias","full_name":"Hovestadt, Matthias"},{"last_name":"Kao","full_name":"Kao, Odej","first_name":"Odej"},{"last_name":"Keller","id":"15274","first_name":"Axel","full_name":"Keller, Axel"},{"last_name":"Voss","full_name":"Voss, Kerstin","first_name":"Kerstin"}],"publication":"Proc. Int. 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It will also outline an implementation within OpenCCS.","lang":"eng"}]},{"author":[{"first_name":"Dominic","full_name":"Battré, Dominic","last_name":"Battré"},{"first_name":"Matthias","full_name":"Hovestadt, Matthias","last_name":"Hovestadt"},{"last_name":"Kao","full_name":"Kao, Odej","first_name":"Odej"},{"full_name":"Keller, Axel","first_name":"Axel","id":"15274","last_name":"Keller"},{"last_name":"Voss","full_name":"Voss, Kerstin","first_name":"Kerstin"}],"department":[{"_id":"27"}],"publication":"Proc. Int. Conf. on Grid and Pervasive Computing (GPC)","status":"public","date_created":"2018-03-29T11:28:58Z","publication_identifier":{"isbn":["978-0-7695-3177-9"]},"publication_status":"published","abstract":[{"lang":"eng","text":"Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution."}],"user_id":"15274","title":"Job Migration and Fault Tolerance in SLA-aware Resource Management Systems","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Battré_Hovestadt_Kao_Keller_Voss_2008, title={Job Migration and Fault Tolerance in SLA-aware Resource Management Systems}, DOI={10.1109/GPC.WORKSHOPS.2008.71}, booktitle={Proc. Int. Conf. on Grid and Pervasive Computing (GPC)}, author={Battré, Dominic and Hovestadt, Matthias and Kao, Odej and Keller, Axel and Voss, Kerstin}, year={2008}, pages={43–48} }","mla":"Battré, Dominic, et al. “Job Migration and Fault Tolerance in SLA-Aware Resource Management Systems.” Proc. Int. Conf. on Grid and Pervasive Computing (GPC), 2008, pp. 43–48, doi:10.1109/GPC.WORKSHOPS.2008.71.","apa":"Battré, D., Hovestadt, M., Kao, O., Keller, A., & Voss, K. (2008). Job Migration and Fault Tolerance in SLA-aware Resource Management Systems. In Proc. Int. Conf. on Grid and Pervasive Computing (GPC) (pp. 43–48). https://doi.org/10.1109/GPC.WORKSHOPS.2008.71","ama":"Battré D, Hovestadt M, Kao O, Keller A, Voss K. Job Migration and Fault Tolerance in SLA-aware Resource Management Systems. In: Proc. Int. Conf. on Grid and Pervasive Computing (GPC). ; 2008:43-48. doi:10.1109/GPC.WORKSHOPS.2008.71","chicago":"Battré, Dominic, Matthias Hovestadt, Odej Kao, Axel Keller, and Kerstin Voss. “Job Migration and Fault Tolerance in SLA-Aware Resource Management Systems.” In Proc. Int. Conf. on Grid and Pervasive Computing (GPC), 43–48, 2008. https://doi.org/10.1109/GPC.WORKSHOPS.2008.71.","ieee":"D. Battré, M. Hovestadt, O. Kao, A. Keller, and K. Voss, “Job Migration and Fault Tolerance in SLA-aware Resource Management Systems,” in Proc. Int. Conf. on Grid and Pervasive Computing (GPC), 2008, pp. 43–48.","short":"D. Battré, M. Hovestadt, O. Kao, A. Keller, K. Voss, in: Proc. Int. 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Platzner et al., “The GOmputer: Accelerating GO with FPGAs,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2008, pp. 245–251.","short":"M. Platzner, S. Döhre, M. Happe, T. Kenter, U. Lorenz, T. Schumacher, A. Send, A. Warkentin, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–251.","bibtex":"@inproceedings{Platzner_Döhre_Happe_Kenter_Lorenz_Schumacher_Send_Warkentin_2008, title={The GOmputer: Accelerating GO with FPGAs}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Platzner, Marco and Döhre, Sven and Happe, Markus and Kenter, Tobias and Lorenz, Ulf and Schumacher, Tobias and Send, Andre and Warkentin, Alexander}, year={2008}, pages={245–251} }","mla":"Platzner, Marco, et al. “The GOmputer: Accelerating GO with FPGAs.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2008, pp. 245–51.","apa":"Platzner, M., Döhre, S., Happe, M., Kenter, T., Lorenz, U., Schumacher, T., … Warkentin, A. (2008). The GOmputer: Accelerating GO with FPGAs. In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) (pp. 245–251). CSREA Press.","ama":"Platzner M, Döhre S, Happe M, et al. The GOmputer: Accelerating GO with FPGAs. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2008:245-251.","chicago":"Platzner, Marco, Sven Döhre, Markus Happe, Tobias Kenter, Ulf Lorenz, Tobias Schumacher, Andre Send, and Alexander Warkentin. “The GOmputer: Accelerating GO with FPGAs.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 245–51. CSREA Press, 2008."},"year":"2008","type":"conference","_id":"2365","date_updated":"2022-01-06T06:55:58Z"}]