TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AB - Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments. AU - Kleineweber, Christoph AU - Keller, Axel AU - Niehörster, Oliver AU - Brinkmann, André ID - 1968 T2 - Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) TI - Rule Based Mapping of Virtual Machines in Clouds ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Miranda, Alberto AU - Effert, Sascha AU - Kang, Yangwook AU - Miller, Ethan AU - Brinkmann, André AU - Cortes, Toni ID - 2188 T2 - Proc. Int. Conf. on High Performance Computing (HIPC) TI - Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems ER - TY - CONF AU - Grawinkel, Matthias AU - Pargmann, Markus AU - Dömer, Hubert AU - Brinkmann, André ID - 2189 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System ER -