TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Brinkmann, André AU - Effert, Sascha ID - 1789 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - Design of an exact data deduplication cluster ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Schlemmer, Tobias AU - Grunzke, Richard AU - Gesing, Sandra AU - Krüger, Jens AU - Birkenheuer, Georg AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2104 T2 - Proc. EGI Technical Forum TI - Generic User Management for Science Gateways via Virtual Organizations ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AU - Congiu, Giuseppe AU - Grawinkel, Matthias AU - Narasimhamurthy, Sai AU - Brinkmann, André ID - 2105 T2 - Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) TI - One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2171 T2 - Proc. EGI Community Forum TI - The MoSGrid Community From National to International Scale ER - TY - CONF AU - Grawinkel, Matthias AU - Süß, Tim AU - Best, Georg AU - Popov, Ivan AU - Brinkmann, André ID - 2101 T2 - Proc. Parallel Data Storage Workshop (PDSW) TI - Towards Dynamic Scripted pNFS Layouts ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AU - Gesing, Sandra AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Warzecha, Klaus-Dieter AU - Wewior, Martin AU - Kohlbacher, Oliver ID - 2199 T2 - Proc. EGI User Forum TI - A Science Gateway for Molecular Simulations ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André ID - 2190 T2 - Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) TI - Autonomic Resource Management Handling Delayed Configuration Effects ER - TY - CONF AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Krieger, Alexaner ID - 2203 SN - 978-0-7695-4572-1 T2 - Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) TI - Autonomic Resource Management with Support Vector Machines ER -