TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Brinkmann, André AU - Effert, Sascha ID - 1789 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - Design of an exact data deduplication cluster ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Schlemmer, Tobias AU - Grunzke, Richard AU - Gesing, Sandra AU - Krüger, Jens AU - Birkenheuer, Georg AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2104 T2 - Proc. EGI Technical Forum TI - Generic User Management for Science Gateways via Virtual Organizations ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AU - Congiu, Giuseppe AU - Grawinkel, Matthias AU - Narasimhamurthy, Sai AU - Brinkmann, André ID - 2105 T2 - Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) TI - One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2171 T2 - Proc. EGI Community Forum TI - The MoSGrid Community From National to International Scale ER - TY - CONF AU - Grawinkel, Matthias AU - Süß, Tim AU - Best, Georg AU - Popov, Ivan AU - Brinkmann, André ID - 2101 T2 - Proc. Parallel Data Storage Workshop (PDSW) TI - Towards Dynamic Scripted pNFS Layouts ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AU - Gesing, Sandra AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Warzecha, Klaus-Dieter AU - Wewior, Martin AU - Kohlbacher, Oliver ID - 2199 T2 - Proc. EGI User Forum TI - A Science Gateway for Molecular Simulations ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André ID - 2190 T2 - Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) TI - Autonomic Resource Management Handling Delayed Configuration Effects ER - TY - CONF AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Krieger, Alexaner ID - 2203 SN - 978-0-7695-4572-1 T2 - Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) TI - Autonomic Resource Management with Support Vector Machines ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CONF AU - Grawinkel, Matthias AU - Schäfer, Thorsten AU - Brinkmann, André AU - Hagemeyer, Jens AU - Porrmann, Mario ID - 2195 T2 - Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability ER - TY - CONF AU - Gesing, Sandra AU - Grunzke, Richard AU - Balaskó, Ákos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Herres-Pawlis, Sonja AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Packschies, Lars AU - Schäfer, Patrick AU - Schuller, Bernd AU - Schuster, Johannes AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Wewior, Martin AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2197 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Granular Security for a Science Gateway in Structural Bioinformatics ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Grawinkel, Matthias AU - Pargmann, Markus AU - Dömer, Hubert AU - Brinkmann, André ID - 2189 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Gesing, Sandra AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Lang, Ulrich AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuster, Johannes AU - Steinke, Thomas AU - Warzecha, Klaus-Dieter AU - Wewior, Martin ID - 2205 T2 - Proc. of Grid Workflow Workshop (GWW) TI - MoSGrid: Progress of Workflow driven Chemical Simulations VL - 829 ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Miranda, Alberto AU - Effert, Sascha AU - Kang, Yangwook AU - Miller, Ethan AU - Brinkmann, André AU - Cortes, Toni ID - 2188 T2 - Proc. Int. Conf. on High Performance Computing (HIPC) TI - Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems ER - TY - CONF AU - Brinkmann, André AU - Gao, Yan AU - Korzeniowski, Miroslaw AU - Meister, Dirk ID - 2196 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Request Load Balancing for Highly Skewed Traffic in P2P Networks ER - TY - CONF AB - Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments. AU - Kleineweber, Christoph AU - Keller, Axel AU - Niehörster, Oliver AU - Brinkmann, André ID - 1968 T2 - Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) TI - Rule Based Mapping of Virtual Machines in Clouds ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2229 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Balls into Bins with Related Random Choices ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2232 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - Balls into Non-uniform Bins ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2230 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD) ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André AU - Fels, Gregor AU - Krüger, Jens AU - Simon, Jens ID - 2237 SN - 1552-5244 T2 - Proc. Int. Conf. on Cluster Computing (CLUSTER) TI - Enforcing SLAs in Scientific Clouds ER - TY - CONF AU - Birkenheuer, Georg AU - Breuers, Sebastian AU - Brinkmann, André AU - Blunk, Dirk AU - Fels, Gregor AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Packschies, Lars ID - 2236 T2 - Proc. of Grid Workflow Workshop (GWW) TI - Grid-Workflows in Molecular Science ER - TY - CONF AU - Lensing, Paul Hermann AU - Meister, Dirk AU - Brinkmann, André ID - 2231 T2 - Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI) TI - hashFS: Applying Hashing to Optimized File Systems for Small File Reads ER - TY - CONF AU - Bolte, Matthias AU - Sievers, Michael AU - Birkenheuer, Georg AU - Niehörster, Oliver AU - Brinkmann, André ID - 2234 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Non-intrusive Virtualization Management Using libvirt ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Gao, Yan AU - Meister, Dirk AU - Brinkmann, André ID - 2225 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 809 T2 - Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers TI - Risk Aware Overbooking for Commercial Grids ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2227 SN - 978-1-4244-7911-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Klonowski, Marek AU - Korzeniowski, Miroslaw ID - 2217 T2 - Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) TI - SkewCCC+: A Heterogeneous Distributed Hash Table VL - 6490 ER -