TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Klonowski, Marek AU - Korzeniowski, Miroslaw ID - 2217 T2 - Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) TI - SkewCCC+: A Heterogeneous Distributed Hash Table VL - 6490 ER - TY - CONF AU - Wewior, Martin AU - Packschies, Lars AU - Blunk, Dirk AU - Wickeroth, Daniel AU - Warzecha, Klaus-Dieter AU - Herres-Pawlis, Sonja AU - Gesing, Sandra AU - Breuers, Sebastian AU - Krüger, Jens AU - Birkenheuer, Georg AU - Lang, Ulrich ID - 2218 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations ER - TY - CONF AU - Gesing, Sandra AU - Marton, Istvan AU - Birkenheuer, Georg AU - Schuller, Bernd AU - Grunzke, Richard AU - Krüger, Jens AU - Breuers, Sebastian AU - Blunk, Dirk AU - Fels, Gregor AU - Packschies, Lars AU - Brinkmann, André AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos ID - 2219 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Workflow Interoperability in a Grid Portal for Molecular Simulations ER - TY - CONF AU - Gao, Yan AU - Meister, Dirk AU - Brinkmann, André ID - 2225 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2229 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Balls into Bins with Related Random Choices ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2230 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD) ER - TY - CONF AU - Lensing, Paul Hermann AU - Meister, Dirk AU - Brinkmann, André ID - 2231 T2 - Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI) TI - hashFS: Applying Hashing to Optimized File Systems for Small File Reads ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2232 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - Balls into Non-uniform Bins ER - TY - CONF AU - Bolte, Matthias AU - Sievers, Michael AU - Birkenheuer, Georg AU - Niehörster, Oliver AU - Brinkmann, André ID - 2234 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Non-intrusive Virtualization Management Using libvirt ER - TY - CONF AU - Birkenheuer, Georg AU - Breuers, Sebastian AU - Brinkmann, André AU - Blunk, Dirk AU - Fels, Gregor AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Packschies, Lars ID - 2236 T2 - Proc. of Grid Workflow Workshop (GWW) TI - Grid-Workflows in Molecular Science ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André AU - Fels, Gregor AU - Krüger, Jens AU - Simon, Jens ID - 2237 SN - 1552-5244 T2 - Proc. Int. Conf. on Cluster Computing (CLUSTER) TI - Enforcing SLAs in Scientific Clouds ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 809 T2 - Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers TI - Risk Aware Overbooking for Commercial Grids ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2227 SN - 978-1-4244-7911-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Höing, Andre AU - Scherp, Guido AU - Gudenkauf, Stefan AU - Meister, Dirk AU - Brinkmann, André ID - 2239 T2 - Proc. Int. Conf. on Service Oriented Computing (ICSOC) TI - An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL VL - 5900 ER - TY - CONF AU - Niehörster, Oliver AU - Birkenheuer, Georg AU - Brinkmann, André AU - Blunk, Dirk AU - Elsässer, Brigitta AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Niehörster, Julia AU - Packschies, Lars AU - Fels, Gregor ID - 2240 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Providing Scientific Software as a Service in Consideration of Service Level Agreements ER - TY - CONF AU - Birkenheuer, Georg AU - Carlson, Arthur AU - Fölling, Alexander AU - Högqvist, Mikael AU - Hoheisel, Andreas AU - Papaspyrou, Alexander AU - Rieger, Klaus AU - Schott, Bernhard AU - Ziegler, Wolfgang ID - 2260 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2264 T2 - Proc. of the Israeli Experimental Systems Conference (SYSTOR) TI - Multi-Level Comparison of Data Deduplication in a Backup Scenario ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 818 T2 - Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers TI - The Gain of Overbooking ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Beutel, Jan AU - Gruber, Stephan AU - Hasler, Andi AU - Lim, Roman AU - Meier, Andreas AU - Plessl, Christian AU - Talzi, Igor AU - Thiele, Lothar AU - Tschudin, Christian AU - Woehrle, Matthias AU - Yuecel, Mustafa ID - 2352 KW - WSN KW - PermaSense SN - 978-1-4244-5108-1 T2 - Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN) TI - PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1974 T2 - Proc. Int. Conf. on Risks and Security of Internet and Systems TI - Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures ER - TY - CONF AB - Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1975 T2 - Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies TI - Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems ER - TY - CONF AB - Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1976 T2 - Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems TI - Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1978 T2 - Proc. Int. Conf. on Grid Computing and Applications (GCA) TI - Germany, Belgium, France, and Back Again: Job Migration using Globus ER - TY - CONF AB - OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1980 T2 - Proc. Int. Conf. on Services Computing (SCC) TI - Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids ER - TY - CONF AB - Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1981 SN - 978-0-7695-3177-9 T2 - Proc. Int. Conf. on Grid and Pervasive Computing (GPC) TI - Job Migration and Fault Tolerance in SLA-aware Resource Management Systems ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ED - Gonzalez, T. F. ID - 1983 SN - 978-0-88986-773-4 T2 - Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS) TI - Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2355 T2 - Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS) TI - Redundant Data Placement Strategies for Cluster Storage Environments ER - TY - CONF AU - Brinkmann, André AU - Gudenkauf, Stefan AU - Hasselbring, Wilhelm AU - Höing, André AU - Karl, Holger AU - Kao, Odej AU - Nitsche, Holger AU - Scherp, Guido ID - 2356 T2 - Proc. Cracow Grid Workshop (CGW) TI - Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, André AU - Dömer, Hubert AU - Effert, Sascha AU - Konersmann, Christoph AU - Niehörster, Oliver AU - Simon, Jens ID - 2357 T2 - Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management TI - Virtual Supercomputer for HPC and HTC ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Battré, Dominic AU - Birkenheuer, Georg AU - Deora, Vikas AU - Hovestadt, Matthias AU - Rana, Omer AU - Wäldrich, Oliver ID - 2359 T2 - Proc. Cracow Grid Workshop (CGW) TI - Guarantee and Penalty Clauses for Service Level Agreements ER - TY - CONF AU - Richert, Willi AU - Niehörster, Oliver AU - Koch, Markus ID - 2360 T2 - Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS) TI - Layered understanding for sporadic imitation in a multi-robot scenario ER - TY - CONF AU - Lietsch, Stefan AU - Zabel, Henning AU - Laroque, Christoph ID - 2363 T2 - Proc. ASME Computers and Information in Engineering Conference (CIE) TI - Computational Steering Of Interactive Material Flow Simulations ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER -