TY - CONF AU - Opdenhövel, Jan-Oliver AU - Plessl, Christian AU - Kenter, Tobias ID - 46190 T2 - Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation ER - TY - CONF AU - Faj, Jennifer AU - Kenter, Tobias AU - Faghih-Naini, Sara AU - Plessl, Christian AU - Aizinger, Vadym ID - 46188 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes ER - TY - CONF AU - Prouveur, Charles AU - Haefele, Matthieu AU - Kenter, Tobias AU - Voss, Nils ID - 46189 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - FPGA Acceleration for HPC Supercapacitor Simulations ER - TY - CONF AB - The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be computed for every time step. In this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence relations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our best knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far. Our evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \times 10^9$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x. AU - Wu, Xin AU - Kenter, Tobias AU - Schade, Robert AU - Kühne, Thomas AU - Plessl, Christian ID - 43228 T2 - 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) TI - Computing and Compressing Electron Repulsion Integrals on FPGAs ER - TY - GEN AB - Viscous hydrodynamics serves as a successful mesoscopic description of the Quark-Gluon Plasma produced in relativistic heavy-ion collisions. In order to investigate, how such an effective description emerges from the underlying microscopic dynamics we calculate the hydrodynamic and non-hydrodynamic modes of linear response in the sound channel from a first-principle calculation in kinetic theory. We do this with a new approach wherein we discretize the collision kernel to directly calculate eigenvalues and eigenmodes of the evolution operator. This allows us to study the Green's functions at any point in the complex frequency space. Our study focuses on scalar theory with quartic interaction and we find that the analytic structure of Green's functions in the complex plane is far more complicated than just poles or cuts which is a first step towards an equivalent study in QCD kinetic theory. AU - Ochsenfeld, Stephan AU - Schlichting, Sören ID - 50172 T2 - arXiv:2308.04491 TI - Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A Numerical Analysis in Scalar Field Theory ER - TY - GEN AB - Memory Gym presents a suite of 2D partially observable environments, namely Mortar Mayhem, Mystery Path, and Searing Spotlights, designed to benchmark memory capabilities in decision-making agents. These environments, originally with finite tasks, are expanded into innovative, endless formats, mirroring the escalating challenges of cumulative memory games such as ``I packed my bag''. This progression in task design shifts the focus from merely assessing sample efficiency to also probing the levels of memory effectiveness in dynamic, prolonged scenarios. To address the gap in available memory-based Deep Reinforcement Learning baselines, we introduce an implementation that integrates Transformer-XL (TrXL) with Proximal Policy Optimization. This approach utilizes TrXL as a form of episodic memory, employing a sliding window technique. Our comparative study between the Gated Recurrent Unit (GRU) and TrXL reveals varied performances across different settings. TrXL, on the finite environments, demonstrates superior sample efficiency in Mystery Path and outperforms in Mortar Mayhem. However, GRU is more efficient on Searing Spotlights. Most notably, in all endless tasks, GRU makes a remarkable resurgence, consistently outperforming TrXL by significant margins. Website and Source Code: https://github.com/MarcoMeter/endless-memory-gym/ AU - Pleines, Marco AU - Pallasch, Matthias AU - Zimmer, Frank AU - Preuss, Mike ID - 50221 T2 - arXiv:2309.17207 TI - Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of Agents ER - TY - GEN AB - This preprint makes the claim of having computed the $9^{th}$ Dedekind Number. This was done by building an efficient FPGA Accelerator for the core operation of the process, and parallelizing it on the Noctua 2 Supercluster at Paderborn University. The resulting value is 286386577668298411128469151667598498812366. This value can be verified in two steps. We have made the data file containing the 490M results available, each of which can be verified separately on CPU, and the whole file sums to our proposed value. AU - Van Hirtum, Lennart AU - De Causmaecker, Patrick AU - Goemaere, Jens AU - Kenter, Tobias AU - Riebler, Heinrich AU - Lass, Michael AU - Plessl, Christian ID - 43439 T2 - arXiv:2304.03039 TI - A computation of D(9) using FPGA Supercomputing ER - TY - GEN AB - We investigate the early time development of the anisotropic transverse flow and spatial eccentricities of a fireball with various particle-based transport approaches using a fixed initial condition. In numerical simulations ranging from the quasi-collisionless case to the hydrodynamic regime, we find that the onset of $v_n$ and of related measures of anisotropic flow can be described with a simple power-law ansatz, with an exponent that depends on the amount of rescatterings in the system. In the few-rescatterings regime we perform semi-analytical calculations, based on a systematic expansion in powers of time and the cross section, which can reproduce the numerical findings. AU - Borghini, Nicolas AU - Borrell, Marc AU - Roch, Hendrik ID - 32177 T2 - arXiv:2201.13294 TI - Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers ER - TY - GEN AB - We test the ability of the "escape mechanism" to create the anisotropic flow observed in high-energy nuclear collisions. We compare the flow harmonics $v_n$ in the few-rescatterings regime from two types of transport simulations, with $2\to 2$ and $2\to 0$ collision kernels respectively, and from analytical calculations neglecting the gain term of the Boltzmann equation. We find that the even flow harmonics are similar in the three approaches, while the odd harmonics differ significantly. AU - Bachmann, Benedikt AU - Borghini, Nicolas AU - Feld, Nina AU - Roch, Hendrik ID - 32178 T2 - arXiv:2203.13306 TI - Even anisotropic-flow harmonics are from Venus, odd ones are from Mars ER - TY - GEN AB - The Julia programming language has evolved into a modern alternative to fill existing gaps in scientific computing and data science applications. Julia leverages a unified and coordinated single-language and ecosystem paradigm and has a proven track record of achieving high performance without sacrificing user productivity. These aspects make Julia a viable alternative to high-performance computing's (HPC's) existing and increasingly costly many-body workflow composition strategy in which traditional HPC languages (e.g., Fortran, C, C++) are used for simulations, and higher-level languages (e.g., Python, R, MATLAB) are used for data analysis and interactive computing. Julia's rapid growth in language capabilities, package ecosystem, and community make it a promising universal language for HPC. This paper presents the views of a multidisciplinary group of researchers from academia, government, and industry that advocate for an HPC software development paradigm that emphasizes developer productivity, workflow portability, and low barriers for entry. We believe that the Julia programming language, its ecosystem, and its community provide modern and powerful capabilities that enable this group's objectives. Crucially, we believe that Julia can provide a feasible and less costly approach to programming scientific applications and workflows that target HPC facilities. In this work, we examine the current practice and role of Julia as a common, end-to-end programming model to address major challenges in scientific reproducibility, data-driven AI/machine learning, co-design and workflows, scalability and performance portability in heterogeneous computing, network communication, data management, and community education. As a result, the diversification of current investments to fulfill the needs of the upcoming decade is crucial as more supercomputing centers prepare for the exascale era. AU - Churavy, Valentin AU - Godoy, William F AU - Bauer, Carsten AU - Ranocha, Hendrik AU - Schlottke-Lakemper, Michael AU - Räss, Ludovic AU - Blaschke, Johannes AU - Giordano, Mosè AU - Schnetter, Erik AU - Omlin, Samuel AU - Vetter, Jeffrey S AU - Edelman, Alan ID - 36879 TI - Bridging HPC Communities through the Julia Programming Language ER - TY - GEN AB - Electronic structure calculations have been instrumental in providing many important insights into a range of physical and chemical properties of various molecular and solid-state systems. Their importance to various fields, including materials science, chemical sciences, computational chemistry and device physics, is underscored by the large fraction of available public supercomputing resources devoted to these calculations. As we enter the exascale era, exciting new opportunities to increase simulation numbers, sizes, and accuracies present themselves. In order to realize these promises, the community of electronic structure software developers will however first have to tackle a number of challenges pertaining to the efficient use of new architectures that will rely heavily on massive parallelism and hardware accelerators. This roadmap provides a broad overview of the state-of-the-art in electronic structure calculations and of the various new directions being pursued by the community. It covers 14 electronic structure codes, presenting their current status, their development priorities over the next five years, and their plans towards tackling the challenges and leveraging the opportunities presented by the advent of exascale computing. AU - Gavini, Vikram AU - Baroni, Stefano AU - Blum, Volker AU - Bowler, David R. AU - Buccheri, Alexander AU - Chelikowsky, James R. AU - Das, Sambit AU - Dawson, William AU - Delugas, Pietro AU - Dogan, Mehmet AU - Draxl, Claudia AU - Galli, Giulia AU - Genovese, Luigi AU - Giannozzi, Paolo AU - Giantomassi, Matteo AU - Gonze, Xavier AU - Govoni, Marco AU - Gulans, Andris AU - Gygi, François AU - Herbert, John M. AU - Kokott, Sebastian AU - Kühne, Thomas AU - Liou, Kai-Hsin AU - Miyazaki, Tsuyoshi AU - Motamarri, Phani AU - Nakata, Ayako AU - Pask, John E. AU - Plessl, Christian AU - Ratcliff, Laura E. AU - Richard, Ryan M. AU - Rossi, Mariana AU - Schade, Robert AU - Scheffler, Matthias AU - Schütt, Ole AU - Suryanarayana, Phanish AU - Torrent, Marc AU - Truflandier, Lionel AU - Windus, Theresa L. AU - Xu, Qimen AU - Yu, Victor W. -Z. AU - Perez, Danny ID - 33493 T2 - arXiv:2209.12747 TI - Roadmap on Electronic Structure Codes in the Exascale Era ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Kenter, Tobias AU - Jansson, Niclas AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 46193 T2 - International Conference on High Performance Computing in Asia-Pacific Region TI - A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges ER - TY - GEN AB - The CP2K program package, which can be considered as the swiss army knife of atomistic simulations, is presented with a special emphasis on ab-initio molecular dynamics using the second-generation Car-Parrinello method. After outlining current and near-term development efforts with regards to massively parallel low-scaling post-Hartree-Fock and eigenvalue solvers, novel approaches on how we plan to take full advantage of future low-precision hardware architectures are introduced. Our focus here is on combining our submatrix method with the approximate computing paradigm to address the immanent exascale era. AU - Kühne, Thomas AU - Plessl, Christian AU - Schade, Robert AU - Schütt, Ole ID - 32404 T2 - arXiv:2205.14741 TI - CP2K on the road to exascale ER - TY - GEN AB - Electronic structure calculations have been instrumental in providing many important insights into a range of physical and chemical properties of various molecular and solid-state systems. Their importance to various fields, including materials science, chemical sciences, computational chemistry and device physics, is underscored by the large fraction of available public supercomputing resources devoted to these calculations. As we enter the exascale era, exciting new opportunities to increase simulation numbers, sizes, and accuracies present themselves. In order to realize these promises, the community of electronic structure software developers will however first have to tackle a number of challenges pertaining to the efficient use of new architectures that will rely heavily on massive parallelism and hardware accelerators. This roadmap provides a broad overview of the state-of-the-art in electronic structure calculations and of the various new directions being pursued by the community. It covers 14 electronic structure codes, presenting their current status, their development priorities over the next five years, and their plans towards tackling the challenges and leveraging the opportunities presented by the advent of exascale computing. AU - Gavini, Vikram AU - Baroni, Stefano AU - Blum, Volker AU - Bowler, David R. AU - Buccheri, Alexander AU - Chelikowsky, James R. AU - Das, Sambit AU - Dawson, William AU - Delugas, Pietro AU - Dogan, Mehmet AU - Draxl, Claudia AU - Galli, Giulia AU - Genovese, Luigi AU - Giannozzi, Paolo AU - Giantomassi, Matteo AU - Gonze, Xavier AU - Govoni, Marco AU - Gulans, Andris AU - Gygi, François AU - Herbert, John M. AU - Kokott, Sebastian AU - Kühne, Thomas AU - Liou, Kai-Hsin AU - Miyazaki, Tsuyoshi AU - Motamarri, Phani AU - Nakata, Ayako AU - Pask, John E. AU - Plessl, Christian AU - Ratcliff, Laura E. AU - Richard, Ryan M. AU - Rossi, Mariana AU - Schade, Robert AU - Scheffler, Matthias AU - Schütt, Ole AU - Suryanarayana, Phanish AU - Torrent, Marc AU - Truflandier, Lionel AU - Windus, Theresa L. AU - Xu, Qimen AU - Yu, Victor W. -Z. AU - Perez, Danny ID - 46275 T2 - arXiv:2209.12747 TI - Roadmap on Electronic Structure Codes in the Exascale Era ER - TY - CONF AU - Meyer, Marius ID - 27365 T2 - Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks ER - TY - CONF AU - Nickchen, Tobias AU - Heindorf, Stefan AU - Engels, Gregor ID - 20886 T2 - Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision TI - Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts ER - TY - GEN AB - We push the boundaries of electronic structure-based \textit{ab-initio} molecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise barely reachable with classical force-field methods or novel neural network and machine learning potentials. We achieve this breakthrough by combining innovations in linear-scaling AIMD, efficient and approximate sparse linear algebra, low and mixed-precision floating-point computation on GPUs, and a compensation scheme for the errors introduced by numerical approximations. The core of our work is the non-orthogonalized local submatrix method (NOLSM), which scales very favorably to massively parallel computing systems and translates large sparse matrix operations into highly parallel, dense matrix operations that are ideally suited to hardware accelerators. We demonstrate that the NOLSM method, which is at the center point of each AIMD step, is able to achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision corresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs. AU - Schade, Robert AU - Kenter, Tobias AU - Elgabarty, Hossam AU - Lass, Michael AU - Schütt, Ole AU - Lazzaro, Alfio AU - Pabst, Hans AU - Mohr, Stephan AU - Hutter, Jürg AU - Kühne, Thomas D. AU - Plessl, Christian ID - 32244 T2 - arXiv:2104.08245 TI - Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms ER - TY - GEN AB - Optical travelling wave antennas offer unique opportunities to control and selectively guide light into a specific direction which renders them as excellent candidates for optical communication and sensing. These applications require state of the art engineering to reach optimized functionalities such as high directivity and radiation efficiency, low side lobe level, broadband and tunable capabilities, and compact design. In this work we report on the numerical optimization of the directivity of optical travelling wave antennas made from low-loss dielectric materials using full-wave numerical simulations in conjunction with a particle swarm optimization algorithm. The antennas are composed of a reflector and a director deposited on a glass substrate and an emitter placed in the feed gap between them serves as an internal source of excitation. In particular, we analysed antennas with rectangular- and horn-shaped directors made of either Hafnium dioxide or Silicon. The optimized antennas produce highly directional emission due to the presence of two dominant guided TE modes in the director in addition to leaky modes. These guided modes dominate the far-field emission pattern and govern the direction of the main lobe emission which predominately originates from the end facet of the director. Our work also provides a comprehensive analysis of the modes, radiation patterns, parametric influences, and bandwidths of the antennas that highlights their robust nature. AU - Farheen, Henna AU - Leuteritz, Till AU - Linden, Stefan AU - Myroshnychenko, Viktor AU - Förstner, Jens ID - 32245 T2 - arXiv:2106.02468 TI - Optimization of optical waveguide antennas for directive emission of light ER - TY - GEN AB - The interaction between quantum light and matter is being intensively studied for systems that are enclosed in high-$Q$ cavities which strongly enhance the light-matter coupling. However, for many applications, cavities with lower $Q$-factors are preferred due to the increased spectral width of the cavity mode. Here, we investigate the interaction between quantum light and matter represented by a $\Lambda$-type three-level system in lossy cavities, assuming that cavity losses are the dominant loss mechanism. We demonstrate that cavity losses lead to non-trivial steady states of the electronic occupations that can be controlled by the loss rate and the initial statistics of the quantum fields. The mechanism of formation of such steady states can be understood on the basis of the equations of motion. Analytical expressions for steady states and their numerical simulations are presented and discussed. AU - Rose, H. AU - Tikhonova, O. V. AU - Meier, T. AU - Sharapova, P. ID - 32236 T2 - arXiv:2109.00842 TI - Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities ER - TY - CONF AU - Kenter, Tobias AU - Shambhu, Adesh AU - Faghih-Naini, Sara AU - Aizinger, Vadym ID - 46194 T2 - Proceedings of the Platform for Advanced Scientific Computing Conference TI - Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Jansson, Niclas AU - Kenter, Tobias AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 46195 T2 - 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) TI - High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection ER - TY - CONF AU - Karp, Martin AU - Podobas, Artur AU - Jansson, Niclas AU - Kenter, Tobias AU - Plessl, Christian AU - Schlatter, Philipp AU - Markidis, Stefano ID - 29937 T2 - 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) TI - High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection ER - TY - GEN AB - We consider a resource-aware variant of the classical multi-armed bandit problem: In each round, the learner selects an arm and determines a resource limit. It then observes a corresponding (random) reward, provided the (random) amount of consumed resources remains below the limit. Otherwise, the observation is censored, i.e., no reward is obtained. For this problem setting, we introduce a measure of regret, which incorporates the actual amount of allocated resources of each learning round as well as the optimality of realizable rewards. Thus, to minimize regret, the learner needs to set a resource limit and choose an arm in such a way that the chance to realize a high reward within the predefined resource limit is high, while the resource limit itself should be kept as low as possible. We derive the theoretical lower bound on the cumulative regret and propose a learning algorithm having a regret upper bound that matches the lower bound. In a simulation study, we show that our learning algorithm outperforms straightforward extensions of standard multi-armed bandit algorithms. AU - Bengs, Viktor AU - Hüllermeier, Eyke ID - 32242 T2 - arXiv:2011.00813 TI - Multi-Armed Bandits with Censored Consumption of Resources ER - TY - CONF AB - Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on complex large-scale systems, so-called linear scaling methods instead of conventional cubic scaling methods are required. In this work, we take up the idea of the submatrix method and apply it to the DFT computations in the software package CP2K. For that purpose, we transform the underlying numeric operations on distributed, large, sparse matrices into computations on local, much smaller and nearly dense matrices. This allows us to exploit the full floating-point performance of modern CPUs and to make use of dedicated accelerator hardware, where performance has been limited by memory bandwidth before. We demonstrate both functionality and performance of our implementation and show how it can be accelerated with GPUs and FPGAs. AU - Lass, Michael AU - Schade, Robert AU - Kühne, Thomas AU - Plessl, Christian ID - 16898 T2 - Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC) TI - A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K ER - TY - CONF AB - FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. AU - Meyer, Marius AU - Kenter, Tobias AU - Plessl, Christian ID - 21632 KW - FPGA KW - OpenCL KW - High Level Synthesis KW - HPC benchmarking SN - 9781665415927 T2 - 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) TI - Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite ER - TY - CONF AB - Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS. AU - Gorlani, Paolo AU - Kenter, Tobias AU - Plessl, Christian ID - 15478 T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs ER - TY - CONF AB - This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation. AU - Keller, Axel ED - Klusáček, D. ED - Cirne, W. ED - Desai, N. ID - 22 KW - Scheduling Planning Mapping Workload management SN - 978-3-319-77398-8 T2 - Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) TI - A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems VL - 10773 ER - TY - CONF AB - The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x. AU - Kenter, Tobias AU - Mahale, Gopinath AU - Alhaddad, Samer AU - Grynko, Yevgen AU - Schmitt, Christian AU - Afzal, Ayesha AU - Hannig, Frank AU - Förstner, Jens AU - Plessl, Christian ID - 1588 KW - tet_topic_hpc T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes ER - TY - CONF AB - We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures. We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution. AU - Lass, Michael AU - Mohr, Stephan AU - Wiebeler, Hendrik AU - Kühne, Thomas AU - Plessl, Christian ID - 1590 KW - approximate computing KW - linear algebra KW - matrix inversion KW - matrix p-th roots KW - numeric algorithm KW - parallel computing SN - 978-1-4503-5891-0/18/07 T2 - Proc. Platform for Advanced Scientific Computing (PASC) Conference TI - A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices ER - TY - CONF AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Kenter, Tobias AU - Plessl, Christian ID - 1204 KW - htrop SN - 9781450349826 T2 - Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) TI - Automated Code Acceleration Targeting Heterogeneous OpenCL Devices ER - TY - CONF AB - Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures. AU - Kenter, Tobias AU - Förstner, Jens AU - Plessl, Christian ID - 1592 KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Flexible FPGA design for FDTD using OpenCL ER - TY - CONF AU - Dellnitz, Michael AU - Eckstein, Julian AU - Flaßkamp, Kathrin AU - Friedel, Patrick AU - Horenkamp, Christian AU - Köhler, Ulrich AU - Ober-Blöbaum, Sina AU - Peitz, Sebastian AU - Tiemeyer, Sebastian ID - 34 SN - 2212-0173 T2 - Progress in Industrial Mathematics at ECMI TI - Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control VL - 22 ER - TY - CONF AB - Version Control Systems (VCS) are a valuable tool for software development and document management. Both client/server and distributed (Peer-to-Peer) models exist, with the latter (e.g., Git and Mercurial) becoming increasingly popular. Their distributed nature introduces complications, especially concerning security: it is hard to control the dissemination of contents stored in distributed VCS as they rely on replication of complete repositories to any involved user. We overcome this issue by designing and implementing a concept for cryptography-enforced access control which is transparent to the user. Use of field-tested schemes (end-to-end encryption, digital signatures) allows for strong security, while adoption of convergent encryption and content-defined chunking retains storage efficiency. The concept is seamlessly integrated into Mercurial---respecting its distributed storage concept---to ensure practical usability and compatibility to existing deployments. AU - Lass, Michael AU - Leibenger, Dominik AU - Sorge, Christoph ID - 19 KW - access control KW - distributed version control systems KW - mercurial KW - peer-to-peer KW - convergent encryption KW - confidentiality KW - authenticity SN - 978-1-5090-2054-6 T2 - Proc. 41st Conference on Local Computer Networks (LCN) TI - Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension ER - TY - CONF AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian AU - Trainiti, Ettore M. G. AU - Durelli, Gianluca C. AU - Bolchini, Cristiana ID - 31 T2 - Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) TI - Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian ID - 24 T2 - Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) TI - Microdisk Cavity FDTD Simulation on FPGA using OpenCL ER - TY - CONF AU - Lass, Michael AU - Kühne, Thomas AU - Plessl, Christian ID - 25 T2 - Workshop on Approximate Computing (AC) TI - Using Approximate Computing in Scientific Codes ER - TY - CONF AB - Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian AU - Trainiti, Ettore M. G. AU - Durelli, Gianluca C. AU - Del Sozzo, Emanuele AU - Santambrogio, Marco D. AU - Bolchini, Christina ID - 138 T2 - Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) TI - Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems ER - TY - CONF AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. AU - Lösch, Achim AU - Beisel, Tobias AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 168 T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center ER - TY - CONF AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Plessl, Christian ID - 171 T2 - Workshop on Reconfigurable Computing (WRC) TI - Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) ER - TY - CONF AB - This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. AU - Damschen, Marvin AU - Plessl, Christian ID - 303 T2 - Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) TI - Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores ER - TY - CONF AU - Schumacher, Jörn AU - T. Anderson, J. AU - Borga, A. AU - Boterenbrood, H. AU - Chen, H. AU - Chen, K. AU - Drake, G. AU - Francis, D. AU - Gorini, B. AU - Lanni, F. AU - Lehmann-Miotto, Giovanna AU - Levinson, L. AU - Narevicius, J. AU - Plessl, Christian AU - Roich, A. AU - Ryu, S. AU - P. Schreuder, F. AU - Vandelli, Wainer AU - Vermeulen, J. AU - Zhang, J. ID - 1773 T2 - Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) TI - Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm ER - TY - CONF AB - In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. AU - Damschen, Marvin AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 238 T2 - Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) TI - Transparent offloading of computational hotspots from binary code to Xeon Phi ER - TY - CONF AB - In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment. AU - Steinle, Tobias AU - Vrabec, Jadran AU - Walther, Andrea ED - Bock, Hans Georg ED - Hoang, Xuan Phu ED - Rannacher, Rolf ED - Schlöder, Johannes P. ID - 1781 SN - 978-3-319-09063-4 T2 - Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) TI - Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres ER - TY - CONF AU - Graf, Tobias AU - Schaefers, Lars AU - Platzner, Marco ID - 1782 IS - 8427 T2 - Proc. Conf. on Computers and Games (CG) TI - On Semeai Detection in Monte-Carlo Go ER - TY - CONF AB - In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. AU - Kenter, Tobias AU - Vaz, Gavin Francis AU - Plessl, Christian ID - 388 T2 - Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC) TI - Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer VL - 8405 ER - TY - CONF AB - In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian AU - Sorge, Christoph ID - 377 KW - coldboot T2 - Proceedings of Field-Programmable Custom Computing Machines (FCCM) TI - Reconstructing AES Key Schedules from Decayed Memory with FPGAs ER - TY - CONF AU - C. Durelli, Gianluca AU - Pogliani, Marcello AU - Miele, Antonio AU - Plessl, Christian AU - Riebler, Heinrich AU - Vaz, Gavin Francis AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1778 T2 - Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) TI - Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach ER - TY - CONF AB - Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. AU - Vaz, Gavin Francis AU - Riebler, Heinrich AU - Kenter, Tobias AU - Plessl, Christian ID - 439 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Deferring Accelerator Offloading Decisions to Application Runtime ER - TY - CONF AB - Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. AU - Kenter, Tobias AU - Schmitz, Henning AU - Plessl, Christian ID - 406 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Kernel-Centric Acceleration of High Accuracy Stereo-Matching ER - TY - CONF AU - C. Durelli, Gianluca AU - Copolla, Marcello AU - Djafarian, Karim AU - Koranaros, George AU - Miele, Antonio AU - Paolino, Michele AU - Pell, Oliver AU - Plessl, Christian AU - D. Santambrogio, Marco AU - Bolchini, Cristiana ID - 1780 T2 - Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC) TI - SAVE: Towards efficient resource management in heterogeneous system architectures ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Gottfried, Viktor AU - Brinkmann, André ID - 1784 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - MCD: Overcoming the Data Download Bottleneck in Data Centers ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 1786 T2 - Proc. IEEE Signal Processing and Communications Conf. (SUI) TI - FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Meister, Dirk AU - Nagel, Lars ID - 1788 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Distributing Storage in Cloud Environments ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André AU - Süß, Tim ID - 1793 T2 - Proc. USENIX Conference on File and Storage Technologies (FAST) TI - File Recipe Compression in Data Deduplication Systems ER - TY - CONF AB - Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. AU - Riebler, Heinrich AU - Kenter, Tobias AU - Sorge, Christoph AU - Plessl, Christian ID - 528 KW - coldboot T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT) TI - FPGA-accelerated Key Search for Cold-Boot Attacks against AES ER - TY - CONF AB - In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. AU - Happe, Markus AU - Kling, Peter AU - Plessl, Christian AU - Platzner, Marco AU - Meyer auf der Heide, Friedhelm ID - 505 T2 - Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) TI - On-The-Fly Computing: A Novel Paradigm for Individualized IT Services ER - TY - CONF AU - Suess, Tim AU - Schoenrock, Andrew AU - Meisner, Sebastian AU - Plessl, Christian ID - 1787 SN - 978-0-7695-4979-8 T2 - Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) TI - Parallel Macro Pipelining on the Intel SCC Many-Core Computer ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2097 T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Hartung, Tim AU - Brinkmann, André ID - 2098 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - ESB: Ext2 Split Block Device ER - TY - CONF AU - Meister, Dirk AU - Kaiser, Jürgen AU - Brinkmann, André AU - Kuhn, Michael AU - Kunkel, Julian AU - Cortes, Toni ID - 2099 T2 - Proc. Int. Conf. on Supercomputing (SC) TI - A Study on Data Deduplication in HPC Storage Systems ER - TY - CONF AU - Kasap, Server AU - Redif, Soydan ID - 2100 T2 - Int. Architecture and Engineering Symp. (ARCHENG) TI - FPGA implementation of a second-order convolutive blind signal separation algorithm ER - TY - CONF AU - Grawinkel, Matthias AU - Süß, Tim AU - Best, Georg AU - Popov, Ivan AU - Brinkmann, André ID - 2101 T2 - Proc. Parallel Data Storage Workshop (PDSW) TI - Towards Dynamic Scripted pNFS Layouts ER - TY - CONF AU - Wistuba, Martin AU - Schaefers, Lars AU - Platzner, Marco ID - 2103 T2 - Proc. IEEE Conf. on Computational Intelligence and Games (CIG) TI - Comparison of Bayesian Move Prediction Systems for Computer Go ER - TY - CONF AU - Schlemmer, Tobias AU - Grunzke, Richard AU - Gesing, Sandra AU - Krüger, Jens AU - Birkenheuer, Georg AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2104 T2 - Proc. EGI Technical Forum TI - Generic User Management for Science Gateways via Virtual Organizations ER - TY - CONF AU - Congiu, Giuseppe AU - Grawinkel, Matthias AU - Narasimhamurthy, Sai AU - Brinkmann, André ID - 2105 T2 - Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) TI - One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services ER - TY - CONF AU - Grunzke, Richard AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Kruse, Martin AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuller, Bernd AU - Steinke, Thomas AU - Zink, Andreas ID - 2107 T2 - Proc. UNICORE Summit TI - A Data Driven Science Gateway for Computational Workflows ER - TY - CONF AU - Kaiser, Jürgen AU - Meister, Dirk AU - Brinkmann, André AU - Effert, Sascha ID - 1789 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - Design of an exact data deduplication cluster ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2171 T2 - Proc. EGI Community Forum TI - The MoSGrid Community From National to International Scale ER - TY - CONF AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Birkenheuer, Georg AU - Brinkmann, André AU - Grunzke, Richard AU - Kacsuk, Peter AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas ID - 2178 T2 - Proceedings of Science TI - A Science Gateway Getting Ready for Serving the International Molecular Simulation Community VL - PoS(EGICF12-EMITC2)050 ER - TY - CONF AB - Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator. In this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort can actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like programming environment exists. As case study we use an application from computational nanophotonics. Our results show that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view. AU - Meyer, Björn AU - Schumacher, Jörn AU - Plessl, Christian AU - Förstner, Jens ID - 2106 KW - funding-upb-forschungspreis KW - funding-maxup KW - tet_topic_hpc T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? ER - TY - CONF AB - Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. AU - Happe, Markus AU - Hangmann, Hendrik AU - Agne, Andreas AU - Plessl, Christian ID - 615 T2 - Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators ER - TY - CONF AB - One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. AU - Kenter, Tobias AU - Plessl, Christian AU - Schmitz, Henning ID - 591 T2 - Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) TI - Pragma based parallelization - Trading hardware efficiency for ease of use? ER - TY - CONF AB - Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian AU - Platzner, Marco ID - 609 T2 - Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) TI - Hardware/Software Platform for Self-aware Compute Nodes ER - TY - CONF AB - Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. AU - Barrio, Pablo AU - Carreras, Carlos AU - Sierra, Roberto AU - Kenter, Tobias AU - Plessl, Christian ID - 567 T2 - Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) TI - Turning control flow graphs into function calls: Code generation for heterogeneous architectures ER - TY - CONF AB - While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. AU - Rüthing, Christoph AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 612 T2 - Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) TI - Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2180 KW - funding-enhance T2 - Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) TI - Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux ER - TY - CONF AB - Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments. AU - Kleineweber, Christoph AU - Keller, Axel AU - Niehörster, Oliver AU - Brinkmann, André ID - 1968 T2 - Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) TI - Rule Based Mapping of Virtual Machines in Clouds ER - TY - CONF AB - We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. AU - Niehörster, Oliver AU - Keller, Axel AU - Brinkmann, André ID - 1972 T2 - Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - An Energy-Aware SaaS Stack ER - TY - CONF AU - Miranda, Alberto AU - Effert, Sascha AU - Kang, Yangwook AU - Miller, Ethan AU - Brinkmann, André AU - Cortes, Toni ID - 2188 T2 - Proc. Int. Conf. on High Performance Computing (HIPC) TI - Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems ER - TY - CONF AU - Grawinkel, Matthias AU - Pargmann, Markus AU - Dömer, Hubert AU - Brinkmann, André ID - 2189 T2 - Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) TI - Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André ID - 2190 T2 - Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) TI - Autonomic Resource Management Handling Delayed Configuration Effects ER - TY - CONF AU - Kenter, Tobias AU - Plessl, Christian AU - Platzner, Marco AU - Kauschke, Michael ID - 2191 KW - funding-intel T2 - Intel European Research and Innovation Conference TI - Estimation and Partitioning for CPU-Accelerator Architectures ER - TY - CONF AU - Grawinkel, Matthias AU - Schäfer, Thorsten AU - Brinkmann, André AU - Hagemeyer, Jens AU - Porrmann, Mario ID - 2195 T2 - Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) TI - Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability ER - TY - CONF AU - Brinkmann, André AU - Gao, Yan AU - Korzeniowski, Miroslaw AU - Meister, Dirk ID - 2196 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Request Load Balancing for Highly Skewed Traffic in P2P Networks ER - TY - CONF AU - Gesing, Sandra AU - Grunzke, Richard AU - Balaskó, Ákos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Herres-Pawlis, Sonja AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Krüger, Jens AU - Packschies, Lars AU - Schäfer, Patrick AU - Schuller, Bernd AU - Schuster, Johannes AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Wewior, Martin AU - Müller-Pfefferkorn, Ralph AU - Kohlbacher, Oliver ID - 2197 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Granular Security for a Science Gateway in Structural Bioinformatics ER - TY - CONF AU - Gesing, Sandra AU - Kacsuk, Peter AU - Kozlovszky, Miklos AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Steinke, Thomas AU - Szikszay Fabri, Anna AU - Warzecha, Klaus-Dieter AU - Wewior, Martin AU - Kohlbacher, Oliver ID - 2199 T2 - Proc. EGI User Forum TI - A Science Gateway for Molecular Simulations ER - TY - CONF AU - Niehörster, Oliver AU - Simon, Jens AU - Brinkmann, André AU - Krieger, Alexaner ID - 2203 SN - 978-0-7695-4572-1 T2 - Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) TI - Autonomic Resource Management with Support Vector Machines ER - TY - CONF AU - Graf, Tobias AU - Lorenz, Ulf AU - Platzner, Marco AU - Schaefers, Lars ID - 2204 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Parallel Monte-Carlo Tree Search for HPC Systems VL - 6853 ER - TY - CONF AU - Birkenheuer, Georg AU - Blunk, Dirk AU - Breuers, Sebastian AU - Brinkmann, André AU - Fels, Gregor AU - Gesing, Sandra AU - Grunzke, Richard AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Lang, Ulrich AU - Packschies, Lars AU - Müller-Pfefferkorn, Ralph AU - Schäfer, Patrick AU - Schuster, Johannes AU - Steinke, Thomas AU - Warzecha, Klaus-Dieter AU - Wewior, Martin ID - 2205 T2 - Proc. of Grid Workflow Workshop (GWW) TI - MoSGrid: Progress of Workflow driven Chemical Simulations VL - 829 ER - TY - CONF AU - Meyer, Björn AU - Plessl, Christian AU - Förstner, Jens ID - 2194 KW - tet_topic_hpc T2 - Symp. on Application Accelerators in High Performance Computing (SAAHPC) TI - Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend ER - TY - CONF AU - Beisel, Tobias AU - Wiersema, Tobias AU - Plessl, Christian AU - Brinkmann, André ID - 2193 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler ER - TY - CONF AB - In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. AU - Happe, Markus AU - Agne, Andreas AU - Plessl, Christian ID - 656 T2 - Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) TI - Measuring and Predicting Temperature Distributions on FPGAs at Run-Time ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2198 T2 - Proc. Reconfigurable Architectures Workshop (RAW) TI - Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Klonowski, Marek AU - Korzeniowski, Miroslaw ID - 2217 T2 - Proceedings of the 14th International Conference On Principles Of Distributed Systems (Opodis) TI - SkewCCC+: A Heterogeneous Distributed Hash Table VL - 6490 ER - TY - CONF AU - Wewior, Martin AU - Packschies, Lars AU - Blunk, Dirk AU - Wickeroth, Daniel AU - Warzecha, Klaus-Dieter AU - Herres-Pawlis, Sonja AU - Gesing, Sandra AU - Breuers, Sebastian AU - Krüger, Jens AU - Birkenheuer, Georg AU - Lang, Ulrich ID - 2218 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - The MoSGrid Gaussian Portlet - Technologies for the Implementation of Portlets for Molecular Simulations ER - TY - CONF AU - Gesing, Sandra AU - Marton, Istvan AU - Birkenheuer, Georg AU - Schuller, Bernd AU - Grunzke, Richard AU - Krüger, Jens AU - Breuers, Sebastian AU - Blunk, Dirk AU - Fels, Gregor AU - Packschies, Lars AU - Brinkmann, André AU - Kohlbacher, Oliver AU - Kozlovszky, Miklos ID - 2219 T2 - Proc. Int. Workshop on Scientific Gateways (IWSG) TI - Workflow Interoperability in a Grid Portal for Molecular Simulations ER - TY - CONF AU - Gao, Yan AU - Meister, Dirk AU - Brinkmann, André ID - 2225 T2 - Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) TI - Reliability Analysis of Declustered-Parity RAID 6 with Disk Scrubbing and Considering Irrecoverable Read Errors ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2229 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Balls into Bins with Related Random Choices ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2230 T2 - Proc. Symp. on Mass Storage Systems and Technologies (MSST) TI - dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD) ER - TY - CONF AU - Lensing, Paul Hermann AU - Meister, Dirk AU - Brinkmann, André ID - 2231 T2 - Proc. Int. Worksh. on Storage Network Architecture and Parallel I/Os (SNAPI) TI - hashFS: Applying Hashing to Optimized File Systems for Small File Reads ER - TY - CONF AU - Berenbrink, Petra AU - Brinkmann, André AU - Friedetzky, Tom AU - Nagel, Lars ID - 2232 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - Balls into Non-uniform Bins ER - TY - CONF AU - Bolte, Matthias AU - Sievers, Michael AU - Birkenheuer, Georg AU - Niehörster, Oliver AU - Brinkmann, André ID - 2234 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Non-intrusive Virtualization Management Using libvirt ER - TY - CONF AU - Birkenheuer, Georg AU - Breuers, Sebastian AU - Brinkmann, André AU - Blunk, Dirk AU - Fels, Gregor AU - Gesing, Sandra AU - Herres-Pawlis, Sonja AU - Kohlbacher, Oliver AU - Krüger, Jens AU - Packschies, Lars ID - 2236 T2 - Proc. of Grid Workflow Workshop (GWW) TI - Grid-Workflows in Molecular Science ER - TY - CONF AU - Niehörster, Oliver AU - Brinkmann, André AU - Fels, Gregor AU - Krüger, Jens AU - Simon, Jens ID - 2237 SN - 1552-5244 T2 - Proc. Int. Conf. on Cluster Computing (CLUSTER) TI - Enforcing SLAs in Scientific Clouds ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 809 T2 - Job Scheduling Strategies for Parallel Processing - 15th International Workshop, JSSPP 2010, Atlanta, GA, USA, April 23, 2010, Revised Selected Papers TI - Risk Aware Overbooking for Commercial Grids ER - TY - CONF AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian AU - Keller, Ariane AU - Plattner, Bernhard ID - 2223 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Towards Adaptive Networking for Embedded Devices based on Reconfigurable Hardware ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2216 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Pruning the Design Space for Just-In-Time Processor Customization ER - TY - CONF AU - Grad, Mariusz AU - Plessl, Christian ID - 2224 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - An Open Source Circuit Library with Benchmarking Facilities ER - TY - CONF AU - Andrews, David AU - Plessl, Christian ID - 2220 SN - 1-60132-140-6 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Configurable Processor Architectures: History and Trends ER - TY - CONF AU - Beisel, Tobias AU - Niekamp, Manuel AU - Plessl, Christian ID - 2226 SN - 978-1-4244-6965-9 T2 - Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) TI - Using Shared Library Interposing for Transparent Acceleration in Systems with Heterogeneous Hardware Accelerators ER - TY - CONF AU - Keller, Ariane AU - Plattner, Bernhard AU - Lübbers, Enno AU - Platzner, Marco AU - Plessl, Christian ID - 2206 SN - 978-1-4244-8864-3 T2 - Proc. IEEE Globecom Workshop on Network of the Future (FutureNet) TI - Reconfigurable Nodes for Future Networks ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Thiele, Lothar ID - 2227 SN - 978-1-4244-7911-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Rupeas: Ruby Powered Event Analysis DSL ER - TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ED - Hammami, Omar ED - Larrabee, Sandra ID - 2228 T2 - Proc. Workshop on Architectural Research Prototyping (WARP), International Symposium on Computer Architecture (ISCA) TI - Performance Estimation for the Exploration of CPU-Accelerator Architectures ER - TY - CONF AU - Höing, Andre AU - Scherp, Guido AU - Gudenkauf, Stefan AU - Meister, Dirk AU - Brinkmann, André ID - 2239 T2 - Proc. Int. Conf. on Service Oriented Computing (ICSOC) TI - An Orchestration as a Service Infrastructure using Grid Technologies and WS-BPEL VL - 5900 ER - TY - CONF AU - Niehörster, Oliver AU - Birkenheuer, Georg AU - Brinkmann, André AU - Blunk, Dirk AU - Elsässer, Brigitta AU - Herres-Pawlis, Sonja AU - Krüger, Jens AU - Niehörster, Julia AU - Packschies, Lars AU - Fels, Gregor ID - 2240 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Providing Scientific Software as a Service in Consideration of Service Level Agreements ER - TY - CONF AU - Birkenheuer, Georg AU - Carlson, Arthur AU - Fölling, Alexander AU - Högqvist, Mikael AU - Hoheisel, Andreas AU - Papaspyrou, Alexander AU - Rieger, Klaus AU - Schott, Bernhard AU - Ziegler, Wolfgang ID - 2260 SN - 978-83-61433-01-9 T2 - Proc. Cracow Grid Workshop (CGW) TI - Connecting Communities on the Meta-Scheduling Level: The DGSI Approach! ER - TY - CONF AU - Meister, Dirk AU - Brinkmann, André ID - 2264 T2 - Proc. of the Israeli Experimental Systems Conference (SYSTOR) TI - Multi-Level Comparison of Data Deduplication in a Backup Scenario ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, Andre AU - Karl, Holger ID - 818 T2 - Job Scheduling Strategies for Parallel Processing, 14th International Workshop, JSSPP 2009, Rome, Italy, May 29, 2009. Revised Papers TI - The Gain of Overbooking ER - TY - CONF AB - Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we first introduce the IMORC architectural template and the on-chip interconnect, and then demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XD1000 reconfigurable computing system. Using IMORC's monitoring infrastructure, we gain insights into the data-dependent behavior of the application which, in turn, allow for optimizing the accelerator. AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2350 KW - IMORC KW - interconnect KW - performance SN - 978-1-4244-4450-2 T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) TI - IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing ER - TY - CONF AB - In this work we present EvoCache, a novel approach for implementing application-specific caches. The key innovation of EvoCache is to make the function that maps memory addresses from the CPU address space to cache indices programmable. We support arbitrary Boolean mapping functions that are implemented within a small reconfigurable logic fabric. For finding suitable cache mapping functions we rely on techniques from the evolvable hardware domain and utilize an evolutionary optimization procedure. We evaluate the use of EvoCache in an embedded processor for two specific applications (JPEG and BZIP2 compression) with respect to execution time, cache miss rate and energy consumption. We show that the evolvable hardware approach for optimizing the cache functions not only significantly improves the cache performance for the training data used during optimization, but that the evolved mapping functions generalize very well. Compared to a conventional cache architecture, EvoCache applied to test data achieves a reduction in execution time of up to 14.31% for JPEG (10.98% for BZIP2), and in energy consumption by 16.43% for JPEG (10.70% for BZIP2). We also discuss the integration of EvoCache into the operating system and show that the area and delay overheads introduced by EvoCache are acceptable. AU - Kaufmann, Paul AU - Plessl, Christian AU - Platzner, Marco ID - 2262 KW - EvoCache KW - evolvable hardware KW - computer architecture T2 - Proc. NASA/ESA Conference on Adaptive Hardware and Systems (AHS) TI - EvoCaches: Application-specific Adaptation of Cache Mapping ER - TY - CONF AU - Beutel, Jan AU - Gruber, Stephan AU - Hasler, Andi AU - Lim, Roman AU - Meier, Andreas AU - Plessl, Christian AU - Talzi, Igor AU - Thiele, Lothar AU - Tschudin, Christian AU - Woehrle, Matthias AU - Yuecel, Mustafa ID - 2352 KW - WSN KW - PermaSense SN - 978-1-4244-5108-1 T2 - Proc. Int. Conf. on Information Processing in Sensor Networks (IPSN) TI - PermaDAQ: A Scientific Instrument for Precision Sensing and Data Recovery in Environmental Extremes ER - TY - CONF AU - Schumacher, Tobias AU - Süß, Tim AU - Plessl, Christian AU - Platzner, Marco ID - 2238 KW - IMORC KW - graphics SN - 978-0-7695-3917-1 T2 - Proc. Int. Conf. on ReConFigurable Computing and FPGAs (ReConFig) TI - Communication Performance Characterization for Reconfigurable Accelerator Design on the XD1000 ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2261 KW - IMORC KW - NOC KW - KNN KW - accelerator SN - 1946-1488 T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) TI - An Accelerator for k-th Nearest Neighbor Thinning Based on the IMORC Infrastructure ER - TY - CONF AB - In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Unit (APU) as well as the partial reconfiguration capabilities to provide dynamically reconfigurable custom instructions. We also present a hardware tool flow that automatically translates software functions into custom instructions and a software tool flow that creates binaries using these instructions. While previous research on processors with reconfigurable functional units has been performed predominantly with simulation, the Woolcano architecture allows for exploring dynamic instruction set extension with commercially available hardware. Finally, we present a case study demonstrating a custom floating-point instruction generated with our approach, which achieves a 40x speedup over software-emulated floating-point operations and a 21% speedup over the Xilinx hardware floating-point unit. AU - Grad, Mariusz AU - Plessl, Christian ID - 2263 SN - 1-60132-101-5 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - Woolcano: An Architecture and Tool Flow for Dynamic Instruction Set Extension on Xilinx Virtex-4 FX ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1974 T2 - Proc. Int. Conf. on Risks and Security of Internet and Systems TI - Quality Assurance of Grid Service Provisioning by Risk Aware Managing of Resource Failures ER - TY - CONF AB - Service Level Agreements (SLAs) have focal importance if the commercial customer should be attracted to the Grid. An SLA-aware resource management system has already been realize, able to fulfill the SLA of jobs even in the case of resource failures. For this, it is able to migrate checkpointed jobs over the Grid. At this, virtual execution environments allow to increase the number of potential migration targets significantly. In this paper we outline the concept of such virtual execution environments and focus on the SLA negotiation aspects. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1975 T2 - Proc. Int. DMTF Academic Alliance Workshop on Systems and Virtualization Management: Standards and New Technologies TI - Virtual Execution Environments and the Negotiation of Service Level Agreements in Grid Systems ER - TY - CONF AB - Abstract: Commercial Grid users demand for contractually fixed QoS levels. Service Level Agreements (SLAs) are powerful instruments for describing such contracts. SLA-aware resource management is the foundation for realizing SLA contracts within the Grid. OpenCCS is such an SLA-aware RMS, using transparent checkpointing to cope with resource outages. It generates a compatibility profile for each checkpoint dataset, so that the job can be resumed even on resources within the Grid. However, only a small number of Grid resources comply to such a profile. This paper describes the concept of virtual execution environments and how they increase the number of potential migration targets.The paper also describes how these virtual execution environments have been implemented within the OpenCCS resource management system. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1976 T2 - Proc. Int. Workshop on Scheduling and Resource Management for Parallel and Distributed Systems TI - Implementation of Virtual Execution Environments for improving SLA-compliant Job Migration in Grids ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1978 T2 - Proc. Int. Conf. on Grid Computing and Applications (GCA) TI - Germany, Belgium, France, and Back Again: Job Migration using Globus ER - TY - CONF AB - OpenCCS is an SLA-aware resource management system which uses transparent checkpointing of applications and migration of checkpoint datasets for ensuring SLA-compliance also in case of resource outages. Migration of checkpoints presumes a high grade of compatibility between source and target resource. Hence, even in large Grid systems only a small number of resources are eligible migration targets. This short paper describes the concept of virtual execution environments and how they increase the number of potential migration targets. It will also outline an implementation within OpenCCS. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1980 T2 - Proc. Int. Conf. on Services Computing (SCC) TI - Virtual Execution Environments for ensuring SLA-compliant Job Migration in Grids ER - TY - CONF AB - Contractually fixed service quality levels are mandatory prerequisites for attracting the commercial user to Grid environments. Service Level Agreements (SLAs) are powerful instruments for describing obligations and expectations in such a business relationship. At the level of local resource management systems, checkpointing and restart is an important instrument for realizing fault tolerance and SLA awareness. This paper highlights the concepts of migrating such checkpoint datasets to achieve the goal of SLA compliant job execution. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1981 SN - 978-0-7695-3177-9 T2 - Proc. Int. Conf. on Grid and Pervasive Computing (GPC) TI - Job Migration and Fault Tolerance in SLA-aware Resource Management Systems ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ED - Gonzalez, T. F. ID - 1983 SN - 978-0-88986-773-4 T2 - Proc. Int. Conf. on Parallel and Distributed Computing and Systems (PDCS) TI - Enhancing SLA Provisioning by Utilizing Profit-Oriented Fault Tolerance ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2355 T2 - Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS) TI - Redundant Data Placement Strategies for Cluster Storage Environments ER - TY - CONF AU - Brinkmann, André AU - Gudenkauf, Stefan AU - Hasselbring, Wilhelm AU - Höing, André AU - Karl, Holger AU - Kao, Odej AU - Nitsche, Holger AU - Scherp, Guido ID - 2356 T2 - Proc. Cracow Grid Workshop (CGW) TI - Employing WS-BPEL Design Patterns for Grid Service Orchestration using a Standard WS-BPEL Engine and a Grid Middleware ER - TY - CONF AU - Birkenheuer, Georg AU - Brinkmann, André AU - Dömer, Hubert AU - Effert, Sascha AU - Konersmann, Christoph AU - Niehörster, Oliver AU - Simon, Jens ID - 2357 T2 - Proc. Gemeinsamer Workshop der GI/ITG Fachgruppen "Betriebssysteme" und "KuVS": Virtualized IT infrastructures and their management TI - Virtual Supercomputer for HPC and HTC ER - TY - CONF AU - Beisel, Tobias AU - Lietsch, Stefan AU - Thielemans, Kris ID - 2358 T2 - IEEE Nuclear Science Symposium Conference Record (NSS) TI - A method for OSEM PET reconstruction on parallel architectures using STIR ER - TY - CONF AU - Battré, Dominic AU - Birkenheuer, Georg AU - Deora, Vikas AU - Hovestadt, Matthias AU - Rana, Omer AU - Wäldrich, Oliver ID - 2359 T2 - Proc. Cracow Grid Workshop (CGW) TI - Guarantee and Penalty Clauses for Service Level Agreements ER - TY - CONF AU - Richert, Willi AU - Niehörster, Oliver AU - Koch, Markus ID - 2360 T2 - Proc. IEEE/RSJ Int.Conf. on Intelligent Robots and Systems (IROS) TI - Layered understanding for sporadic imitation in a multi-robot scenario ER - TY - CONF AU - Lietsch, Stefan AU - Zabel, Henning AU - Laroque, Christoph ID - 2363 T2 - Proc. ASME Computers and Information in Engineering Conference (CIE) TI - Computational Steering Of Interactive Material Flow Simulations ER - TY - CONF AU - Platzner, Marco AU - Döhre, Sven AU - Happe, Markus AU - Kenter, Tobias AU - Lorenz, Ulf AU - Schumacher, Tobias AU - Send, Andre AU - Warkentin, Alexander ID - 2365 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - The GOmputer: Accelerating GO with FPGAs ER - TY - CONF AU - Lietsch, Stefan AU - Hermann Lensing, Paul ID - 2368 SN - 978-84-9830-164-9 T2 - Proc. Int. Symp. on Image/Video Communications over fixed and mobile networks (ISVC) TI - CUDA-based, parallel JPEG Compression for Remote Rendering ER - TY - CONF AU - Birkenheuer, Georg AU - Hovestadt, Matthias AU - Kao, Odej AU - Voß, Kerstin ID - 2369 T2 - Proc. Int. Conf. on Grid Computing & Applications (GCA) TI - Overbooking in Planning Based Scheduling Systems ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2371 T2 - Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) TI - Data Replication in P2P Environments ER - TY - CONF AU - Griese, Björn AU - Brinkmann, André AU - Porrmann, Mario ID - 2374 T2 - Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) TI - SelfS – A Real-Time Protocol for Virtual Ring Topologies ER - TY - CONF AU - Voss, Kerstin ID - 2375 T2 - Proc. Int. Conf. on Networking and Services (ICNS) TI - Recursive Evaluation of Fault Tolerance Mechanisms for SLA Management ER - TY - CONF AU - Brinkmann, André AU - Effert, Sascha ID - 2380 T2 - Proc. of the GI/ITG KuVS Fachgespr ̈ach Virtualisierung TI - Storage Cluster Architectures ER - TY - CONF AU - Richert, Willi AU - Klompmaker, Florian AU - Niehörster, Oliver ID - 2382 T2 - Proc. IFIP Conf. on Biologically Inspired Cooperative Computing (BICC) TI - Guiding exploration by combining individual learning and imitation in societies of autonomous robots ER - TY - CONF AU - Lietsch, Stefan AU - Hermann Lensing, Paul ID - 2383 T2 - Proc. Int. Symp. on Visual Computing (ISVC) TI - GPU-Supported Image Compression for Remote Visualization - Realization and Benchmarking VL - 5358 ER - TY - CONF AU - Bienkowski, Marcin AU - Brinkmann, André AU - Korzeniowski, Miroslaw ID - 2386 T2 - Proc. Int. Conf. on Principles Of DIstributed Systems (OPODIS) TI - Degree 3 Suffices: A Large-Scale Overlay for P2P Networks ER - TY - CONF AU - Battre, Dominic AU - Birkenheuer, Georg AU - Hovestadt, Matthias AU - Kao, Odej AU - Voss, Kerstin ID - 2387 T2 - Proc. Cracow Grid Workshop (CGW) TI - Applying Risk Management to Support SLA Provisioning ER - TY - CONF AU - Battré, Dominic AU - Kao, Odej AU - Voss, Kerstin ID - 2388 T2 - Proc. Usage of Service Level Agreements in Grids Workshop held in conjunction with International Conference on Grid Computing TI - Implementing WS-Agreement in a Globus Toolkit 4.0 Environment ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Lim, Roman AU - Beutel, Jan AU - Thiele, Lothar ID - 2370 KW - WSN KW - testing KW - verification SN - 978-0-7695-3158-8 T2 - IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC) TI - EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks ER - TY - CONF AU - Schumacher, Tobias AU - Meiche, Robert AU - Kaufmann, Paul AU - Lübbers, Enno AU - Plessl, Christian AU - Platzner, Marco ID - 2364 SN - 1-60132-064-7 T2 - Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) TI - A Hardware Accelerator for k-th Nearest Neighbor Thinning ER - TY - CONF AU - Schumacher, Tobias AU - Plessl, Christian AU - Platzner, Marco ID - 2372 KW - IMORC KW - IP core KW - interconnect T2 - Many-core and Reconfigurable Supercomputing Conference (MRSC) TI - IMORC: An infrastructure for performance monitoring and optimization of reconfigurable computers ER - TY - CONF AB - Service level agreements (SLAs) are powerful instruments for describing all obligations and expectations in a business relationship. It is of focal importance for deploying Grid technology to commercial applications. The EC-funded project HPC4U (Highly Predictable Clusters for Internet Grids) aimed at introducing SLA-awareness in local resource management systems, while the EC-funded project AssessGrid introduced the notion of risk, which is associated with every business contract. This paper highlights the concept of planning based resource management and describes the SLA-aware scheduler developed and used in these projects. AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1986 T2 - Proc. Workshop of the UK PLANNING AND SCHEDULING Special Interest Group (PlanSIG) TI - Planning-based Scheduling for SLA-awareness and Grid Integration ER - TY - CONF AU - Battré, Dominic AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Voss, Kerstin ID - 1988 T2 - Proc. Cracow Grid Workshop, Academic Computer Center CYFRNET TI - Transparent Cross Border Migration of Parallel Multi Node Applications ER - TY - CONF AU - Lietsch, Stefan AU - Marquardt, Oliver ID - 2389 SN - 978-3-540-76857-9 T2 - Proc. Int. Symp. on Visual Computing (ISVC) TI - A CUDA-Supported Approach to Remote Rendering VL - 4841 ER - TY - CONF AU - Voss, Kerstin ID - 2390 SN - 0-7695-3007-9 T2 - Proc. Int. Conf. on Semantics, Knowledge and Grid (SKG) TI - Comparing Fault Tolerance Mechanisms for Self-Organizing Resource Management in Grids ER - TY - CONF AU - Battré, Dominic AU - Djemame, Karim AU - Kao, Odej AU - Voss, Kerstin ID - 2391 T2 - Proc. Int. Conf. on Security and Privacy in Communications Networks (SecureComm) TI - Gaining Users' Trust by Publishing Failure Probabilities ER - TY - CONF AU - Voss, Kerstin AU - Djemame, Karim AU - Gourlay, Iain AU - Padgett, James ED - Altmann, Jörn ED - Veit, Daniel ID - 2396 T2 - Proc. Int. Worksh. on Grid Economics and Business Models (GECON) TI - AssessGrid, Economic Issues Underlying Risk Awareness in Grids VL - 4685 ER - TY - CONF AU - Voss, Kerstin ID - 2397 SN - 0-7695-2858-9 T2 - Proc. Int. Conf. on Networking and Services (ICNS) TI - Enhance Self-managing Grids by Risk Management ER - TY - CONF AU - Lietsch, Stefan AU - Zabel, Henning AU - Berssenbruegge, Jan ID - 2398 SN - 0-7918-3806-4 T2 - Proc. ASME Computers and Information in Engineering Conference (CIE) TI - Computational Steering of Interactive and Distributed Virtual Reality Applications ER - TY - CONF AU - Birkenheuer, Georg AU - Majlender, Peter AU - Nitsche, Holger AU - Voss, Kerstin AU - Weber, Elmar ID - 2399 T2 - Proc. Cracow Grid Workshop (CGW) TI - Gather and Prepare Monitoring Data for Estimating Resource Stability ER - TY - CONF AU - Berssenbrügge, Jan AU - Lietsch, Stefan ID - 2400 SN - 978-3-939350-28-6 T2 - Proc. Worksh. Augmented & Virtual Reality in der Produktentstehung TI - Verteilte Berechnung und Darstellung automobiler Scheinwerfer VL - 209 ER - TY - CONF AU - Woehrle, Matthias AU - Plessl, Christian AU - Beutel, Jan AU - Thiele, Lothar ID - 2392 KW - WSN KW - testing KW - distributed KW - embedded SN - 978-1-59593-694-3 T2 - Proc. Workshop on Embedded Networked Sensors (EmNets) TI - Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework ER - TY - CONF AU - Beutel, Jan AU - Dyer, Matthias AU - Lim, Roman AU - Plessl, Christian AU - Woehrle, Matthias AU - Yuecel, Mustafa AU - Thiele, Lothar ID - 2393 KW - WSN KW - testing KW - verification SN - 1-4244-1231-5 T2 - Proc. Int. Conf. Networked Sensing Systems (INSS) TI - Automated Wireless Sensor Network Testing ER - TY - CONF AU - Djemame, Karim AU - Gourlay, Iain AU - Padgett, James AU - Birkenheuer, Georg AU - Hovestadt, Matthias AU - Kao, Odej AU - Voss, Kerstin ID - 2402 SN - 0-7695-2734-5 T2 - Proc. Int. Conf. on e-Science and Grid Computing TI - Introducing Risk Management into the Grid ER - TY - CONF AU - Hovestadt, Matthias AU - Kao, Odej AU - Voss, Kerstin ID - 2403 SN - 0-7695-2670-5 T2 - Proc. Int. Conf. on Services Computing (SCC) TI - The First Step of Introducing Risk Management for Prepossessing SLAs ER - TY - CONF AU - Voss, Kerstin ID - 2406 SN - 0-7695-2622-5 T2 - Proc. Int. Conf. on Networking and Services (ICNS) TI - Risk Aware Migrations for Prepossessing SLAs ER - TY - CONF AU - Lietsch, Stefan AU - Zabel, Henning AU - Berssenbruegge, Jan AU - Wittenberg, Veit AU - Eikermann, Martin ID - 2407 SN - 3-540-48628-3 T2 - Proc. Int. Symp. on Visual Computing (ISVC) TI - Light Simulation in a Distributed Driving Simulator VL - 4291 ER - TY - CONF AU - Lerch, Nicolas AU - Nitsche, Holger AU - Voss, Kerstin AU - Hovestadt, Matthias ID - 2408 T2 - Proc. Cracow Grid Workshop (CGW) TI - First Steps of a Monitoring Framework to Empower Risk Assessment on Grids ER - TY - CONF AU - Birkenheuer, Georg AU - Döhre, Sven AU - Hovestadt, Matthias AU - Kao, Odej AU - Voss, Kerstin ID - 2409 T2 - Proc. Cracow Grid Workshop (CGW) TI - On Similarities of Grid Resources for Identifying Potential Migration Targets ER - TY - CONF AU - Birkenheuer, Georg AU - Djemame, Karim AU - Gourlay, Iain AU - Kao, Odej AU - Padgett, James AU - Voß, Kerstin ID - 2410 T2 - Proc. WS-Agreement Workshop (Open Grid Forum 18) TI - Using WS-Agreement for Risk Management in the Grid ER - TY - CONF AB - The next generation grid applications demand grid middleware for a flexible negotiation mechanism supporting various ways of quality-of-service (QoS) guarantees. In this context, a QoS guarantee covers simultaneous allocations of various kinds of different resources, such as processor runtime, storage capacity, or network bandwidth, which are specified in the form of service level agreements (SLA). Currently, a gap exists between the capabilities of grid middleware and the underlying resource management systems concerning their support for QoS and SLA negotiation. In this paper we present an approach which closes this gap. Introducing the architecture of the virtual resource manager, we highlight its main QoS management features like run-time responsibility, co-allocation, and fault tolerance. AU - Burchard, Lars-Olof AU - Heine, Felix AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Linnert, Barry ID - 1992 T2 - Proc. IEEE Int. Parallel & Distributed Processing Symposium (IPDPS) TI - A Quality-of-Service Architecture for Future Grid Computing Applications. ER - TY - CONF AU - Lietsch, Stefan AU - Kao, Odej ID - 2413 T2 - Proc. Intelligence in Communication Systems (INTELLCOMM) TI - CoLoS - A System for Device Unaware and Position Dependent Communication Based on the Session Initiation Protocol VL - 190 ER - TY - CONF AU - Birkenheuer, Georg AU - Hagelweide, Wilke AU - Hagemeier, Björn AU - Japs, Viktor AU - Keller, Matthias AU - Mayr, Nikolas AU - Meyer, Jan AU - Schumacher, Tobias AU - Voß, Kerstin AU - Zajac, Markus ID - 2414 T2 - Proc. GI Informatiktage TI - PIRANHA – Hunter of Idle Resources VL - 2 ER - TY - CONF AU - Kao, Odej AU - Hovestadt, Matthias AU - Keller, Axel ID - 1993 T2 - Proc. Advanced Research Workshop on High Perfomance Computing: Technology and Applications TI - SLA-aware Job Migration in Grid Environments ER - TY - CONF AU - Burchard, Lars-Olof AU - Heiss, Hans-Ulrich AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Linnert, Barry ID - 1994 T2 - Proceedings of the GI-Meeting on Operating Systems TI - An Architecture for SLA-aware Resource Management ER - TY - CONF AB - The next generation Grid will demand the Grid middleware to provide flexibility, transparency, and reliability. This implies the appliance of service level agreements to guarantee a negotiated level of quality of service. These requirements also affect the local resource management systems providing resources for the Grid. At this a gap between these demands and the features of today's resource management systems becomes apparent. In this paper we present an approach which closes this gap. Introducing the architecture of the virtual resource manager we highlight its main features of runtime responsibility, resource virtualization, information hiding, autonomy provision, and smooth integration of existing resource management system installations. AU - Burchard, Lars-Olof AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Linnert, Barry ID - 1995 T2 - Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID) TI - Virtual Resource Manager: An Architecture for SLA-aware Resource Management ER - TY - CONF AU - Groppe, Sven AU - Böttcher, Stefan AU - Birkenheuer, Georg ID - 2416 T2 - Proc. Int. Conf. on Enterprise Information Systems (ICEIS) TI - Efficient Querying of Transformed XML Documents ER - TY - CONF AU - Groppe, Sven AU - Böttcher, Stefan AU - Heckel, Reiko AU - Birkenheuer, Georg ID - 2417 T2 - Proc. East-European Conf. on Advances in Databases and Information Systems (ADBIS) TI - Using XSLT Stylesheets to Transform XPath Queries ER - TY - CONF AB - Nearly all existing HPC systems are operated by resource management systems based on the queuing approach. With the increasing acceptance of grid middleware like Globus, new requirements for the underlying local resource management systems arise. Features like advanced reservation or quality of service are needed to implement high level functions like co-allocation. However it is difficult to realize these features with a resource management system based on the queuing concept since it considers only the present resource usage. In this paper we present an approach which closes this gap. By assigning start times to each resource request, a complete schedule is planned. Advanced reservations are now easily possible. Based on this planning approach functions like diffuse requests, automatic duration extension, or service level agreements are described. We think they are useful to increase the usability, acceptance and performance of HPC machines. In the second part of this paper we present a planning based resource management system which already covers some of the mentioned features. AU - Hovestadt, Matthias AU - Kao, Odej AU - Keller, Axel AU - Streit, Achim ID - 1998 KW - High Performance Computing KW - Service Level Agreement KW - Grid Resource KW - Resource Management System KW - Advance Reservation T2 - Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) TI - Scheduling in HPC Resource Management Systems: Queuing vs. Planning VL - 2862 ER - TY - CONF AU - P. Miller, Barton AU - Labarta, Jesús AU - Schintke, Florian AU - Simon, Jens ID - 2426 SN - 978-3-540-45706-0 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Performance Evaluation, Analysis and Optimization VL - 2400 ER - TY - CONF AB - The Testbed and Applications working group of the European Grid Forum (EGrid) is actively building and experimenting with a grid infrastructure connecting several research-based supercomputing sites located in Europe. The paper reports on our first feasibility study: running a self-migrating version of the Cactus simulation code across the European grid testbed, including "live" remote data visualization and steering from different demonstration booths at Supercomputing 2000, in Dallas, TX. We report on the problems that had to be resolved for this endeavour and identify open research challenges for building production-grade grid environments. AU - Gehring, Jörn AU - Keller, Axel AU - Reinefeld, Alexander AU - Streit, Achim ID - 2000 T2 - Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID) TI - Early Experiences with the EGrid Testbed ER - TY - CONF AB - The availability of commodity high performance components for workstations and networks made it possible to build up large, PC based compute clusters at modest costs. These clusters seem to be a realistic alternative to proprietary, massively parallel systems with respect to the price/performance ratio. However, from the administration point of view, those systems are still often solely a collection of autonomous nodes, connected by a fast short area network. Therefore, aiming at providing the best possible performance in daily work to all users, a lot of work has to be done before obtaining the expected result. The paper describes the problem areas we had to cope with during the integration of two large SCI clusters (one with 64 and one with 192 processors) in the environment of the Paderborn Center for Parallel Computing. AU - Keller, Axel AU - Krawinkel, Andreas ID - 2002 T2 - Proc. Int. Symposium on Cluster Computing and the Grid (CCGRID) TI - Lessons Learned While Operating Two Large SCI Clusters ER - TY - CONF AU - Schintke, Florian AU - Simon, Jens AU - Reinefeld, Alexander ID - 2431 T2 - Proc. Int. Conf. on Computational Science (ICCS) TI - A Cache Simulator for Shared Memory Systems VL - 2074 ER - TY - CONF AB - RsdEditor is a graphical user interface which produces specifications of computational resources. It is used in the RSD (Resource and Service Description) environment for specifying, registering, requesting and accessing resources and services in a metacomputer. RsdEditor was designed to be used by the administrators and users of metacomputing environments. At the administrator level, the GUI is used to describe the available computing and networking components of a metacomputer. At the user level, RsdEditor can be used to specify which characteristics of the computational resources are needed to execute a meta-application. This paper is organized as follows: it first introduces RsdEditor. It then briefly describes the RSD environment, and finally, it highlights various features and implementation issues of RsdEditor. AU - Baraglia, Ranieri AU - Keller, Axel AU - Laforenza, Domenico AU - Reinefeld, Alexander ID - 2003 T2 - Proc. Heterogenous Computing Workshop HCW at IPDPS TI - RsdEditor: A Graphical User Interface for Specifying Metacomputer Components ER - TY - CONF AB - With the recent availability of cost-effective network cards for the PCI bus, researchers have been tempted to build up large compute clusters with standard PCs. Many of them are operated with workstation cluster management software in high-throughput or single user mode. For very large clusters with more than 100 PEs, however, it becomes necessary to implement a full fledged resource management software that allows to partition the system for multi-user access. In this paper, we present our Computing Center Software (CCS), which was originally designed for managing massively parallel high-performance computers, and now adapted to modern workstation clusters. It provides - partitioning of exclusive and non-exclusive resources, - hardware-independent scheduling of interactive and batch jobs, - open, extensible interfaces to other resource management systems, - a high degree of reliability. AU - Brune, Matthias AU - Keller, Axel AU - Reinefeld, Alexander ID - 2004 T2 - Proc. Int. Conf. on High-Performance Computing and Networking (HPCN) TI - Resource Management for High-Performance PC Clusters ER - TY - CONF AU - Brune, Matthias AU - Reinefeld, Alexander AU - Varnholt, Jörg ID - 2436 T2 - Proc. Int. Symp. High-Performance Distributed Computing (HPDC) TI - A Resource Description Environment for Distributed Computing Systems ER - TY - CONF AB - RSD (Resource and Service Description) is a scheme for specifying resources and services in complex heterogeneous computing systems and metacomputing environments. At the system administrator level, RSD is used to specify the available system components, such as the number of nodes, their interconnection topology, CPU speeds, and available software packages. At the user level, a GUI provides a comfortable, high-level interface for specifying system requests. A textual editor can be used for defining repetitive and recursive structures. This gives service providers the necessary flexibility for fine-grained specification of system topologies, interconnection networks, system and software dependent properties. All these representations are mapped onto a single, coherent internal object-oriented resource representation. Dynamic aspects (like network performance, availability of compute nodes, and compute node loads) are traced at runtime and included in the resource description to allow for optimal process mapping and dynamic task load balancing at runtime at the metacomputer level. This is done in a self-organizing way, with human system operators becoming only involved when new hardware/software components are installed. AU - Brune, Matthias AU - Gehring, Jörn AU - Keller, Axel AU - Reinefeld, Alexander ID - 2009 T2 - Proc. Int. Conf. on High-Performance Computing Systems (HPCS) TI - RSD - Resource and Service Description ER - TY - CONF AB - CCS is a resource management system for parallel high-performance computers. At the user level, CCS provides vendor-independent access to parallel systems. At the system administrator level, CCS offers tools for controlling (i.e, specifying, configuring and scheduling) the system components that are operated in a computing center. Hence the name "Computing Center Software". CCS provides: hardware-independent scheduling of interactive and batch jobs; partitioning of exclusive and non-exclusive resources; open, extensible interfaces to other resource management systems; a high degree of reliability (e.g. automatic restart of crashed daemons); fault tolerance in the case of network breakdowns. The authors describe CCS as one important component for the access, job distribution, and administration of networked HPC systems in a metacomputing environment. AU - Keller, Axel AU - Reinefeld, Alexander ID - 2011 T2 - Proc. Heterogenous Computing Workshop (HCW) at IPPS TI - CCS Resource Management in Networked HPC Systems ER - TY - CONF AU - Brune, Matthias AU - Hellmann, Christian AU - Keller, Axel ID - 2013 T2 - Proc. Workshop Hypercomputing at ITG/GI-Conference Architekur von Rechensystemen TI - A Closer Step towards Management of Metacomputing-Resources ER - TY - CONF AU - Simon, Jens AU - Weicker, Reinhold AU - Vieth, Marco ID - 2438 SN - 978-3-540-69549-3 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Workload Analysis of Computation Intensive Tasks: Case Study on SPEC CPU95 Benchmarks VL - 1300 ER - TY - CONF AU - Heinz, Oliver AU - Simon, Jens ID - 2439 T2 - Proc. Int. Conf. on Architecture of Computing Systems (ARCS) TI - Experiences with a SCI Multiprocessor Workstation Cluster ER - TY - CONF AU - Simon, Jens AU - Heinz, Oliver ID - 2440 T2 - Proc. Workshops im Rahmen der 14. ITG/GI-Fachtagung Architektur von Rechensystemen TI - SCI multiprocessor PC cluster in a WindowsNT environment ER - TY - CONF AU - Fischer, Markus AU - Simon, Jens ID - 2441 T2 - Proc. European Parallel Virtual Machine / Message Passing Interface Users’ Group Meeting (EuroPVM/MPI) TI - Embedding SCI into PVM VL - 1332 ER - TY - CONF AU - Reinefeld, Alexander AU - Baraglia, Ranieri AU - Decker, Thomas AU - Gehring, Jörn AU - Laforenza, Domenico AU - Ramme, Friedhelm AU - Römke, Thomas AU - Simon, Jens ID - 2442 T2 - Proc. Heterogenous Computing Workshop (HCW) TI - The MOL Project: An Open, Extensible Metacomputer ER - TY - CONF AU - Simon, Jens AU - Wierum, Jens-Michael ID - 2443 SN - 978-3-540-61142-4 T2 - Proc. Int. Conf. on High-Performance Computing and Networking (HPCN-Europe) TI - Sequential Performance versus Scalability: Optimizing Parallel LU-Decomposition VL - 1067 ER - TY - CONF AU - Simon, Jens AU - Wierum, Jens-Michael ID - 2444 T2 - Proc. Annual Int. Conf. on High-Performance Computers (HPCS) TI - Performance Prediction of Benchmark Programs for Massively Parallel Architectures ER - TY - CONF AU - Simon, Jens AU - Wierum, Jens-Michael ID - 2445 T2 - Proc. European Conf. on Parallel Processing (Euro-Par) TI - Accurate Performance Prediction for Massively Parallel Systems and its Applications VL - 1124 ER -