--- _id: '43439' abstract: - lang: eng text: "This preprint makes the claim of having computed the $9^{th}$ Dedekind\r\nNumber. This was done by building an efficient FPGA Accelerator for the core\r\noperation of the process, and parallelizing it on the Noctua 2 Supercluster at\r\nPaderborn University. The resulting value is\r\n286386577668298411128469151667598498812366. This value can be verified in two\r\nsteps. We have made the data file containing the 490M results available, each\r\nof which can be verified separately on CPU, and the whole file sums to our\r\nproposed value." author: - first_name: Lennart full_name: Van Hirtum, Lennart last_name: Van Hirtum - first_name: Patrick full_name: De Causmaecker, Patrick last_name: De Causmaecker - first_name: Jens full_name: Goemaere, Jens last_name: Goemaere - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Van Hirtum L, De Causmaecker P, Goemaere J, et al. A computation of D(9) using FPGA Supercomputing. arXiv:230403039. Published online 2023. apa: Van Hirtum, L., De Causmaecker, P., Goemaere, J., Kenter, T., Riebler, H., Lass, M., & Plessl, C. (2023). A computation of D(9) using FPGA Supercomputing. In arXiv:2304.03039. bibtex: '@article{Van Hirtum_De Causmaecker_Goemaere_Kenter_Riebler_Lass_Plessl_2023, title={A computation of D(9) using FPGA Supercomputing}, journal={arXiv:2304.03039}, author={Van Hirtum, Lennart and De Causmaecker, Patrick and Goemaere, Jens and Kenter, Tobias and Riebler, Heinrich and Lass, Michael and Plessl, Christian}, year={2023} }' chicago: Van Hirtum, Lennart, Patrick De Causmaecker, Jens Goemaere, Tobias Kenter, Heinrich Riebler, Michael Lass, and Christian Plessl. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023. ieee: L. Van Hirtum et al., “A computation of D(9) using FPGA Supercomputing,” arXiv:2304.03039. 2023. mla: Van Hirtum, Lennart, et al. “A Computation of D(9) Using FPGA Supercomputing.” ArXiv:2304.03039, 2023. short: L. Van Hirtum, P. De Causmaecker, J. Goemaere, T. Kenter, H. Riebler, M. Lass, C. Plessl, ArXiv:2304.03039 (2023). date_created: 2023-04-08T11:05:29Z date_updated: 2024-01-22T09:56:42Z department: - _id: '27' - _id: '518' external_id: arxiv: - '2304.03039' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2304.03039 status: public title: A computation of D(9) using FPGA Supercomputing type: preprint user_id: '3145' year: '2023' ... --- _id: '43228' abstract: - lang: eng text: "The computation of electron repulsion integrals (ERIs) over Gaussian-type orbitals (GTOs) is a challenging problem in quantum-mechanics-based atomistic simulations. In practical simulations, several trillions of ERIs may have to be\r\ncomputed for every time step.\r\nIn this work, we investigate FPGAs as accelerators for the ERI computation. We use template parameters, here within the Intel oneAPI tool flow, to create customized designs for 256 different ERI quartet classes, based on their orbitals. To maximize data reuse, all intermediates are buffered in FPGA on-chip memory with customized layout. The pre-calculation of intermediates also helps to overcome data dependencies caused by multi-dimensional recurrence\r\nrelations. The involved loop structures are partially or even fully unrolled for high throughput of FPGA kernels. Furthermore, a lossy compression algorithm utilizing arbitrary bitwidth integers is integrated in the FPGA kernels. To our\r\nbest knowledge, this is the first work on ERI computation on FPGAs that supports more than just the single most basic quartet class. Also, the integration of ERI computation and compression it a novelty that is not even covered by CPU or GPU libraries so far.\r\nOur evaluation shows that using 16-bit integer for the ERI compression, the fastest FPGA kernels exceed the performance of 10 GERIS ($10 \\times 10^9$ ERIs per second) on one Intel Stratix 10 GX 2800 FPGA, with maximum absolute errors around $10^{-7}$ - $10^{-5}$ Hartree. The measured throughput can be accurately explained by a performance model. The FPGA kernels deployed on 2 FPGAs outperform similar computations using the widely used libint reference on a two-socket server with 40 Xeon Gold 6148 CPU cores of the same process technology by factors up to 6.0x and on a new two-socket server with 128 EPYC 7713 CPU cores by up to 1.9x." author: - first_name: Xin full_name: Wu, Xin id: '77439' last_name: Wu - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Wu X, Kenter T, Schade R, Kühne T, Plessl C. Computing and Compressing Electron Repulsion Integrals on FPGAs. In: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). ; 2023:162-173. doi:10.1109/FCCM57271.2023.00026' apa: Wu, X., Kenter, T., Schade, R., Kühne, T., & Plessl, C. (2023). Computing and Compressing Electron Repulsion Integrals on FPGAs. 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–173. https://doi.org/10.1109/FCCM57271.2023.00026 bibtex: '@inproceedings{Wu_Kenter_Schade_Kühne_Plessl_2023, title={Computing and Compressing Electron Repulsion Integrals on FPGAs}, DOI={10.1109/FCCM57271.2023.00026}, booktitle={2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)}, author={Wu, Xin and Kenter, Tobias and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2023}, pages={162–173} }' chicago: Wu, Xin, Tobias Kenter, Robert Schade, Thomas Kühne, and Christian Plessl. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” In 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 162–73, 2023. https://doi.org/10.1109/FCCM57271.2023.00026. ieee: 'X. Wu, T. Kenter, R. Schade, T. Kühne, and C. Plessl, “Computing and Compressing Electron Repulsion Integrals on FPGAs,” in 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173, doi: 10.1109/FCCM57271.2023.00026.' mla: Wu, Xin, et al. “Computing and Compressing Electron Repulsion Integrals on FPGAs.” 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–73, doi:10.1109/FCCM57271.2023.00026. short: 'X. Wu, T. Kenter, R. Schade, T. Kühne, C. Plessl, in: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2023, pp. 162–173.' date_created: 2023-03-30T11:15:40Z date_updated: 2023-08-02T15:05:42Z department: - _id: '27' - _id: '518' doi: 10.1109/FCCM57271.2023.00026 external_id: arxiv: - '2303.13632' language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/document/10171537 page: 162-173 project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: 2023 IEEE 31st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) quality_controlled: '1' status: public title: Computing and Compressing Electron Repulsion Integrals on FPGAs type: conference user_id: '75963' year: '2023' ... --- _id: '46189' author: - first_name: Charles full_name: Prouveur, Charles last_name: Prouveur - first_name: Matthieu full_name: Haefele, Matthieu last_name: Haefele - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Nils full_name: Voss, Nils last_name: Voss citation: ama: 'Prouveur C, Haefele M, Kenter T, Voss N. FPGA Acceleration for HPC Supercapacitor Simulations. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2023. doi:10.1145/3592979.3593419' apa: Prouveur, C., Haefele, M., Kenter, T., & Voss, N. (2023). FPGA Acceleration for HPC Supercapacitor Simulations. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3592979.3593419 bibtex: '@inproceedings{Prouveur_Haefele_Kenter_Voss_2023, title={FPGA Acceleration for HPC Supercapacitor Simulations}, DOI={10.1145/3592979.3593419}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Prouveur, Charles and Haefele, Matthieu and Kenter, Tobias and Voss, Nils}, year={2023} }' chicago: Prouveur, Charles, Matthieu Haefele, Tobias Kenter, and Nils Voss. “FPGA Acceleration for HPC Supercapacitor Simulations.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2023. https://doi.org/10.1145/3592979.3593419. ieee: 'C. Prouveur, M. Haefele, T. Kenter, and N. Voss, “FPGA Acceleration for HPC Supercapacitor Simulations,” 2023, doi: 10.1145/3592979.3593419.' mla: Prouveur, Charles, et al. “FPGA Acceleration for HPC Supercapacitor Simulations.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023, doi:10.1145/3592979.3593419. short: 'C. Prouveur, M. Haefele, T. Kenter, N. Voss, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023.' date_created: 2023-07-28T09:46:25Z date_updated: 2023-07-28T09:58:16Z department: - _id: '27' - _id: '518' doi: 10.1145/3592979.3593419 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593419 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proceedings of the Platform for Advanced Scientific Computing Conference publication_status: published publisher: ACM quality_controlled: '1' status: public title: FPGA Acceleration for HPC Supercapacitor Simulations type: conference user_id: '3145' year: '2023' ... --- _id: '50172' abstract: - lang: eng text: "Viscous hydrodynamics serves as a successful mesoscopic description of the\r\nQuark-Gluon Plasma produced in relativistic heavy-ion collisions. In order to\r\ninvestigate, how such an effective description emerges from the underlying\r\nmicroscopic dynamics we calculate the hydrodynamic and non-hydrodynamic modes\r\nof linear response in the sound channel from a first-principle calculation in\r\nkinetic theory. We do this with a new approach wherein we discretize the\r\ncollision kernel to directly calculate eigenvalues and eigenmodes of the\r\nevolution operator. This allows us to study the Green's functions at any point\r\nin the complex frequency space. Our study focuses on scalar theory with quartic\r\ninteraction and we find that the analytic structure of Green's functions in the\r\ncomplex plane is far more complicated than just poles or cuts which is a first\r\nstep towards an equivalent study in QCD kinetic theory." author: - first_name: Stephan full_name: Ochsenfeld, Stephan last_name: Ochsenfeld - first_name: Sören full_name: Schlichting, Sören last_name: Schlichting citation: ama: Ochsenfeld S, Schlichting S. Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory. arXiv:230804491. Published online 2023. apa: Ochsenfeld, S., & Schlichting, S. (2023). Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory. In arXiv:2308.04491. bibtex: '@article{Ochsenfeld_Schlichting_2023, title={Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory}, journal={arXiv:2308.04491}, author={Ochsenfeld, Stephan and Schlichting, Sören}, year={2023} }' chicago: Ochsenfeld, Stephan, and Sören Schlichting. “Hydrodynamic and Non-Hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory.” ArXiv:2308.04491, 2023. ieee: S. Ochsenfeld and S. Schlichting, “Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory,” arXiv:2308.04491. 2023. mla: Ochsenfeld, Stephan, and Sören Schlichting. “Hydrodynamic and Non-Hydrodynamic Excitations in Kinetic Theory -- A  Numerical Analysis in Scalar Field Theory.” ArXiv:2308.04491, 2023. short: S. Ochsenfeld, S. Schlichting, ArXiv:2308.04491 (2023). date_created: 2024-01-04T08:47:38Z date_updated: 2024-01-04T08:47:47Z department: - _id: '27' external_id: arxiv: - '2308.04491' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2308.04491 status: public title: Hydrodynamic and Non-hydrodynamic Excitations in Kinetic Theory -- A Numerical Analysis in Scalar Field Theory type: preprint user_id: '67287' year: '2023' ... --- _id: '50221' abstract: - lang: eng text: "Memory Gym presents a suite of 2D partially observable environments, namely\r\nMortar Mayhem, Mystery Path, and Searing Spotlights, designed to benchmark\r\nmemory capabilities in decision-making agents. These environments, originally\r\nwith finite tasks, are expanded into innovative, endless formats, mirroring the\r\nescalating challenges of cumulative memory games such as ``I packed my bag''.\r\nThis progression in task design shifts the focus from merely assessing sample\r\nefficiency to also probing the levels of memory effectiveness in dynamic,\r\nprolonged scenarios. To address the gap in available memory-based Deep\r\nReinforcement Learning baselines, we introduce an implementation that\r\nintegrates Transformer-XL (TrXL) with Proximal Policy Optimization. This\r\napproach utilizes TrXL as a form of episodic memory, employing a sliding window\r\ntechnique. Our comparative study between the Gated Recurrent Unit (GRU) and\r\nTrXL reveals varied performances across different settings. TrXL, on the finite\r\nenvironments, demonstrates superior sample efficiency in Mystery Path and\r\noutperforms in Mortar Mayhem. However, GRU is more efficient on Searing\r\nSpotlights. Most notably, in all endless tasks, GRU makes a remarkable\r\nresurgence, consistently outperforming TrXL by significant margins. Website and\r\nSource Code: https://github.com/MarcoMeter/endless-memory-gym/" author: - first_name: Marco full_name: Pleines, Marco last_name: Pleines - first_name: Matthias full_name: Pallasch, Matthias last_name: Pallasch - first_name: Frank full_name: Zimmer, Frank last_name: Zimmer - first_name: Mike full_name: Preuss, Mike last_name: Preuss citation: ama: 'Pleines M, Pallasch M, Zimmer F, Preuss M. Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents. arXiv:230917207. Published online 2023.' apa: 'Pleines, M., Pallasch, M., Zimmer, F., & Preuss, M. (2023). Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents. In arXiv:2309.17207.' bibtex: '@article{Pleines_Pallasch_Zimmer_Preuss_2023, title={Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents}, journal={arXiv:2309.17207}, author={Pleines, Marco and Pallasch, Matthias and Zimmer, Frank and Preuss, Mike}, year={2023} }' chicago: 'Pleines, Marco, Matthias Pallasch, Frank Zimmer, and Mike Preuss. “Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents.” ArXiv:2309.17207, 2023.' ieee: 'M. Pleines, M. Pallasch, F. Zimmer, and M. Preuss, “Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents,” arXiv:2309.17207. 2023.' mla: 'Pleines, Marco, et al. “Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of  Agents.” ArXiv:2309.17207, 2023.' short: M. Pleines, M. Pallasch, F. Zimmer, M. Preuss, ArXiv:2309.17207 (2023). date_created: 2024-01-05T12:38:42Z date_updated: 2024-01-05T12:39:50Z department: - _id: '27' external_id: arxiv: - '2309.17207' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2309.17207 status: public title: 'Memory Gym: Towards Endless Tasks to Benchmark Memory Capabilities of Agents' type: preprint user_id: '67287' year: '2023' ... --- _id: '46190' author: - first_name: Jan-Oliver full_name: Opdenhövel, Jan-Oliver last_name: Opdenhövel - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter citation: ama: 'Opdenhövel J-O, Plessl C, Kenter T. Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. In: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM; 2023. doi:10.1145/3597031.3597050' apa: Opdenhövel, J.-O., Plessl, C., & Kenter, T. (2023). Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation. Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3597031.3597050 bibtex: '@inproceedings{Opdenhövel_Plessl_Kenter_2023, title={Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation}, DOI={10.1145/3597031.3597050}, booktitle={Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, publisher={ACM}, author={Opdenhövel, Jan-Oliver and Plessl, Christian and Kenter, Tobias}, year={2023} }' chicago: Opdenhövel, Jan-Oliver, Christian Plessl, and Tobias Kenter. “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.” In Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ACM, 2023. https://doi.org/10.1145/3597031.3597050. ieee: 'J.-O. Opdenhövel, C. Plessl, and T. Kenter, “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation,” 2023, doi: 10.1145/3597031.3597050.' mla: Opdenhövel, Jan-Oliver, et al. “Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation.” Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2023, doi:10.1145/3597031.3597050. short: 'J.-O. Opdenhövel, C. Plessl, T. Kenter, in: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, ACM, 2023.' date_created: 2023-07-28T09:49:23Z date_updated: 2023-07-28T09:58:06Z department: - _id: '27' - _id: '518' doi: 10.1145/3597031.3597050 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3597031.3597050 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proceedings of the 13th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies publication_status: published publisher: ACM quality_controlled: '1' status: public title: Mutation Tree Reconstruction of Tumor Cells on FPGAs Using a Bit-Level Matrix Representation type: conference user_id: '3145' year: '2023' ... --- _id: '46188' author: - first_name: Jennifer full_name: Faj, Jennifer id: '78722' last_name: Faj - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Sara full_name: Faghih-Naini, Sara last_name: Faghih-Naini - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Vadym full_name: Aizinger, Vadym last_name: Aizinger citation: ama: 'Faj J, Kenter T, Faghih-Naini S, Plessl C, Aizinger V. Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2023. doi:10.1145/3592979.3593407' apa: Faj, J., Kenter, T., Faghih-Naini, S., Plessl, C., & Aizinger, V. (2023). Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3592979.3593407 bibtex: '@inproceedings{Faj_Kenter_Faghih-Naini_Plessl_Aizinger_2023, title={Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes}, DOI={10.1145/3592979.3593407}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Faj, Jennifer and Kenter, Tobias and Faghih-Naini, Sara and Plessl, Christian and Aizinger, Vadym}, year={2023} }' chicago: Faj, Jennifer, Tobias Kenter, Sara Faghih-Naini, Christian Plessl, and Vadym Aizinger. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2023. https://doi.org/10.1145/3592979.3593407. ieee: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, and V. Aizinger, “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes,” 2023, doi: 10.1145/3592979.3593407.' mla: Faj, Jennifer, et al. “Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023, doi:10.1145/3592979.3593407. short: 'J. Faj, T. Kenter, S. Faghih-Naini, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2023.' date_created: 2023-07-28T09:42:14Z date_updated: 2023-07-28T09:48:19Z department: - _id: '27' - _id: '518' doi: 10.1145/3592979.3593407 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3592979.3593407 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proceedings of the Platform for Advanced Scientific Computing Conference publication_status: published publisher: ACM quality_controlled: '1' status: public title: Scalable Multi-FPGA Design of a Discontinuous Galerkin Shallow-Water Model on Unstructured Meshes type: conference user_id: '3145' year: '2023' ... --- _id: '46193' author: - first_name: Martin full_name: Karp, Martin last_name: Karp - first_name: Artur full_name: Podobas, Artur last_name: Podobas - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Niclas full_name: Jansson, Niclas last_name: Jansson - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Philipp full_name: Schlatter, Philipp last_name: Schlatter - first_name: Stefano full_name: Markidis, Stefano last_name: Markidis citation: ama: 'Karp M, Podobas A, Kenter T, et al. A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges. In: International Conference on High Performance Computing in Asia-Pacific Region. ACM; 2022. doi:10.1145/3492805.3492808' apa: 'Karp, M., Podobas, A., Kenter, T., Jansson, N., Plessl, C., Schlatter, P., & Markidis, S. (2022). A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges. International Conference on High Performance Computing in Asia-Pacific Region. https://doi.org/10.1145/3492805.3492808' bibtex: '@inproceedings{Karp_Podobas_Kenter_Jansson_Plessl_Schlatter_Markidis_2022, title={A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges}, DOI={10.1145/3492805.3492808}, booktitle={International Conference on High Performance Computing in Asia-Pacific Region}, publisher={ACM}, author={Karp, Martin and Podobas, Artur and Kenter, Tobias and Jansson, Niclas and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2022} }' chicago: 'Karp, Martin, Artur Podobas, Tobias Kenter, Niclas Jansson, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges.” In International Conference on High Performance Computing in Asia-Pacific Region. ACM, 2022. https://doi.org/10.1145/3492805.3492808.' ieee: 'M. Karp et al., “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges,” 2022, doi: 10.1145/3492805.3492808.' mla: 'Karp, Martin, et al. “A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges.” International Conference on High Performance Computing in Asia-Pacific Region, ACM, 2022, doi:10.1145/3492805.3492808.' short: 'M. Karp, A. Podobas, T. Kenter, N. Jansson, C. Plessl, P. Schlatter, S. Markidis, in: International Conference on High Performance Computing in Asia-Pacific Region, ACM, 2022.' date_created: 2023-07-28T11:51:55Z date_updated: 2023-07-28T11:53:15Z department: - _id: '27' - _id: '518' doi: 10.1145/3492805.3492808 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3492805.3492808 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: International Conference on High Performance Computing in Asia-Pacific Region publication_status: published publisher: ACM quality_controlled: '1' status: public title: 'A High-Fidelity Flow Solver for Unstructured Meshes on Field-Programmable Gate Arrays: Design, Evaluation, and Future Challenges' type: conference user_id: '3145' year: '2022' ... --- _id: '36879' abstract: - lang: eng text: The Julia programming language has evolved into a modern alternative to fill existing gaps in scientific computing and data science applications. Julia leverages a unified and coordinated single-language and ecosystem paradigm and has a proven track record of achieving high performance without sacrificing user productivity. These aspects make Julia a viable alternative to high-performance computing's (HPC's) existing and increasingly costly many-body workflow composition strategy in which traditional HPC languages (e.g., Fortran, C, C++) are used for simulations, and higher-level languages (e.g., Python, R, MATLAB) are used for data analysis and interactive computing. Julia's rapid growth in language capabilities, package ecosystem, and community make it a promising universal language for HPC. This paper presents the views of a multidisciplinary group of researchers from academia, government, and industry that advocate for an HPC software development paradigm that emphasizes developer productivity, workflow portability, and low barriers for entry. We believe that the Julia programming language, its ecosystem, and its community provide modern and powerful capabilities that enable this group's objectives. Crucially, we believe that Julia can provide a feasible and less costly approach to programming scientific applications and workflows that target HPC facilities. In this work, we examine the current practice and role of Julia as a common, end-to-end programming model to address major challenges in scientific reproducibility, data-driven AI/machine learning, co-design and workflows, scalability and performance portability in heterogeneous computing, network communication, data management, and community education. As a result, the diversification of current investments to fulfill the needs of the upcoming decade is crucial as more supercomputing centers prepare for the exascale era. author: - first_name: Valentin full_name: Churavy, Valentin last_name: Churavy - first_name: William F full_name: Godoy, William F last_name: Godoy - first_name: Carsten full_name: Bauer, Carsten id: '90082' last_name: Bauer - first_name: Hendrik full_name: Ranocha, Hendrik last_name: Ranocha - first_name: Michael full_name: Schlottke-Lakemper, Michael last_name: Schlottke-Lakemper - first_name: Ludovic full_name: Räss, Ludovic last_name: Räss - first_name: Johannes full_name: Blaschke, Johannes last_name: Blaschke - first_name: Mosè full_name: Giordano, Mosè last_name: Giordano - first_name: Erik full_name: Schnetter, Erik last_name: Schnetter - first_name: Samuel full_name: Omlin, Samuel last_name: Omlin - first_name: Jeffrey S full_name: Vetter, Jeffrey S last_name: Vetter - first_name: Alan full_name: Edelman, Alan last_name: Edelman citation: ama: Churavy V, Godoy WF, Bauer C, et al. Bridging HPC Communities through the Julia Programming Language. Published online 2022. apa: Churavy, V., Godoy, W. F., Bauer, C., Ranocha, H., Schlottke-Lakemper, M., Räss, L., Blaschke, J., Giordano, M., Schnetter, E., Omlin, S., Vetter, J. S., & Edelman, A. (2022). Bridging HPC Communities through the Julia Programming Language. bibtex: '@article{Churavy_Godoy_Bauer_Ranocha_Schlottke-Lakemper_Räss_Blaschke_Giordano_Schnetter_Omlin_et al._2022, title={Bridging HPC Communities through the Julia Programming Language}, author={Churavy, Valentin and Godoy, William F and Bauer, Carsten and Ranocha, Hendrik and Schlottke-Lakemper, Michael and Räss, Ludovic and Blaschke, Johannes and Giordano, Mosè and Schnetter, Erik and Omlin, Samuel and et al.}, year={2022} }' chicago: Churavy, Valentin, William F Godoy, Carsten Bauer, Hendrik Ranocha, Michael Schlottke-Lakemper, Ludovic Räss, Johannes Blaschke, et al. “Bridging HPC Communities through the Julia Programming Language,” 2022. ieee: V. Churavy et al., “Bridging HPC Communities through the Julia Programming Language.” 2022. mla: Churavy, Valentin, et al. Bridging HPC Communities through the Julia Programming Language. 2022. short: V. Churavy, W.F. Godoy, C. Bauer, H. Ranocha, M. Schlottke-Lakemper, L. Räss, J. Blaschke, M. Giordano, E. Schnetter, S. Omlin, J.S. Vetter, A. Edelman, (2022). date_created: 2023-01-16T09:10:48Z date_updated: 2023-01-16T09:16:20Z department: - _id: '27' language: - iso: eng main_file_link: - open_access: '1' url: https://arxiv.org/abs/2211.02740 oa: '1' status: public title: Bridging HPC Communities through the Julia Programming Language type: preprint user_id: '90082' year: '2022' ... --- _id: '32404' abstract: - lang: eng text: "The CP2K program package, which can be considered as the swiss army knife of\r\natomistic simulations, is presented with a special emphasis on ab-initio\r\nmolecular dynamics using the second-generation Car-Parrinello method. After\r\noutlining current and near-term development efforts with regards to massively\r\nparallel low-scaling post-Hartree-Fock and eigenvalue solvers, novel approaches\r\non how we plan to take full advantage of future low-precision hardware\r\narchitectures are introduced. Our focus here is on combining our submatrix\r\nmethod with the approximate computing paradigm to address the immanent exascale\r\nera." author: - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Ole full_name: Schütt, Ole last_name: Schütt citation: ama: Kühne T, Plessl C, Schade R, Schütt O. CP2K on the road to exascale. arXiv:220514741. Published online 2022. apa: Kühne, T., Plessl, C., Schade, R., & Schütt, O. (2022). CP2K on the road to exascale. In arXiv:2205.14741. bibtex: '@article{Kühne_Plessl_Schade_Schütt_2022, title={CP2K on the road to exascale}, journal={arXiv:2205.14741}, author={Kühne, Thomas and Plessl, Christian and Schade, Robert and Schütt, Ole}, year={2022} }' chicago: Kühne, Thomas, Christian Plessl, Robert Schade, and Ole Schütt. “CP2K on the Road to Exascale.” ArXiv:2205.14741, 2022. ieee: T. Kühne, C. Plessl, R. Schade, and O. Schütt, “CP2K on the road to exascale,” arXiv:2205.14741. 2022. mla: Kühne, Thomas, et al. “CP2K on the Road to Exascale.” ArXiv:2205.14741, 2022. short: T. Kühne, C. Plessl, R. Schade, O. Schütt, ArXiv:2205.14741 (2022). date_created: 2022-07-22T08:14:08Z date_updated: 2023-08-02T14:55:35Z department: - _id: '27' - _id: '518' - _id: '304' external_id: arxiv: - '2205.14741' language: - iso: eng main_file_link: - url: https://arxiv.org/abs/2205.14741 project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2205.14741 status: public title: CP2K on the road to exascale type: preprint user_id: '75963' year: '2022' ... --- _id: '32177' abstract: - lang: eng text: "We investigate the early time development of the anisotropic transverse flow\r\nand spatial eccentricities of a fireball with various particle-based transport\r\napproaches using a fixed initial condition. In numerical simulations ranging\r\nfrom the quasi-collisionless case to the hydrodynamic regime, we find that the\r\nonset of $v_n$ and of related measures of anisotropic flow can be described\r\nwith a simple power-law ansatz, with an exponent that depends on the amount of\r\nrescatterings in the system. In the few-rescatterings regime we perform\r\nsemi-analytical calculations, based on a systematic expansion in powers of time\r\nand the cross section, which can reproduce the numerical findings." author: - first_name: Nicolas full_name: Borghini, Nicolas last_name: Borghini - first_name: Marc full_name: Borrell, Marc last_name: Borrell - first_name: Hendrik full_name: Roch, Hendrik last_name: Roch citation: ama: Borghini N, Borrell M, Roch H. Early time behavior of spatial and momentum anisotropies in kinetic  theory across different Knudsen numbers. arXiv:220113294. Published online 2022. apa: Borghini, N., Borrell, M., & Roch, H. (2022). Early time behavior of spatial and momentum anisotropies in kinetic  theory across different Knudsen numbers. In arXiv:2201.13294. bibtex: '@article{Borghini_Borrell_Roch_2022, title={Early time behavior of spatial and momentum anisotropies in kinetic  theory across different Knudsen numbers}, journal={arXiv:2201.13294}, author={Borghini, Nicolas and Borrell, Marc and Roch, Hendrik}, year={2022} }' chicago: Borghini, Nicolas, Marc Borrell, and Hendrik Roch. “Early Time Behavior of Spatial and Momentum Anisotropies in Kinetic  Theory across Different Knudsen Numbers.” ArXiv:2201.13294, 2022. ieee: N. Borghini, M. Borrell, and H. Roch, “Early time behavior of spatial and momentum anisotropies in kinetic  theory across different Knudsen numbers,” arXiv:2201.13294. 2022. mla: Borghini, Nicolas, et al. “Early Time Behavior of Spatial and Momentum Anisotropies in Kinetic  Theory across Different Knudsen Numbers.” ArXiv:2201.13294, 2022. short: N. Borghini, M. Borrell, H. Roch, ArXiv:2201.13294 (2022). date_created: 2022-06-27T09:08:04Z date_updated: 2022-06-27T09:35:53Z department: - _id: '27' external_id: arxiv: - '2201.13294' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2201.13294 status: public title: Early time behavior of spatial and momentum anisotropies in kinetic theory across different Knudsen numbers type: preprint user_id: '67287' year: '2022' ... --- _id: '32178' abstract: - lang: eng text: "We test the ability of the \"escape mechanism\" to create the anisotropic flow\r\nobserved in high-energy nuclear collisions. We compare the flow harmonics $v_n$\r\nin the few-rescatterings regime from two types of transport simulations, with\r\n$2\\to 2$ and $2\\to 0$ collision kernels respectively, and from analytical\r\ncalculations neglecting the gain term of the Boltzmann equation. We find that\r\nthe even flow harmonics are similar in the three approaches, while the odd\r\nharmonics differ significantly." author: - first_name: Benedikt full_name: Bachmann, Benedikt last_name: Bachmann - first_name: Nicolas full_name: Borghini, Nicolas last_name: Borghini - first_name: Nina full_name: Feld, Nina last_name: Feld - first_name: Hendrik full_name: Roch, Hendrik last_name: Roch citation: ama: Bachmann B, Borghini N, Feld N, Roch H. Even anisotropic-flow harmonics are from Venus, odd ones are from Mars. arXiv:220313306. Published online 2022. apa: Bachmann, B., Borghini, N., Feld, N., & Roch, H. (2022). Even anisotropic-flow harmonics are from Venus, odd ones are from Mars. In arXiv:2203.13306. bibtex: '@article{Bachmann_Borghini_Feld_Roch_2022, title={Even anisotropic-flow harmonics are from Venus, odd ones are from Mars}, journal={arXiv:2203.13306}, author={Bachmann, Benedikt and Borghini, Nicolas and Feld, Nina and Roch, Hendrik}, year={2022} }' chicago: Bachmann, Benedikt, Nicolas Borghini, Nina Feld, and Hendrik Roch. “Even Anisotropic-Flow Harmonics Are from Venus, Odd Ones Are from Mars.” ArXiv:2203.13306, 2022. ieee: B. Bachmann, N. Borghini, N. Feld, and H. Roch, “Even anisotropic-flow harmonics are from Venus, odd ones are from Mars,” arXiv:2203.13306. 2022. mla: Bachmann, Benedikt, et al. “Even Anisotropic-Flow Harmonics Are from Venus, Odd Ones Are from Mars.” ArXiv:2203.13306, 2022. short: B. Bachmann, N. Borghini, N. Feld, H. Roch, ArXiv:2203.13306 (2022). date_created: 2022-06-27T09:12:26Z date_updated: 2022-06-27T09:35:34Z department: - _id: '27' external_id: arxiv: - '2203.13306' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2203.13306 status: public title: Even anisotropic-flow harmonics are from Venus, odd ones are from Mars type: preprint user_id: '67287' year: '2022' ... --- _id: '33493' abstract: - lang: eng text: "Electronic structure calculations have been instrumental in providing many\r\nimportant insights into a range of physical and chemical properties of various\r\nmolecular and solid-state systems. Their importance to various fields,\r\nincluding materials science, chemical sciences, computational chemistry and\r\ndevice physics, is underscored by the large fraction of available public\r\nsupercomputing resources devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities to increase simulation numbers, sizes,\r\nand accuracies present themselves. In order to realize these promises, the\r\ncommunity of electronic structure software developers will however first have\r\nto tackle a number of challenges pertaining to the efficient use of new\r\narchitectures that will rely heavily on massive parallelism and hardware\r\naccelerators. This roadmap provides a broad overview of the state-of-the-art in\r\nelectronic structure calculations and of the various new directions being\r\npursued by the community. It covers 14 electronic structure codes, presenting\r\ntheir current status, their development priorities over the next five years,\r\nand their plans towards tackling the challenges and leveraging the\r\nopportunities presented by the advent of exascale computing." author: - first_name: Vikram full_name: Gavini, Vikram last_name: Gavini - first_name: Stefano full_name: Baroni, Stefano last_name: Baroni - first_name: Volker full_name: Blum, Volker last_name: Blum - first_name: David R. full_name: Bowler, David R. last_name: Bowler - first_name: Alexander full_name: Buccheri, Alexander last_name: Buccheri - first_name: James R. full_name: Chelikowsky, James R. last_name: Chelikowsky - first_name: Sambit full_name: Das, Sambit last_name: Das - first_name: William full_name: Dawson, William last_name: Dawson - first_name: Pietro full_name: Delugas, Pietro last_name: Delugas - first_name: Mehmet full_name: Dogan, Mehmet last_name: Dogan - first_name: Claudia full_name: Draxl, Claudia last_name: Draxl - first_name: Giulia full_name: Galli, Giulia last_name: Galli - first_name: Luigi full_name: Genovese, Luigi last_name: Genovese - first_name: Paolo full_name: Giannozzi, Paolo last_name: Giannozzi - first_name: Matteo full_name: Giantomassi, Matteo last_name: Giantomassi - first_name: Xavier full_name: Gonze, Xavier last_name: Gonze - first_name: Marco full_name: Govoni, Marco last_name: Govoni - first_name: Andris full_name: Gulans, Andris last_name: Gulans - first_name: François full_name: Gygi, François last_name: Gygi - first_name: John M. full_name: Herbert, John M. last_name: Herbert - first_name: Sebastian full_name: Kokott, Sebastian last_name: Kokott - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Kai-Hsin full_name: Liou, Kai-Hsin last_name: Liou - first_name: Tsuyoshi full_name: Miyazaki, Tsuyoshi last_name: Miyazaki - first_name: Phani full_name: Motamarri, Phani last_name: Motamarri - first_name: Ayako full_name: Nakata, Ayako last_name: Nakata - first_name: John E. full_name: Pask, John E. last_name: Pask - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Laura E. full_name: Ratcliff, Laura E. last_name: Ratcliff - first_name: Ryan M. full_name: Richard, Ryan M. last_name: Richard - first_name: Mariana full_name: Rossi, Mariana last_name: Rossi - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Matthias full_name: Scheffler, Matthias last_name: Scheffler - first_name: Ole full_name: Schütt, Ole last_name: Schütt - first_name: Phanish full_name: Suryanarayana, Phanish last_name: Suryanarayana - first_name: Marc full_name: Torrent, Marc last_name: Torrent - first_name: Lionel full_name: Truflandier, Lionel last_name: Truflandier - first_name: Theresa L. full_name: Windus, Theresa L. last_name: Windus - first_name: Qimen full_name: Xu, Qimen last_name: Xu - first_name: Victor W. -Z. full_name: Yu, Victor W. -Z. last_name: Yu - first_name: Danny full_name: Perez, Danny last_name: Perez citation: ama: Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022. apa: Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky, J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese, L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F., … Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era. In arXiv:2209.12747. bibtex: '@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747}, author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson, William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }' chicago: Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022. ieee: V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale Era,” arXiv:2209.12747. 2022. mla: Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022. short: V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022). date_created: 2022-09-28T05:25:10Z date_updated: 2023-07-28T08:03:41Z department: - _id: '27' - _id: '518' external_id: arxiv: - '2209.12747' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2209.12747 status: public title: Roadmap on Electronic Structure Codes in the Exascale Era type: preprint user_id: '24135' year: '2022' ... --- _id: '46275' abstract: - lang: eng text: "Electronic structure calculations have been instrumental in providing many\r\nimportant insights into a range of physical and chemical properties of various\r\nmolecular and solid-state systems. Their importance to various fields,\r\nincluding materials science, chemical sciences, computational chemistry and\r\ndevice physics, is underscored by the large fraction of available public\r\nsupercomputing resources devoted to these calculations. As we enter the\r\nexascale era, exciting new opportunities to increase simulation numbers, sizes,\r\nand accuracies present themselves. In order to realize these promises, the\r\ncommunity of electronic structure software developers will however first have\r\nto tackle a number of challenges pertaining to the efficient use of new\r\narchitectures that will rely heavily on massive parallelism and hardware\r\naccelerators. This roadmap provides a broad overview of the state-of-the-art in\r\nelectronic structure calculations and of the various new directions being\r\npursued by the community. It covers 14 electronic structure codes, presenting\r\ntheir current status, their development priorities over the next five years,\r\nand their plans towards tackling the challenges and leveraging the\r\nopportunities presented by the advent of exascale computing." author: - first_name: Vikram full_name: Gavini, Vikram last_name: Gavini - first_name: Stefano full_name: Baroni, Stefano last_name: Baroni - first_name: Volker full_name: Blum, Volker last_name: Blum - first_name: David R. full_name: Bowler, David R. last_name: Bowler - first_name: Alexander full_name: Buccheri, Alexander last_name: Buccheri - first_name: James R. full_name: Chelikowsky, James R. last_name: Chelikowsky - first_name: Sambit full_name: Das, Sambit last_name: Das - first_name: William full_name: Dawson, William last_name: Dawson - first_name: Pietro full_name: Delugas, Pietro last_name: Delugas - first_name: Mehmet full_name: Dogan, Mehmet last_name: Dogan - first_name: Claudia full_name: Draxl, Claudia last_name: Draxl - first_name: Giulia full_name: Galli, Giulia last_name: Galli - first_name: Luigi full_name: Genovese, Luigi last_name: Genovese - first_name: Paolo full_name: Giannozzi, Paolo last_name: Giannozzi - first_name: Matteo full_name: Giantomassi, Matteo last_name: Giantomassi - first_name: Xavier full_name: Gonze, Xavier last_name: Gonze - first_name: Marco full_name: Govoni, Marco last_name: Govoni - first_name: Andris full_name: Gulans, Andris last_name: Gulans - first_name: François full_name: Gygi, François last_name: Gygi - first_name: John M. full_name: Herbert, John M. last_name: Herbert - first_name: Sebastian full_name: Kokott, Sebastian last_name: Kokott - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Kai-Hsin full_name: Liou, Kai-Hsin last_name: Liou - first_name: Tsuyoshi full_name: Miyazaki, Tsuyoshi last_name: Miyazaki - first_name: Phani full_name: Motamarri, Phani last_name: Motamarri - first_name: Ayako full_name: Nakata, Ayako last_name: Nakata - first_name: John E. full_name: Pask, John E. last_name: Pask - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Laura E. full_name: Ratcliff, Laura E. last_name: Ratcliff - first_name: Ryan M. full_name: Richard, Ryan M. last_name: Richard - first_name: Mariana full_name: Rossi, Mariana last_name: Rossi - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Matthias full_name: Scheffler, Matthias last_name: Scheffler - first_name: Ole full_name: Schütt, Ole last_name: Schütt - first_name: Phanish full_name: Suryanarayana, Phanish last_name: Suryanarayana - first_name: Marc full_name: Torrent, Marc last_name: Torrent - first_name: Lionel full_name: Truflandier, Lionel last_name: Truflandier - first_name: Theresa L. full_name: Windus, Theresa L. last_name: Windus - first_name: Qimen full_name: Xu, Qimen last_name: Xu - first_name: Victor W. -Z. full_name: Yu, Victor W. -Z. last_name: Yu - first_name: Danny full_name: Perez, Danny last_name: Perez citation: ama: Gavini V, Baroni S, Blum V, et al. Roadmap on Electronic Structure Codes in the Exascale Era. arXiv:220912747. Published online 2022. apa: Gavini, V., Baroni, S., Blum, V., Bowler, D. R., Buccheri, A., Chelikowsky, J. R., Das, S., Dawson, W., Delugas, P., Dogan, M., Draxl, C., Galli, G., Genovese, L., Giannozzi, P., Giantomassi, M., Gonze, X., Govoni, M., Gulans, A., Gygi, F., … Perez, D. (2022). Roadmap on Electronic Structure Codes in the Exascale Era. In arXiv:2209.12747. bibtex: '@article{Gavini_Baroni_Blum_Bowler_Buccheri_Chelikowsky_Das_Dawson_Delugas_Dogan_et al._2022, title={Roadmap on Electronic Structure Codes in the Exascale Era}, journal={arXiv:2209.12747}, author={Gavini, Vikram and Baroni, Stefano and Blum, Volker and Bowler, David R. and Buccheri, Alexander and Chelikowsky, James R. and Das, Sambit and Dawson, William and Delugas, Pietro and Dogan, Mehmet and et al.}, year={2022} }' chicago: Gavini, Vikram, Stefano Baroni, Volker Blum, David R. Bowler, Alexander Buccheri, James R. Chelikowsky, Sambit Das, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022. ieee: V. Gavini et al., “Roadmap on Electronic Structure Codes in the Exascale Era,” arXiv:2209.12747. 2022. mla: Gavini, Vikram, et al. “Roadmap on Electronic Structure Codes in the Exascale Era.” ArXiv:2209.12747, 2022. short: V. Gavini, S. Baroni, V. Blum, D.R. Bowler, A. Buccheri, J.R. Chelikowsky, S. Das, W. Dawson, P. Delugas, M. Dogan, C. Draxl, G. Galli, L. Genovese, P. Giannozzi, M. Giantomassi, X. Gonze, M. Govoni, A. Gulans, F. Gygi, J.M. Herbert, S. Kokott, T. Kühne, K.-H. Liou, T. Miyazaki, P. Motamarri, A. Nakata, J.E. Pask, C. Plessl, L.E. Ratcliff, R.M. Richard, M. Rossi, R. Schade, M. Scheffler, O. Schütt, P. Suryanarayana, M. Torrent, L. Truflandier, T.L. Windus, Q. Xu, V.W.-Z. Yu, D. Perez, ArXiv:2209.12747 (2022). date_created: 2023-08-02T14:59:18Z date_updated: 2023-08-02T15:00:47Z department: - _id: '27' external_id: arxiv: - '2209.12747' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2209.12747 status: public title: Roadmap on Electronic Structure Codes in the Exascale Era type: preprint user_id: '75963' year: '2022' ... --- _id: '46194' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Adesh full_name: Shambhu, Adesh last_name: Shambhu - first_name: Sara full_name: Faghih-Naini, Sara last_name: Faghih-Naini - first_name: Vadym full_name: Aizinger, Vadym last_name: Aizinger citation: ama: 'Kenter T, Shambhu A, Faghih-Naini S, Aizinger V. Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. In: Proceedings of the Platform for Advanced Scientific Computing Conference. ACM; 2021. doi:10.1145/3468267.3470617' apa: Kenter, T., Shambhu, A., Faghih-Naini, S., & Aizinger, V. (2021). Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA. Proceedings of the Platform for Advanced Scientific Computing Conference. https://doi.org/10.1145/3468267.3470617 bibtex: '@inproceedings{Kenter_Shambhu_Faghih-Naini_Aizinger_2021, title={Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA}, DOI={10.1145/3468267.3470617}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference}, publisher={ACM}, author={Kenter, Tobias and Shambhu, Adesh and Faghih-Naini, Sara and Aizinger, Vadym}, year={2021} }' chicago: Kenter, Tobias, Adesh Shambhu, Sara Faghih-Naini, and Vadym Aizinger. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” In Proceedings of the Platform for Advanced Scientific Computing Conference. ACM, 2021. https://doi.org/10.1145/3468267.3470617. ieee: 'T. Kenter, A. Shambhu, S. Faghih-Naini, and V. Aizinger, “Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA,” 2021, doi: 10.1145/3468267.3470617.' mla: Kenter, Tobias, et al. “Algorithm-Hardware Co-Design of a Discontinuous Galerkin Shallow-Water Model for a Dataflow Architecture on FPGA.” Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021, doi:10.1145/3468267.3470617. short: 'T. Kenter, A. Shambhu, S. Faghih-Naini, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference, ACM, 2021.' date_created: 2023-07-28T11:58:14Z date_updated: 2023-07-28T12:03:19Z department: - _id: '27' - _id: '518' doi: 10.1145/3468267.3470617 language: - iso: eng main_file_link: - open_access: '1' url: https://dl.acm.org/doi/pdf/10.1145/3468267.3470617 oa: '1' project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proceedings of the Platform for Advanced Scientific Computing Conference publication_status: published publisher: ACM quality_controlled: '1' status: public title: Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA type: conference user_id: '3145' year: '2021' ... --- _id: '20886' author: - first_name: Tobias full_name: Nickchen, Tobias last_name: Nickchen - first_name: Stefan full_name: Heindorf, Stefan last_name: Heindorf - first_name: Gregor full_name: Engels, Gregor last_name: Engels citation: ama: 'Nickchen T, Heindorf S, Engels G. Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts. In: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision. ; 2021:1994-2002.' apa: Nickchen, T., Heindorf, S., & Engels, G. (2021). Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts. In Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision (pp. 1994–2002). Hawaii. bibtex: '@inproceedings{Nickchen_Heindorf_Engels_2021, title={Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts}, booktitle={Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision}, author={Nickchen, Tobias and Heindorf, Stefan and Engels, Gregor}, year={2021}, pages={1994–2002} }' chicago: Nickchen, Tobias, Stefan Heindorf, and Gregor Engels. “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts.” In Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 1994–2002, 2021. ieee: T. Nickchen, S. Heindorf, and G. Engels, “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts,” in Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, Hawaii, 2021, pp. 1994–2002. mla: Nickchen, Tobias, et al. “Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts.” Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2021, pp. 1994–2002. short: 'T. Nickchen, S. Heindorf, G. Engels, in: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2021, pp. 1994–2002.' conference: end_date: 2021-09-01 location: Hawaii name: IEEE/CVF Winter Conference on Applications of Computer Vision start_date: 2021-05-01 date_created: 2021-01-07T15:32:45Z date_updated: 2022-01-06T06:54:41Z department: - _id: '66' - _id: '534' - _id: '624' - _id: '219' - _id: '27' language: - iso: eng page: 1994-2002 publication: Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision publication_status: published status: public title: Generating Physically Sound Training Data for Image Recognition of Additively Manufactured Parts type: conference user_id: '27340' year: '2021' ... --- _id: '46195' author: - first_name: Martin full_name: Karp, Martin last_name: Karp - first_name: Artur full_name: Podobas, Artur last_name: Podobas - first_name: Niclas full_name: Jansson, Niclas last_name: Jansson - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Philipp full_name: Schlatter, Philipp last_name: Schlatter - first_name: Stefano full_name: Markidis, Stefano last_name: Markidis citation: ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116' apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116' bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }' chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.' ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.' mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.' short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.' date_created: 2023-07-28T12:04:27Z date_updated: 2023-07-28T12:05:15Z department: - _id: '27' - _id: '518' doi: 10.1109/ipdps49936.2021.00116 language: - iso: eng publication: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) publication_status: published publisher: IEEE quality_controlled: '1' status: public title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection' type: conference user_id: '3145' year: '2021' ... --- _id: '29937' author: - first_name: Martin full_name: Karp, Martin last_name: Karp - first_name: Artur full_name: Podobas, Artur last_name: Podobas - first_name: Niclas full_name: Jansson, Niclas last_name: Jansson - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Philipp full_name: Schlatter, Philipp last_name: Schlatter - first_name: Stefano full_name: Markidis, Stefano last_name: Markidis citation: ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE; 2021. doi:10.1109/ipdps49936.2021.00116' apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P., & Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116' bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021, title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116}, booktitle={2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson, Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis, Stefano}, year={2021} }' chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” In 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.' ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.' mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021, doi:10.1109/ipdps49936.2021.00116.' short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S. Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS), IEEE, 2021.' date_created: 2022-02-21T14:26:37Z date_updated: 2024-01-22T09:59:13Z department: - _id: '27' - _id: '518' doi: 10.1109/ipdps49936.2021.00116 language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS) publication_status: published publisher: IEEE quality_controlled: '1' status: public title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection' type: conference user_id: '3145' year: '2021' ... --- _id: '32245' abstract: - lang: eng text: "Optical travelling wave antennas offer unique opportunities to control and\r\nselectively guide light into a specific direction which renders them as\r\nexcellent candidates for optical communication and sensing. These applications\r\nrequire state of the art engineering to reach optimized functionalities such as\r\nhigh directivity and radiation efficiency, low side lobe level, broadband and\r\ntunable capabilities, and compact design. In this work we report on the\r\nnumerical optimization of the directivity of optical travelling wave antennas\r\nmade from low-loss dielectric materials using full-wave numerical simulations\r\nin conjunction with a particle swarm optimization algorithm. The antennas are\r\ncomposed of a reflector and a director deposited on a glass substrate and an\r\nemitter placed in the feed gap between them serves as an internal source of\r\nexcitation. In particular, we analysed antennas with rectangular- and\r\nhorn-shaped directors made of either Hafnium dioxide or Silicon. The optimized\r\nantennas produce highly directional emission due to the presence of two\r\ndominant guided TE modes in the director in addition to leaky modes. These\r\nguided modes dominate the far-field emission pattern and govern the direction\r\nof the main lobe emission which predominately originates from the end facet of\r\nthe director. Our work also provides a comprehensive analysis of the modes,\r\nradiation patterns, parametric influences, and bandwidths of the antennas that\r\nhighlights their robust nature." author: - first_name: Henna full_name: Farheen, Henna last_name: Farheen - first_name: Till full_name: Leuteritz, Till last_name: Leuteritz - first_name: Stefan full_name: Linden, Stefan last_name: Linden - first_name: Viktor full_name: Myroshnychenko, Viktor last_name: Myroshnychenko - first_name: Jens full_name: Förstner, Jens last_name: Förstner citation: ama: Farheen H, Leuteritz T, Linden S, Myroshnychenko V, Förstner J. Optimization of optical waveguide antennas for directive emission of  light. arXiv:210602468. Published online 2021. apa: Farheen, H., Leuteritz, T., Linden, S., Myroshnychenko, V., & Förstner, J. (2021). Optimization of optical waveguide antennas for directive emission of  light. In arXiv:2106.02468. bibtex: '@article{Farheen_Leuteritz_Linden_Myroshnychenko_Förstner_2021, title={Optimization of optical waveguide antennas for directive emission of  light}, journal={arXiv:2106.02468}, author={Farheen, Henna and Leuteritz, Till and Linden, Stefan and Myroshnychenko, Viktor and Förstner, Jens}, year={2021} }' chicago: Farheen, Henna, Till Leuteritz, Stefan Linden, Viktor Myroshnychenko, and Jens Förstner. “Optimization of Optical Waveguide Antennas for Directive Emission of  Light.” ArXiv:2106.02468, 2021. ieee: H. Farheen, T. Leuteritz, S. Linden, V. Myroshnychenko, and J. Förstner, “Optimization of optical waveguide antennas for directive emission of  light,” arXiv:2106.02468. 2021. mla: Farheen, Henna, et al. “Optimization of Optical Waveguide Antennas for Directive Emission of  Light.” ArXiv:2106.02468, 2021. short: H. Farheen, T. Leuteritz, S. Linden, V. Myroshnychenko, J. Förstner, ArXiv:2106.02468 (2021). date_created: 2022-06-28T08:01:09Z date_updated: 2022-06-28T08:01:39Z department: - _id: '27' external_id: arxiv: - '2106.02468' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2106.02468 status: public title: Optimization of optical waveguide antennas for directive emission of light type: preprint user_id: '15278' year: '2021' ... --- _id: '32236' abstract: - lang: eng text: "The interaction between quantum light and matter is being intensively studied\r\nfor systems that are enclosed in high-$Q$ cavities which strongly enhance the\r\nlight-matter coupling. However, for many applications, cavities with lower\r\n$Q$-factors are preferred due to the increased spectral width of the cavity\r\nmode. Here, we investigate the interaction between quantum light and matter\r\nrepresented by a $\\Lambda$-type three-level system in lossy cavities, assuming\r\nthat cavity losses are the dominant loss mechanism. We demonstrate that cavity\r\nlosses lead to non-trivial steady states of the electronic occupations that can\r\nbe controlled by the loss rate and the initial statistics of the quantum\r\nfields. The mechanism of formation of such steady states can be understood on\r\nthe basis of the equations of motion. Analytical expressions for steady states\r\nand their numerical simulations are presented and discussed." author: - first_name: H. full_name: Rose, H. last_name: Rose - first_name: O. V. full_name: Tikhonova, O. V. last_name: Tikhonova - first_name: T. full_name: Meier, T. last_name: Meier - first_name: 'P. ' full_name: 'Sharapova, P. ' last_name: Sharapova citation: ama: Rose H, Tikhonova OV, Meier T, Sharapova P. Steady states of $Λ$-type three-level systems excited by quantum  light in lossy cavities. arXiv:210900842. Published online 2021. apa: Rose, H., Tikhonova, O. V., Meier, T., & Sharapova, P. (2021). Steady states of $Λ$-type three-level systems excited by quantum  light in lossy cavities. In arXiv:2109.00842. bibtex: '@article{Rose_Tikhonova_Meier_Sharapova_2021, title={Steady states of $Λ$-type three-level systems excited by quantum  light in lossy cavities}, journal={arXiv:2109.00842}, author={Rose, H. and Tikhonova, O. V. and Meier, T. and Sharapova, P. }, year={2021} }' chicago: Rose, H., O. V. Tikhonova, T. Meier, and P. Sharapova. “Steady States of $Λ$-Type Three-Level Systems Excited by Quantum  Light in Lossy Cavities.” ArXiv:2109.00842, 2021. ieee: H. Rose, O. V. Tikhonova, T. Meier, and P. Sharapova, “Steady states of $Λ$-type three-level systems excited by quantum  light in lossy cavities,” arXiv:2109.00842. 2021. mla: Rose, H., et al. “Steady States of $Λ$-Type Three-Level Systems Excited by Quantum  Light in Lossy Cavities.” ArXiv:2109.00842, 2021. short: H. Rose, O.V. Tikhonova, T. Meier, P. Sharapova, ArXiv:2109.00842 (2021). date_created: 2022-06-28T07:03:29Z date_updated: 2023-02-10T16:00:12Z department: - _id: '27' external_id: arxiv: - '2109.00842' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2109.00842 status: public title: Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities type: preprint user_id: '14931' year: '2021' ... --- _id: '32244' abstract: - lang: eng text: "We push the boundaries of electronic structure-based \\textit{ab-initio}\r\nmolecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise\r\nbarely reachable with classical force-field methods or novel neural network and\r\nmachine learning potentials. We achieve this breakthrough by combining\r\ninnovations in linear-scaling AIMD, efficient and approximate sparse linear\r\nalgebra, low and mixed-precision floating-point computation on GPUs, and a\r\ncompensation scheme for the errors introduced by numerical approximations. The\r\ncore of our work is the non-orthogonalized local submatrix method (NOLSM),\r\nwhich scales very favorably to massively parallel computing systems and\r\ntranslates large sparse matrix operations into highly parallel, dense matrix\r\noperations that are ideally suited to hardware accelerators. We demonstrate\r\nthat the NOLSM method, which is at the center point of each AIMD step, is able\r\nto achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision\r\ncorresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs." author: - first_name: Robert full_name: Schade, Robert last_name: Schade - first_name: Tobias full_name: Kenter, Tobias last_name: Kenter - first_name: Hossam full_name: Elgabarty, Hossam last_name: Elgabarty - first_name: Michael full_name: Lass, Michael last_name: Lass - first_name: Ole full_name: Schütt, Ole last_name: Schütt - first_name: Alfio full_name: Lazzaro, Alfio last_name: Lazzaro - first_name: Hans full_name: Pabst, Hans last_name: Pabst - first_name: Stephan full_name: Mohr, Stephan last_name: Mohr - first_name: Jürg full_name: Hutter, Jürg last_name: Hutter - first_name: Thomas D. full_name: Kühne, Thomas D. last_name: Kühne - first_name: Christian full_name: Plessl, Christian last_name: Plessl citation: ama: Schade R, Kenter T, Elgabarty H, et al. Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms. arXiv:210408245. Published online 2021. apa: Schade, R., Kenter, T., Elgabarty, H., Lass, M., Schütt, O., Lazzaro, A., Pabst, H., Mohr, S., Hutter, J., Kühne, T. D., & Plessl, C. (2021). Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms. In arXiv:2104.08245. bibtex: '@article{Schade_Kenter_Elgabarty_Lass_Schütt_Lazzaro_Pabst_Mohr_Hutter_Kühne_et al._2021, title={Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms}, journal={arXiv:2104.08245}, author={Schade, Robert and Kenter, Tobias and Elgabarty, Hossam and Lass, Michael and Schütt, Ole and Lazzaro, Alfio and Pabst, Hans and Mohr, Stephan and Hutter, Jürg and Kühne, Thomas D. and et al.}, year={2021} }' chicago: Schade, Robert, Tobias Kenter, Hossam Elgabarty, Michael Lass, Ole Schütt, Alfio Lazzaro, Hans Pabst, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021. ieee: R. Schade et al., “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms,” arXiv:2104.08245. 2021. mla: Schade, Robert, et al. “Towards Electronic Structure-Based Ab-Initio Molecular Dynamics  Simulations with Hundreds of Millions of Atoms.” ArXiv:2104.08245, 2021. short: R. Schade, T. Kenter, H. Elgabarty, M. Lass, O. Schütt, A. Lazzaro, H. Pabst, S. Mohr, J. Hutter, T.D. Kühne, C. Plessl, ArXiv:2104.08245 (2021). date_created: 2022-06-28T07:48:31Z date_updated: 2022-06-28T07:49:31Z department: - _id: '27' external_id: arxiv: - '2104.08245' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2104.08245 status: public title: Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms type: preprint user_id: '15278' year: '2021' ... --- _id: '27365' author: - first_name: Marius full_name: Meyer, Marius id: '40778' last_name: Meyer citation: ama: 'Meyer M. Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. In: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. ; 2021. doi:10.1145/3468044.3468058' apa: Meyer, M. (2021). Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks. Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies. https://doi.org/10.1145/3468044.3468058 bibtex: '@inproceedings{Meyer_2021, title={Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks}, DOI={10.1145/3468044.3468058}, booktitle={Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Meyer, Marius}, year={2021} }' chicago: Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” In Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021. https://doi.org/10.1145/3468044.3468058. ieee: 'M. Meyer, “Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks,” 2021, doi: 10.1145/3468044.3468058.' mla: Meyer, Marius. “Towards Performance Characterization of FPGAs in Context of HPC Using OpenCL Benchmarks.” Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021, doi:10.1145/3468044.3468058. short: 'M. Meyer, in: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021.' date_created: 2021-11-10T14:42:17Z date_updated: 2022-01-06T06:57:38Z department: - _id: '27' doi: 10.1145/3468044.3468058 language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies publication_status: published status: public title: Towards Performance Characterization of FPGAs in Context of HPC using OpenCL Benchmarks type: conference user_id: '40778' year: '2021' ... --- _id: '16898' abstract: - lang: eng text: "Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance computing resources. To perform these quantum-mechanical DFT\r\ncalculations on complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional cubic scaling methods are required. In this work, we\r\ntake up the idea of the submatrix method and apply it to the DFT computations\r\nin the software package CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed, large, sparse matrices into computations on\r\nlocal, much smaller and nearly dense matrices. This allows us to exploit the\r\nfull floating-point performance of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality and performance of our implementation\r\nand show how it can be accelerated with GPUs and FPGAs." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Robert full_name: Schade, Robert id: '75963' last_name: Schade orcid: 0000-0002-6268-539 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC). IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084' apa: Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K. Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084 bibtex: '@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA, USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084}, booktitle={Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140} }' chicago: 'Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” In Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society, 2020. https://doi.org/10.1109/SC41405.2020.00084.' ieee: 'M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.' mla: Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084. short: 'M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.' conference: location: Atlanta, GA, US name: 'SC20: International Conference for High Performance Computing, Networking, Storage and Analysis (SC)' date_created: 2020-04-28T14:44:21Z date_updated: 2023-08-02T14:55:59Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1109/SC41405.2020.00084 external_id: arxiv: - '2004.10811' language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/document/9355245 page: 1127-1140 place: Los Alamitos, CA, USA project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC) publisher: IEEE Computer Society quality_controlled: '1' status: public title: A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K type: conference user_id: '75963' year: '2020' ... --- _id: '21632' abstract: - lang: eng text: FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. author: - first_name: Marius full_name: Meyer, Marius id: '40778' last_name: Meyer - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007' apa: Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007 bibtex: '@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007}, booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and Plessl, Christian}, year={2020} }' chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007. ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.' mla: Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.” 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007. short: 'M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.' date_created: 2021-04-16T10:17:22Z date_updated: 2023-09-26T11:42:53Z department: - _id: '27' - _id: '518' doi: 10.1109/h2rc51942.2020.00007 keyword: - FPGA - OpenCL - High Level Synthesis - HPC benchmarking language: - iso: eng main_file_link: - url: https://ieeexplore.ieee.org/document/9306963 project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) publication_identifier: isbn: - '9781665415927' publication_status: published quality_controlled: '1' related_material: link: - description: Official repository of the benchmark suite on GitHub relation: supplementary_material url: https://github.com/pc2/HPCC_FPGA status: public title: Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite type: conference user_id: '15278' year: '2020' ... --- _id: '32242' abstract: - lang: eng text: "We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem: In each round, the learner selects an arm and determines a resource\r\nlimit. It then observes a corresponding (random) reward, provided the (random)\r\namount of consumed resources remains below the limit. Otherwise, the\r\nobservation is censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce a measure of regret, which incorporates the actual amount of\r\nallocated resources of each learning round as well as the optimality of\r\nrealizable rewards. Thus, to minimize regret, the learner needs to set a\r\nresource limit and choose an arm in such a way that the chance to realize a\r\nhigh reward within the predefined resource limit is high, while the resource\r\nlimit itself should be kept as low as possible. We derive the theoretical lower\r\nbound on the cumulative regret and propose a learning algorithm having a regret\r\nupper bound that matches the lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms straightforward extensions of standard\r\nmulti-armed bandit algorithms." author: - first_name: Viktor full_name: Bengs, Viktor last_name: Bengs - first_name: Eyke full_name: Hüllermeier, Eyke last_name: Hüllermeier citation: ama: Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources. arXiv:201100813. Published online 2020. apa: Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored Consumption of Resources. In arXiv:2011.00813. bibtex: '@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and Hüllermeier, Eyke}, year={2020} }' chicago: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020. ieee: V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption of Resources,” arXiv:2011.00813. 2020. mla: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption of Resources.” ArXiv:2011.00813, 2020. short: V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020). date_created: 2022-06-28T07:26:54Z date_updated: 2022-06-28T07:27:19Z department: - _id: '27' external_id: arxiv: - '2011.00813' language: - iso: eng project: - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: arXiv:2011.00813 status: public title: Multi-Armed Bandits with Censored Consumption of Resources type: preprint user_id: '15278' year: '2020' ... --- _id: '15478' abstract: - lang: eng text: Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS. author: - first_name: Paolo full_name: Gorlani, Paolo id: '72045' last_name: Gorlani - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020' apa: Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00020 bibtex: '@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl, Christian}, year={2019} }' chicago: Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE, 2019. https://doi.org/10.1109/ICFPT47387.2019.00020. ieee: P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2019. mla: Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020. short: 'P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2019.' conference: name: International Conference on Field-Programmable Technology (FPT) date_created: 2020-01-09T12:54:48Z date_updated: 2022-01-06T06:52:26Z ddc: - '004' department: - _id: '27' - _id: '518' doi: 10.1109/ICFPT47387.2019.00020 file: - access_level: closed content_type: application/pdf creator: plessl date_created: 2020-01-09T12:53:57Z date_updated: 2020-01-09T12:53:57Z file_id: '15479' file_name: gorlani19_fpt.pdf file_size: 250559 relation: main_file success: 1 file_date_updated: 2020-01-09T12:53:57Z has_accepted_license: '1' language: - iso: eng project: - _id: '33' grant_number: 01|H16005 name: HighPerMeshes - _id: '32' grant_number: PL 595/2-1 name: Performance and Efficiency in HPC with Custom Computing publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) publisher: IEEE quality_controlled: '1' status: public title: OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs type: conference user_id: '3145' year: '2019' ... --- _id: '22' abstract: - lang: eng text: This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation. author: - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller citation: ama: 'Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8' apa: 'Keller, A. (2018). A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) (Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8' bibtex: '@inproceedings{Keller_2018, series={Lecture Notes in Computer Science}, title={A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8}, booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture Notes in Computer Science} }' chicago: Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai, 10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8. ieee: A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151. mla: Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51, doi:10.1007/978-3-319-77398-8_8. short: 'A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp. 132–151.' conference: end_date: 2017-06-02 location: Orlando, FL, USA name: 21st Workshop on Job Scheduling Strategies for Parallel Processing start_date: 2017-06-02 date_created: 2017-07-25T14:54:08Z date_updated: 2022-01-06T06:55:22Z department: - _id: '27' doi: 10.1007/978-3-319-77398-8_8 editor: - first_name: D. full_name: Klusáček, D. last_name: Klusáček - first_name: W. full_name: Cirne, W. last_name: Cirne - first_name: N. full_name: Desai, N. last_name: Desai intvolume: ' 10773' keyword: - Scheduling Planning Mapping Workload management language: - iso: eng page: 132-151 publication: Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP) publication_identifier: isbn: - 978-3-319-77398-8 - 978-3-319-77397-1 publication_status: published publisher: Springer series_title: Lecture Notes in Computer Science status: public title: A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems type: conference user_id: '15274' volume: 10773 year: '2018' ... --- _id: '1590' abstract: - lang: eng text: "We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Stephan full_name: Mohr, Stephan last_name: Mohr - first_name: Hendrik full_name: Wiebeler, Hendrik last_name: Wiebeler - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. In: Proc. Platform for Advanced Scientific Computing (PASC) Conference. ACM; 2018. doi:10.1145/3218176.3218231' apa: Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference. Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland. https://doi.org/10.1145/3218176.3218231 bibtex: '@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY, USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231}, booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference}, publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik and Kühne, Thomas and Plessl, Christian}, year={2018} }' chicago: 'Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.' ieee: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices,” presented at the Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.' mla: Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231. short: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.' conference: end_date: 2018-07-04 location: Basel, Switzerland name: Platform for Advanced Scientific Computing Conference (PASC) start_date: 2018-07-02 date_created: 2018-03-22T10:53:01Z date_updated: 2023-09-26T11:48:12Z department: - _id: '27' - _id: '518' - _id: '304' doi: 10.1145/3218176.3218231 external_id: arxiv: - '1710.10899' keyword: - approximate computing - linear algebra - matrix inversion - matrix p-th roots - numeric algorithm - parallel computing language: - iso: eng place: New York, NY, USA project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proc. Platform for Advanced Scientific Computing (PASC) Conference publication_identifier: isbn: - 978-1-4503-5891-0/18/07 publisher: ACM quality_controlled: '1' status: public title: A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices type: conference user_id: '15278' year: '2018' ... --- _id: '1204' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534' apa: Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534 bibtex: '@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP). ACM, 2018. https://doi.org/10.1145/3178487.3178534. ieee: 'H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.' mla: Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534. short: 'H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.' date_created: 2018-03-08T14:45:18Z date_updated: 2023-09-26T11:47:23Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1145/3178487.3178534 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T14:43:37Z date_updated: 2018-11-02T14:43:37Z file_id: '5281' file_name: p417-riebler.pdf file_size: 447769 relation: main_file success: 1 file_date_updated: 2018-11-02T14:43:37Z has_accepted_license: '1' keyword: - htrop language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP) publication_identifier: isbn: - '9781450349826' publication_status: published publisher: ACM quality_controlled: '1' status: public title: Automated Code Acceleration Targeting Heterogeneous OpenCL Devices type: conference user_id: '15278' year: '2018' ... --- _id: '1588' abstract: - lang: eng text: The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gopinath full_name: Mahale, Gopinath last_name: Mahale - first_name: Samer full_name: Alhaddad, Samer id: '42456' last_name: Alhaddad - first_name: Yevgen full_name: Grynko, Yevgen id: '26059' last_name: Grynko - first_name: Christian full_name: Schmitt, Christian last_name: Schmitt - first_name: Ayesha full_name: Afzal, Ayesha last_name: Afzal - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018. doi:10.1109/FCCM.2018.00037' apa: Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig, F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037 bibtex: '@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018, title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037}, booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank and Förstner, Jens and Plessl, Christian}, year={2018} }' chicago: Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037. ieee: 'T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi: 10.1109/FCCM.2018.00037.' mla: Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037. short: 'T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig, J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), IEEE, 2018.' conference: name: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) date_created: 2018-03-22T10:48:01Z date_updated: 2023-09-26T11:47:52Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '61' doi: 10.1109/FCCM.2018.00037 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T14:45:05Z date_updated: 2018-11-02T14:45:05Z file_id: '5282' file_name: 08457652.pdf file_size: 269130 relation: main_file success: 1 file_date_updated: 2018-11-02T14:45:05Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng project: - _id: '33' grant_number: 01|H16005A name: HighPerMeshes - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE quality_controlled: '1' status: public title: OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes type: conference user_id: '15278' year: '2018' ... --- _id: '1592' abstract: - lang: eng text: Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844' apa: Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844 bibtex: '@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }' chicago: Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844. ieee: 'T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.' mla: Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844. short: 'T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.' date_created: 2018-03-22T11:10:23Z date_updated: 2023-09-26T13:24:38Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '61' doi: 10.23919/FPL.2017.8056844 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:02:28Z date_updated: 2018-11-02T15:02:28Z file_id: '5291' file_name: 08056844.pdf file_size: 230235 relation: main_file success: 1 file_date_updated: 2018-11-02T15:02:28Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '33' grant_number: 01|H16005A name: HighPerMeshes - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Flexible FPGA design for FDTD using OpenCL type: conference user_id: '15278' year: '2017' ... --- _id: '19' abstract: - lang: eng text: "Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Dominik full_name: Leibenger, Dominik last_name: Leibenger - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11' apa: Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11 bibtex: '@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }' chicago: Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11. ieee: M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016. mla: Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11. short: 'M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.' date_created: 2017-07-25T14:36:16Z date_updated: 2022-01-06T06:53:56Z department: - _id: '27' - _id: '518' doi: 10.1109/lcn.2016.11 keyword: - access control - distributed version control systems - mercurial - peer-to-peer - convergent encryption - confidentiality - authenticity language: - iso: eng publication: Proc. 41st Conference on Local Computer Networks (LCN) publication_identifier: isbn: - 978-1-5090-2054-6 publication_status: published publisher: IEEE status: public title: Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension type: conference user_id: '24135' year: '2016' ... --- _id: '24' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.' apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016. mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.' date_created: 2017-07-26T15:00:43Z date_updated: 2023-09-26T13:26:17Z ddc: - '004' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: kenter date_created: 2018-11-14T12:38:45Z date_updated: 2018-11-14T12:38:45Z file_id: '5602' file_name: paper_26.pdf file_size: 129552 relation: main_file success: 1 file_date_updated: 2018-11-14T12:38:45Z has_accepted_license: '1' language: - iso: eng project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) quality_controlled: '1' status: public title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL type: conference user_id: '15278' year: '2016' ... --- _id: '34' author: - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz - first_name: Julian full_name: Eckstein, Julian last_name: Eckstein - first_name: Kathrin full_name: Flaßkamp, Kathrin last_name: Flaßkamp - first_name: Patrick full_name: Friedel, Patrick last_name: Friedel - first_name: Christian full_name: Horenkamp, Christian last_name: Horenkamp - first_name: Ulrich full_name: Köhler, Ulrich last_name: Köhler - first_name: Sina full_name: Ober-Blöbaum, Sina last_name: Ober-Blöbaum - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Sebastian full_name: Tiemeyer, Sebastian last_name: Tiemeyer citation: ama: 'Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87' apa: 'Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87' bibtex: '@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }' chicago: 'Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.' ieee: M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641. mla: Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87. short: 'M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.' date_created: 2017-07-26T15:25:33Z date_updated: 2022-01-06T06:59:14Z department: - _id: '27' - _id: '101' doi: 10.1007/978-3-319-23413-7_87 intvolume: ' 22' page: 633-641 place: Cham publication: Progress in Industrial Mathematics at ECMI publication_identifier: issn: - 2212-0173 publisher: Springer International Publishing series_title: Mathematics in Industry status: public title: Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control type: conference user_id: '24135' volume: 22 year: '2016' ... --- _id: '171' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.' apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC). bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016. ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016. mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016. short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.' date_created: 2017-10-17T12:41:25Z date_updated: 2023-09-26T13:27:21Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:39:46Z date_updated: 2018-03-21T12:39:46Z file_id: '1538' file_name: 171-plessl16_fpl_wrc.pdf file_size: 54421 relation: main_file success: 1 file_date_updated: 2018-03-21T12:39:46Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Workshop on Reconfigurable Computing (WRC) quality_controlled: '1' status: public title: Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) type: conference user_id: '15278' year: '2016' ... --- _id: '168' abstract: - lang: eng text: The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.' apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917. bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }' chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016. ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917. mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17. short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.' date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:27:00Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:41:55Z date_updated: 2018-03-21T12:41:55Z file_id: '1541' file_name: 168-07459438.pdf file_size: 261356 relation: main_file success: 1 file_date_updated: 2018-03-21T12:41:55Z has_accepted_license: '1' language: - iso: eng page: 912-917 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center type: conference user_id: '15278' year: '2016' ... --- _id: '25' author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.' apa: Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC). bibtex: '@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }' chicago: Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016. ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016. mla: Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016. short: 'M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.' date_created: 2017-07-26T15:02:20Z date_updated: 2023-09-26T13:25:17Z department: - _id: '27' - _id: '518' - _id: '304' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Workshop on Approximate Computing (AC) quality_controlled: '1' status: public title: Using Approximate Computing in Scientific Codes type: conference user_id: '15278' year: '2016' ... --- _id: '31' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Ettore M. G. full_name: Trainiti, Ettore M. G. last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. ieee: H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016. mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.' date_created: 2017-07-26T15:16:31Z date_updated: 2023-09-26T13:25:59Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: deffel date_created: 2019-01-11T11:56:55Z date_updated: 2019-01-11T11:56:55Z file_id: '6626' file_name: wrc_upb_polimi_final.pdf file_size: 394563 relation: main_file success: 1 file_date_updated: 2019-01-11T11:56:55Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '138' abstract: - lang: eng text: Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: 'Ettore M. G. ' full_name: 'Trainiti, Ettore M. G. ' last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Emanuele full_name: Del Sozzo, Emanuele last_name: Del Sozzo - first_name: 'Marco D. ' full_name: 'Santambrogio, Marco D. ' last_name: Santambrogio - first_name: Christina full_name: Bolchini, Christina last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545 bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545. ieee: 'H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.' mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.' date_created: 2017-10-17T12:41:18Z date_updated: 2023-09-26T13:28:11Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1109/RTSI.2016.7740545 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:01:09Z date_updated: 2018-03-21T13:01:09Z file_id: '1560' file_name: 138-07740545.pdf file_size: 184334 relation: main_file success: 1 file_date_updated: 2018-03-21T13:01:09Z has_accepted_license: '1' language: - iso: eng page: 1-5 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) publisher: IEEE quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '303' abstract: - lang: eng text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.' apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }' chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015. mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.' date_created: 2017-10-17T12:41:51Z date_updated: 2023-09-26T13:29:59Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' external_id: arxiv: - '1412.3906' file: - access_level: open_access content_type: application/pdf creator: florida date_created: 2018-03-20T07:46:46Z date_updated: 2019-08-01T09:10:44Z file_id: '1442' file_name: 303-plessl15_adapt.pdf file_size: 1176620 relation: main_file file_date_updated: 2019-08-01T09:10:44Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) quality_controlled: '1' status: public title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores type: conference user_id: '15278' year: '2015' ... --- _id: '1773' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: J. full_name: T. Anderson, J. last_name: T. Anderson - first_name: A. full_name: Borga, A. last_name: Borga - first_name: H. full_name: Boterenbrood, H. last_name: Boterenbrood - first_name: H. full_name: Chen, H. last_name: Chen - first_name: K. full_name: Chen, K. last_name: Chen - first_name: G. full_name: Drake, G. last_name: Drake - first_name: D. full_name: Francis, D. last_name: Francis - first_name: B. full_name: Gorini, B. last_name: Gorini - first_name: F. full_name: Lanni, F. last_name: Lanni - first_name: Giovanna full_name: Lehmann-Miotto, Giovanna last_name: Lehmann-Miotto - first_name: L. full_name: Levinson, L. last_name: Levinson - first_name: J. full_name: Narevicius, J. last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A. full_name: Roich, A. last_name: Roich - first_name: S. full_name: Ryu, S. last_name: Ryu - first_name: F. full_name: P. Schreuder, F. last_name: P. Schreuder - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J. full_name: Vermeulen, J. last_name: Vermeulen - first_name: J. full_name: Zhang, J. last_name: Zhang citation: ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824' apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824 bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }' chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824. ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.' mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824. short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.' date_created: 2018-03-23T14:09:33Z date_updated: 2023-09-26T13:31:01Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/2675743.2771824 language: - iso: eng publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) publisher: ACM quality_controlled: '1' status: public title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm type: conference user_id: '15278' year: '2015' ... --- _id: '238' abstract: - lang: eng text: In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124' apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124 bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }' chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124. ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.' mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124. short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.' date_created: 2017-10-17T12:41:38Z date_updated: 2023-09-26T13:31:44Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.7873/DATE.2015.1124 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T10:29:49Z date_updated: 2018-03-21T10:29:49Z file_id: '1500' file_name: 238-plessl15_date.pdf file_size: 380552 relation: main_file success: 1 file_date_updated: 2018-03-21T10:29:49Z has_accepted_license: '1' language: - iso: eng page: 1078-1083 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Transparent offloading of computational hotspots from binary code to Xeon Phi type: conference user_id: '15278' year: '2015' ... --- _id: '439' abstract: - lang: eng text: Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509' apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509 bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509. ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.' mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509. short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:17Z date_updated: 2023-09-26T13:37:02Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032509 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:29:52Z date_updated: 2018-03-16T11:29:52Z file_id: '1353' file_name: 439-plessl14a_reconfig.pdf file_size: 557362 relation: main_file success: 1 file_date_updated: 2018-03-16T11:29:52Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Deferring Accelerator Offloading Decisions to Application Runtime type: conference user_id: '15278' year: '2014' ... --- _id: '406' abstract: - lang: eng text: Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535' apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535 bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.' mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535. short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:11Z date_updated: 2023-09-26T13:36:40Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032535 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:37:42Z date_updated: 2018-03-16T11:37:42Z file_id: '1366' file_name: 406-ReConFig14.pdf file_size: 932852 relation: main_file success: 1 file_date_updated: 2018-03-16T11:37:42Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching type: conference user_id: '15278' year: '2014' ... --- _id: '1781' abstract: - lang: eng text: In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment. author: - first_name: Tobias full_name: Steinle, Tobias last_name: Steinle - first_name: Jadran full_name: Vrabec, Jadran last_name: Vrabec - first_name: Andrea full_name: Walther, Andrea last_name: Walther citation: ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19' apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19 bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }' chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19. ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243. mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19. short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.' date_created: 2018-03-26T13:47:16Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '104' - _id: '155' doi: 10.1007/978-3-319-09063-4_19 editor: - first_name: Hans Georg full_name: Bock, Hans Georg last_name: Bock - first_name: Xuan Phu full_name: Hoang, Xuan Phu last_name: Hoang - first_name: Rolf full_name: Rannacher, Rolf last_name: Rannacher - first_name: Johannes P. full_name: Schlöder, Johannes P. last_name: Schlöder page: 233-243 publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) publication_identifier: isbn: - 978-3-319-09063-4 publisher: Springer International Publishing status: public title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres type: conference user_id: '24135' year: '2014' ... --- _id: '1782' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2' apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2' bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }' chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.' ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25. mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2. short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.' date_created: 2018-03-26T13:50:37Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-319-09165-5_2 issue: '8427' page: 14-25 place: Switzerland publication: Proc. Conf. on Computers and Games (CG) publisher: Springer series_title: Lecture Notes in Computer Science status: public title: On Semeai Detection in Monte-Carlo Go type: conference user_id: '24135' year: '2014' ... --- _id: '388' abstract: - lang: eng text: In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13' apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13' bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.' ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.' mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.' short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.' date_created: 2017-10-17T12:42:07Z date_updated: 2023-09-26T13:34:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_13 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:02:02Z date_updated: 2018-03-20T07:02:02Z file_id: '1387' file_name: 388-plessl14_arc.pdf file_size: 330193 relation: main_file success: 1 file_date_updated: 2018-03-20T07:02:02Z has_accepted_license: '1' intvolume: ' 8405' language: - iso: eng page: 144-155 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)' publisher: Springer International Publishing quality_controlled: '1' series_title: Lecture Notes in Computer Science (LNCS) status: public title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer type: conference user_id: '15278' volume: 8405 year: '2014' ... --- _id: '377' abstract: - lang: eng text: In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67' apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67 bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }' chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67. ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.' mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67. short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.' date_created: 2017-10-17T12:42:05Z date_updated: 2023-09-26T13:33:50Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FCCM.2014.67 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:14:20Z date_updated: 2018-03-20T07:14:20Z file_id: '1397' file_name: 377-FCCM14.pdf file_size: 1003907 relation: main_file success: 1 file_date_updated: 2018-03-20T07:14:20Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 222-229 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE quality_controlled: '1' status: public title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs type: conference user_id: '15278' year: '2014' ... --- _id: '1778' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Pogliani, Marcello last_name: Pogliani - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27' apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27' bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }' chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.' ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.' mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.' short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.' date_created: 2018-03-26T13:40:14Z date_updated: 2023-09-26T13:35:40Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISPA.2014.27 language: - iso: eng page: 142-149 project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) publisher: IEEE quality_controlled: '1' status: public title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach' type: conference user_id: '15278' year: '2014' ... --- _id: '1780' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Copolla, Marcello last_name: Copolla - first_name: Karim full_name: Djafarian, Karim last_name: Djafarian - first_name: George full_name: Koranaros, George last_name: Koranaros - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Michele full_name: Paolino, Michele last_name: Paolino - first_name: Oliver full_name: Pell, Oliver last_name: Pell - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38' apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38' bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }' chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.' ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.' mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.' short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.' date_created: 2018-03-26T13:45:35Z date_updated: 2023-09-26T13:36:20Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_38 language: - iso: eng project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)' publisher: Springer quality_controlled: '1' status: public title: 'SAVE: Towards efficient resource management in heterogeneous system architectures' type: conference user_id: '15278' year: '2014' ... --- _id: '1788' author: - first_name: Petra full_name: Berenbrink, Petra last_name: Berenbrink - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tom full_name: Friedetzky, Tom last_name: Friedetzky - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Lars full_name: Nagel, Lars last_name: Nagel citation: ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148' apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L. (2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148 bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Meister, Dirk and Nagel, Lars}, year={2013} }' chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148. ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013. mla: Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013, doi:10.1109/IPDPSW.2013.148. short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.' date_created: 2018-03-26T14:52:56Z date_updated: 2022-01-06T06:53:22Z department: - _id: '27' doi: 10.1109/IPDPSW.2013.148 publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) publisher: IEEE status: public title: Distributing Storage in Cloud Environments type: conference user_id: '24135' year: '2013' ... --- _id: '1793' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tim full_name: Süß, Tim last_name: Süß citation: ama: 'Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST). USENIX Association; 2013:175-182.' apa: Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In Proc. USENIX Conference on File and Storage Technologies (FAST) (pp. 175–182). USENIX Association. bibtex: '@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }' chicago: Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage Technologies (FAST), 175–82. USENIX Association, 2013. ieee: D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST), 2013, pp. 175–182. mla: Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–82. short: 'D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.' date_created: 2018-03-26T15:16:03Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' page: 175-182 publication: Proc. USENIX Conference on File and Storage Technologies (FAST) publisher: USENIX Association status: public title: File Recipe Compression in Data Deduplication Systems type: conference user_id: '24135' year: '2013' ... --- _id: '1786' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530' apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530 bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530}, booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013} }' chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530. ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications Conf. (SUI), 2013. mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530. short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications Conf. (SUI), IEEE, 2013.' date_created: 2018-03-26T14:48:53Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1109/SIU.2013.6531530 publication: Proc. IEEE Signal Processing and Communications Conf. (SUI) publisher: IEEE status: public title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm type: conference user_id: '24135' year: '2013' ... --- _id: '528' abstract: - lang: eng text: Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394' apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394 bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }' chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 386–89. IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394. ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.' mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394. short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.' date_created: 2017-10-17T12:42:35Z date_updated: 2023-09-26T13:37:35Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FPT.2013.6718394 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:36:08Z date_updated: 2018-03-15T10:36:08Z file_id: '1294' file_name: 528-plessl13_fpt.pdf file_size: 822680 relation: main_file success: 1 file_date_updated: 2018-03-15T10:36:08Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 386-389 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '13' name: SFB 901 - Subproject C1 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) publisher: IEEE quality_controlled: '1' status: public title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES type: conference user_id: '15278' year: '2013' ... --- _id: '1784' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Viktor full_name: Gottfried, Viktor last_name: Gottfried - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97. doi:10.1109/NAS.2013.18' apa: 'Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/NAS.2013.18' bibtex: '@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers}, DOI={10.1109/NAS.2013.18}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor and Brinkmann, André}, year={2013}, pages={88–97} }' chicago: 'Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.' ieee: 'J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2013, pp. 88–97.' mla: 'Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.' short: 'J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington DC, USA, 2013, pp. 88–97.' date_created: 2018-03-26T14:43:38Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' doi: 10.1109/NAS.2013.18 page: 88-97 place: Washington DC, USA publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) publisher: IEEE Computer Society status: public title: 'MCD: Overcoming the Data Download Bottleneck in Data Centers' type: conference user_id: '24135' year: '2013' ... --- _id: '505' abstract: - lang: eng text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Peter full_name: Kling, Peter last_name: Kling - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Friedhelm full_name: Meyer auf der Heide, Friedhelm id: '15523' last_name: Meyer auf der Heide citation: ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232' apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232' bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232}, booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide, Friedhelm}, year={2013} }' chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.' ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.' mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.' short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in: Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013.' date_created: 2017-10-17T12:42:30Z date_updated: 2023-09-26T13:38:20Z ddc: - '040' department: - _id: '63' - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISORC.2013.6913232 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T13:38:56Z date_updated: 2018-03-15T13:38:56Z file_id: '1308' file_name: 505-Plessl13_seus.pdf file_size: 1040834 relation: main_file success: 1 file_date_updated: 2018-03-15T13:38:56Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS) publisher: IEEE quality_controlled: '1' status: public title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services' type: conference user_id: '15278' year: '2013' ... --- _id: '1787' author: - first_name: Tim full_name: Suess, Tim last_name: Suess - first_name: Andrew full_name: Schoenrock, Andrew last_name: Schoenrock - first_name: Sebastian full_name: Meisner, Sebastian last_name: Meisner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136' apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136 bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington, DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer}, DOI={10.1109/IPDPSW.2013.136}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)}, publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }' chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington, DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.' ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.' mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136. short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society, Washington, DC, USA, 2013, pp. 64–73.' date_created: 2018-03-26T14:51:05Z date_updated: 2023-09-26T13:38:05Z department: - _id: '27' - _id: '518' - _id: '78' - _id: '63' doi: 10.1109/IPDPSW.2013.136 language: - iso: eng page: 64-73 place: Washington, DC, USA project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW) publication_identifier: isbn: - 978-0-7695-4979-8 publisher: IEEE Computer Society quality_controlled: '1' status: public title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer type: conference user_id: '15278' year: '2013' ... --- _id: '2107' author: - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Martin full_name: Kruse, Martin last_name: Kruse - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Bernd full_name: Schuller, Bernd last_name: Schuller - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Andreas full_name: Zink, Andreas last_name: Zink citation: ama: 'Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for Computational Workflows. In: Proc. UNICORE Summit. ; 2012.' apa: Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing, S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows. In Proc. UNICORE Summit. bibtex: '@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc. UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012} }' chicago: Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway for Computational Workflows.” In Proc. UNICORE Summit, 2012. ieee: R. Grunzke et al., “A Data Driven Science Gateway for Computational Workflows,” in Proc. UNICORE Summit, 2012. mla: Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.” Proc. UNICORE Summit, 2012. short: 'R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P. Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.' date_created: 2018-03-29T15:06:46Z date_updated: 2022-01-06T06:54:44Z department: - _id: '27' - _id: '518' publication: Proc. UNICORE Summit status: public title: A Data Driven Science Gateway for Computational Workflows type: conference user_id: '24135' year: '2012' ... --- _id: '2178' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke citation: ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In: Proceedings of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.' apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving the International Molecular Simulation Community. In Proceedings of Science (Vol. PoS(EGICF12-EMITC2)050). bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={A Science Gateway Getting Ready for Serving the International Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }' chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In Proceedings of Science, Vol. PoS(EGICF12-EMITC2)050, 2012. ieee: S. Gesing et al., “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community,” in Proceedings of Science, 2012, vol. PoS(EGICF12-EMITC2)050. mla: Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050, 2012. short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proceedings of Science, 2012.' date_created: 2018-04-03T09:15:35Z date_updated: 2022-01-06T06:55:13Z department: - _id: '27' publication: Proceedings of Science status: public title: A Science Gateway Getting Ready for Serving the International Molecular Simulation Community type: conference user_id: '24135' volume: PoS(EGICF12-EMITC2)050 year: '2012' ... --- _id: '2099' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Michael full_name: Kuhn, Michael last_name: Kuhn - first_name: Julian full_name: Kunkel, Julian last_name: Kunkel - first_name: Toni full_name: Cortes, Toni last_name: Cortes citation: ama: 'Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing (SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14' apa: 'Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes, T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int. Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer Society. https://doi.org/10.1109/SC.2012.14' bibtex: '@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems}, DOI={10.1109/SC.2012.14}, booktitle={Proc. Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian and Cortes, Toni}, year={2012}, pages={7:1-7:11} }' chicago: 'Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel, and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc. Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer Society, 2012. https://doi.org/10.1109/SC.2012.14.' ieee: D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on Supercomputing (SC), 2012, pp. 7:1-7:11. mla: Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.” Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp. 7:1-7:11, doi:10.1109/SC.2012.14. short: 'D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in: Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos, CA, USA, 2012, pp. 7:1-7:11.' date_created: 2018-03-29T14:41:55Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/SC.2012.14 page: 7:1-7:11 place: Los Alamitos, CA, USA publication: Proc. Int. Conf. on Supercomputing (SC) publisher: IEEE Computer Society status: public title: A Study on Data Deduplication in HPC Storage Systems type: conference user_id: '24135' year: '2012' ... --- _id: '2103' author: - first_name: Martin full_name: Wistuba, Martin last_name: Wistuba - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143' apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143 bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143}, booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE}, author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012}, pages={91–99} }' chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143. ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence and Games (CIG), 2012, pp. 91–99. mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143. short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.' date_created: 2018-03-29T14:59:35Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/CIG.2012.6374143 page: 91-99 publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG) publisher: IEEE status: public title: Comparison of Bayesian Move Prediction Systems for Computer Go type: conference user_id: '24135' year: '2012' ... --- _id: '2106' abstract: - lang: eng text: "Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view." author: - first_name: Björn full_name: Meyer, Björn last_name: Meyer - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: 'Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370' apa: Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370 bibtex: '@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }' chicago: Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370. ieee: 'B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.' mla: Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370. short: 'B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.' conference: name: 22nd International Conference on Field Programmable Logic and Applicaitons (FPL) date_created: 2018-03-29T15:04:25Z date_updated: 2023-09-26T13:39:13Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '15' - _id: '78' doi: 10.1109/FPL.2012.6339370 file: - access_level: closed content_type: application/pdf creator: fossie date_created: 2019-02-13T09:04:46Z date_updated: 2019-02-13T09:04:46Z file_id: '7638' file_name: 2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf file_size: 2148787 relation: main_file success: 1 file_date_updated: 2019-02-13T09:04:46Z has_accepted_license: '1' keyword: - funding-upb-forschungspreis - funding-maxup - tet_topic_hpc language: - iso: eng page: 189-196 publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? type: conference user_id: '15278' year: '2012' ... --- _id: '1789' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sascha full_name: Effert, Sascha last_name: Effert citation: ama: 'Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380' apa: Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380 bibtex: '@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha}, year={2012}, pages={1–12} }' chicago: Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380. ieee: J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2012, pp. 1–12. mla: Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12, doi:10.1109/MSST.2012.6232380. short: 'J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.' date_created: 2018-03-26T15:12:01Z date_updated: 2022-01-06T06:53:22Z department: - _id: '27' doi: 10.1109/MSST.2012.6232380 page: 1-12 publication: Proc. Symp. on Mass Storage Systems and Technologies (MSST) publisher: IEEE status: public title: Design of an exact data deduplication cluster type: conference user_id: '24135' year: '2012' ... --- _id: '615' abstract: - lang: eng text: Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416745' apa: Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416745 bibtex: '@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }' chicago: Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745. ieee: 'M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416745.' mla: Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745. short: 'M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:51Z date_updated: 2023-09-26T13:42:26Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416745 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T06:48:32Z date_updated: 2018-03-15T06:48:32Z file_id: '1246' file_name: 615-ReConFig12_01.pdf file_size: 730144 relation: main_file success: 1 file_date_updated: 2018-03-15T06:48:32Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators type: conference user_id: '15278' year: '2012' ... --- _id: '2098' author: - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: Tim full_name: Hartung, Tim last_name: Hartung - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34' apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2 Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34' bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2 Split Block Device}, DOI={10.1109/ICPADS.2012.34}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and Brinkmann, André}, year={2012}, pages={181–188} }' chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB: Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.' ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2012, pp. 181–188.' mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88, doi:10.1109/ICPADS.2012.34.' short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.' date_created: 2018-03-29T14:40:04Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/ICPADS.2012.34 page: 181-188 publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) publisher: IEEE status: public title: 'ESB: Ext2 Split Block Device' type: conference user_id: '24135' year: '2012' ... --- _id: '612' abstract: - lang: eng text: While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA. author: - first_name: Christoph full_name: Rüthing, Christoph last_name: Rüthing - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562. doi:10.1109/FPL.2012.6339370' apa: Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–562. https://doi.org/10.1109/FPL.2012.6339370 bibtex: '@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }' chicago: Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370. ieee: 'C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.' mla: Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62, doi:10.1109/FPL.2012.6339370. short: 'C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.' date_created: 2017-10-17T12:42:51Z date_updated: 2023-09-26T13:42:03Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FPL.2012.6339370 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T06:49:03Z date_updated: 2018-03-15T06:49:03Z file_id: '1247' file_name: 612-ruething_fpl12.pdf file_size: 202923 relation: main_file success: 1 file_date_updated: 2018-03-15T06:49:03Z has_accepted_license: '1' language: - iso: eng page: 559-562 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs type: conference user_id: '15278' year: '2012' ... --- _id: '2100' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG). ; 2012.' apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive blind signal separation algorithm. In Int. Architecture and Engineering Symp. (ARCHENG). bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order convolutive blind signal separation algorithm}, booktitle={Int. Architecture and Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012} }' chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering Symp. (ARCHENG), 2012. ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive blind signal separation algorithm,” in Int. Architecture and Engineering Symp. (ARCHENG), 2012. mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp. (ARCHENG), 2012. short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG), 2012.' date_created: 2018-03-29T14:43:18Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' publication: Int. Architecture and Engineering Symp. (ARCHENG) status: public title: FPGA implementation of a second-order convolutive blind signal separation algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2097' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125' apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125 bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140} }' chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012. https://doi.org/10.1109/FPT.2012.6412125. ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable Technology (ICFPT), 2012, pp. 135–140. mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125. short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–140.' date_created: 2018-03-29T14:34:48Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' - _id: '78' doi: 10.1109/FPT.2012.6412125 page: 135-140 publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT) publisher: IEEE Computer Society status: public title: FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm type: conference user_id: '24135' year: '2012' ... --- _id: '2104' author: - first_name: Tobias full_name: Schlemmer, Tobias last_name: Schlemmer - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: 'Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.' apa: Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn, R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways via Virtual Organizations. In Proc. EGI Technical Forum. bibtex: '@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012, title={Generic User Management for Science Gateways via Virtual Organizations}, booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke, Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn, Ralph and Kohlbacher, Oliver}, year={2012} }' chicago: Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer, Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum, 2012. ieee: T. Schlemmer et al., “Generic User Management for Science Gateways via Virtual Organizations,” in Proc. EGI Technical Forum, 2012. mla: Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via Virtual Organizations.” Proc. EGI Technical Forum, 2012. short: 'T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.' date_created: 2018-03-29T15:00:48Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' publication: Proc. EGI Technical Forum status: public title: Generic User Management for Science Gateways via Virtual Organizations type: conference user_id: '24135' year: '2012' ... --- _id: '609' abstract: - lang: eng text: Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS). ; 2012:8-9.' apa: Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9. bibtex: '@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }' chicago: Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 8–9, 2012. ieee: M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. mla: Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9. short: 'M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.' date_created: 2017-10-17T12:42:50Z date_updated: 2023-09-26T13:41:36Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:14:17Z date_updated: 2018-03-15T08:14:17Z file_id: '1249' file_name: 609-happe12_fpl_awareness.pdf file_size: 146789 relation: main_file success: 1 file_date_updated: 2018-03-15T08:14:17Z has_accepted_license: '1' language: - iso: eng page: 8-9 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS) quality_controlled: '1' status: public title: Hardware/Software Platform for Self-aware Compute Nodes type: conference user_id: '15278' year: '2012' ... --- _id: '2105' author: - first_name: Giuseppe full_name: Congiu, Giuseppe last_name: Congiu - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Sai full_name: Narasimhamurthy, Sai last_name: Narasimhamurthy - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS). IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16' apa: 'Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012). One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16' bibtex: '@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services}, DOI={10.1109/ClusterW.2012.16}, booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }' chicago: 'Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” In Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.' ieee: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,” in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), 2012, pp. 16–24.' mla: 'Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24, doi:10.1109/ClusterW.2012.16.' short: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24.' date_created: 2018-03-29T15:02:15Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/ClusterW.2012.16 page: 16-24 publication: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS) publisher: IEEE status: public title: 'One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services' type: conference user_id: '24135' year: '2012' ... --- _id: '591' abstract: - lang: eng text: One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz citation: ama: 'Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773' apa: Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773 bibtex: '@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }' chicago: Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416773. ieee: 'T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8, doi: 10.1109/ReConFig.2012.6416773.' mla: Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773. short: 'T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.' date_created: 2017-10-17T12:42:47Z date_updated: 2023-09-26T13:41:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2012.6416773 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T08:33:18Z date_updated: 2018-03-15T08:33:18Z file_id: '1257' file_name: 591-ReConFig2012Kenter_Schmitz_Plessl.pdf file_size: 371235 relation: main_file success: 1 file_date_updated: 2018-03-15T08:33:18Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Pragma based parallelization - Trading hardware efficiency for ease of use? type: conference user_id: '15278' year: '2012' ... --- _id: '2180' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). ; 2012.' apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS). bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }' chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012. ieee: T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012. mla: Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012. short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.' date_created: 2018-04-03T09:18:33Z date_updated: 2023-09-26T13:40:17Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - funding-enhance language: - iso: eng project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS) quality_controlled: '1' status: public title: Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux type: conference user_id: '15278' year: '2012' ... --- _id: '2171' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke citation: ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From National to International Scale. In: Proc. EGI Community Forum. ; 2012.' apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R., Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International Scale. In Proc. EGI Community Forum. bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et al._2012, title={The MoSGrid Community From National to International Scale}, booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and et al.}, year={2012} }' chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community From National to International Scale.” In Proc. EGI Community Forum, 2012. ieee: S. Gesing et al., “The MoSGrid Community From National to International Scale,” in Proc. EGI Community Forum, 2012. mla: Gesing, Sandra, et al. “The MoSGrid Community From National to International Scale.” Proc. EGI Community Forum, 2012. short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P. Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, in: Proc. EGI Community Forum, 2012.' date_created: 2018-04-03T09:01:19Z date_updated: 2022-01-06T06:55:11Z department: - _id: '27' publication: Proc. EGI Community Forum status: public title: The MoSGrid Community From National to International Scale type: conference user_id: '24135' year: '2012' ... --- _id: '2101' author: - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Georg full_name: Best, Georg last_name: Best - first_name: Ivan full_name: Popov, Ivan last_name: Popov - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17. doi:10.1109/SC.Companion.2012.13' apa: Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW) (pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13 bibtex: '@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13}, booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel, Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012}, pages={13–17} }' chicago: Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann. “Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop (PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13. ieee: M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW), 2012, pp. 13–17. mla: Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13. short: 'M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17.' date_created: 2018-03-29T14:44:24Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1109/SC.Companion.2012.13 page: 13-17 publication: Proc. Parallel Data Storage Workshop (PDSW) publisher: IEEE status: public title: Towards Dynamic Scripted pNFS Layouts type: conference user_id: '24135' year: '2012' ... --- _id: '567' abstract: - lang: eng text: Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided. author: - first_name: Pablo full_name: Barrio, Pablo last_name: Barrio - first_name: Carlos full_name: Carreras, Carlos last_name: Carreras - first_name: Roberto full_name: Sierra, Roberto last_name: Sierra - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS). IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973' apa: 'Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973' bibtex: '@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={10.1109/HPCSim.2012.6266973}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }' chicago: 'Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.' ieee: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.' mla: 'Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–65, doi:10.1109/HPCSim.2012.6266973.' short: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.' date_created: 2017-10-17T12:42:42Z date_updated: 2023-09-26T13:42:54Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/HPCSim.2012.6266973 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-15T10:20:24Z date_updated: 2018-03-15T10:20:24Z file_id: '1275' file_name: 567-ba-ca-12a.pdf file_size: 288508 relation: main_file success: 1 file_date_updated: 2018-03-15T10:20:24Z has_accepted_license: '1' language: - iso: eng page: 559-565 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C publication: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS) publisher: IEEE quality_controlled: '1' status: public title: 'Turning control flow graphs into function calls: Code generation for heterogeneous architectures' type: conference user_id: '15278' year: '2012' ... --- _id: '2199' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Lars full_name: Packschies, Lars last_name: Packschies - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Anna full_name: Szikszay Fabri, Anna last_name: Szikszay Fabri - first_name: Klaus-Dieter full_name: Warzecha, Klaus-Dieter last_name: Warzecha - first_name: Martin full_name: Wewior, Martin last_name: Wewior - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: 'Gesing S, Kacsuk P, Kozlovszky M, et al. A Science Gateway for Molecular Simulations. In: Proc. EGI User Forum. ; 2011:94-95.' apa: Gesing, S., Kacsuk, P., Kozlovszky, M., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). A Science Gateway for Molecular Simulations. In Proc. EGI User Forum (pp. 94–95). bibtex: '@inproceedings{Gesing_Kacsuk_Kozlovszky_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Grunzke_Herres-Pawlis_et al._2011, title={A Science Gateway for Molecular Simulations}, booktitle={Proc. EGI User Forum}, author={Gesing, Sandra and Kacsuk, Peter and Kozlovszky, Miklos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Grunzke, Richard and Herres-Pawlis, Sonja and et al.}, year={2011}, pages={94–95} }' chicago: Gesing, Sandra, Peter Kacsuk, Miklos Kozlovszky, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “A Science Gateway for Molecular Simulations.” In Proc. EGI User Forum, 94–95, 2011. ieee: S. Gesing et al., “A Science Gateway for Molecular Simulations,” in Proc. EGI User Forum, 2011, pp. 94–95. mla: Gesing, Sandra, et al. “A Science Gateway for Molecular Simulations.” Proc. EGI User Forum, 2011, pp. 94–95. short: 'S. Gesing, P. Kacsuk, M. Kozlovszky, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, R. Grunzke, S. Herres-Pawlis, J. Krüger, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, A. Szikszay Fabri, K.-D. Warzecha, M. Wewior, O. Kohlbacher, in: Proc. EGI User Forum, 2011, pp. 94–95.' date_created: 2018-04-03T15:07:11Z date_updated: 2022-01-06T06:55:22Z department: - _id: '27' page: 94-95 publication: Proc. EGI User Forum status: public title: A Science Gateway for Molecular Simulations type: conference user_id: '24135' year: '2011' ... --- _id: '1972' abstract: - lang: eng text: We present a multi-agent system on top of the IaaS layer consisting of a scheduler agent and multiple worker agents. Each job is controlled by an autonomous worker agent, which is equipped with application specific knowledge (e.g., performance functions) allowing it to estimate the type and number of necessary resources. During runtime, the worker agent monitors the job and adapts its resources to ensure the specified quality of service - even in noisy clouds where the job instances are influenced by other jobs. All worker agents interact with the scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low energy costs. The whole architecture is self-optimizing and able to use public or private clouds. author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Niehörster O, Keller A, Brinkmann A. An Energy-Aware SaaS Stack. In: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). ; 2011. doi:10.1109/MASCOTS.2011.52' apa: Niehörster, O., Keller, A., & Brinkmann, A. (2011). An Energy-Aware SaaS Stack. In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). https://doi.org/10.1109/MASCOTS.2011.52 bibtex: '@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware SaaS Stack}, DOI={10.1109/MASCOTS.2011.52}, booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster, Oliver and Keller, Axel and Brinkmann, André}, year={2011} }' chicago: Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011. https://doi.org/10.1109/MASCOTS.2011.52. ieee: O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,” in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011. mla: Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52. short: 'O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.' date_created: 2018-03-29T11:23:22Z date_updated: 2022-01-06T06:54:10Z department: - _id: '27' doi: 10.1109/MASCOTS.2011.52 language: - iso: eng publication: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) publication_status: published status: public title: An Energy-Aware SaaS Stack type: conference user_id: '15274' year: '2011' ... --- _id: '2190' author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145. doi:10.1109/CloudCom.2011.28' apa: 'Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) (pp. 138–145). Washington DC, USA: IEEE Computer Society. https://doi.org/10.1109/CloudCom.2011.28' bibtex: '@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28}, booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André}, year={2011}, pages={138–145} }' chicago: 'Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.' ieee: O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed Configuration Effects,” in Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), 2011, pp. 138–145. mla: Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28. short: 'O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA, 2011, pp. 138–145.' date_created: 2018-04-03T14:33:50Z date_updated: 2022-01-06T06:55:19Z department: - _id: '27' doi: 10.1109/CloudCom.2011.28 page: 138-145 place: Washington DC, USA publication: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom) publisher: IEEE Computer Society status: public title: Autonomic Resource Management Handling Delayed Configuration Effects type: conference user_id: '24135' year: '2011' ... --- _id: '2203' author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Alexaner full_name: Krieger, Alexaner last_name: Krieger citation: ama: 'Niehörster O, Simon J, Brinkmann A, Krieger A. Autonomic Resource Management with Support Vector Machines. In: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID). Washington, DC, USA: IEEE Computer Society; 2011:157-164. doi:10.1109/Grid.2011.28' apa: 'Niehörster, O., Simon, J., Brinkmann, A., & Krieger, A. (2011). Autonomic Resource Management with Support Vector Machines. In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) (pp. 157–164). Washington, DC, USA: IEEE Computer Society. https://doi.org/10.1109/Grid.2011.28' bibtex: '@inproceedings{Niehörster_Simon_Brinkmann_Krieger_2011, place={Washington, DC, USA}, title={Autonomic Resource Management with Support Vector Machines}, DOI={10.1109/Grid.2011.28}, booktitle={Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)}, publisher={IEEE Computer Society}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Krieger, Alexaner}, year={2011}, pages={157–164} }' chicago: 'Niehörster, Oliver, Jens Simon, André Brinkmann, and Alexaner Krieger. “Autonomic Resource Management with Support Vector Machines.” In Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 157–64. Washington, DC, USA: IEEE Computer Society, 2011. https://doi.org/10.1109/Grid.2011.28.' ieee: O. Niehörster, J. Simon, A. Brinkmann, and A. Krieger, “Autonomic Resource Management with Support Vector Machines,” in Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), 2011, pp. 157–164. mla: Niehörster, Oliver, et al. “Autonomic Resource Management with Support Vector Machines.” Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, 2011, pp. 157–64, doi:10.1109/Grid.2011.28. short: 'O. Niehörster, J. Simon, A. Brinkmann, A. Krieger, in: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer Society, Washington, DC, USA, 2011, pp. 157–164.' date_created: 2018-04-03T15:13:42Z date_updated: 2022-01-06T06:55:23Z department: - _id: '27' doi: 10.1109/Grid.2011.28 page: 157-164 place: Washington, DC, USA publication: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID) publication_identifier: isbn: - 978-0-7695-4572-1 publisher: IEEE Computer Society status: public title: Autonomic Resource Management with Support Vector Machines type: conference user_id: '24135' year: '2011' ... --- _id: '2193' author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. In: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP). IEEE Computer Society; 2011:223-226. doi:10.1109/ASAP.2011.6043273' apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2011). Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler. Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–226. https://doi.org/10.1109/ASAP.2011.6043273 bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2011, title={Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler}, DOI={10.1109/ASAP.2011.6043273}, booktitle={Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP)}, publisher={IEEE Computer Society}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2011}, pages={223–226} }' chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” In Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 223–26. IEEE Computer Society, 2011. https://doi.org/10.1109/ASAP.2011.6043273. ieee: 'T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler,” in Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), 2011, pp. 223–226, doi: 10.1109/ASAP.2011.6043273.' mla: Beisel, Tobias, et al. “Cooperative Multitasking for Heterogeneous Accelerators in the Linux Completely Fair Scheduler.” Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–26, doi:10.1109/ASAP.2011.6043273. short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP), IEEE Computer Society, 2011, pp. 223–226.' date_created: 2018-04-03T14:37:14Z date_updated: 2023-09-26T13:43:48Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ASAP.2011.6043273 language: - iso: eng page: 223-226 project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP) publisher: IEEE Computer Society quality_controlled: '1' status: public title: Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler type: conference user_id: '15278' year: '2011' ... --- _id: '2191' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Michael full_name: Kauschke, Michael last_name: Kauschke citation: ama: 'Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: Intel European Research and Innovation Conference. ; 2011.' apa: Kenter, T., Plessl, C., Platzner, M., & Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In Intel European Research and Innovation Conference. bibtex: '@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }' chicago: Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In Intel European Research and Innovation Conference, 2011. ieee: T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in Intel European Research and Innovation Conference, 2011. mla: Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” Intel European Research and Innovation Conference, 2011. short: 'T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.' date_created: 2018-04-03T14:34:57Z date_updated: 2022-01-06T06:55:19Z department: - _id: '27' - _id: '518' - _id: '78' keyword: - funding-intel publication: Intel European Research and Innovation Conference status: public title: Estimation and Partitioning for CPU-Accelerator Architectures type: conference user_id: '24135' year: '2011' ... --- _id: '2195' author: - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Thorsten full_name: Schäfer, Thorsten last_name: Schäfer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Jens full_name: Hagemeyer, Jens last_name: Hagemeyer - first_name: Mario full_name: Porrmann, Mario last_name: Porrmann citation: ama: 'Grawinkel M, Schäfer T, Brinkmann A, Hagemeyer J, Porrmann M. Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS). IEEE Computer Society; 2011:297-306. doi:10.1109/mascots.2011.13' apa: Grawinkel, M., Schäfer, T., Brinkmann, A., Hagemeyer, J., & Porrmann, M. (2011). Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability. In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) (pp. 297–306). IEEE Computer Society. https://doi.org/10.1109/mascots.2011.13 bibtex: '@inproceedings{Grawinkel_Schäfer_Brinkmann_Hagemeyer_Porrmann_2011, title={Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability}, DOI={10.1109/mascots.2011.13}, booktitle={Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)}, publisher={IEEE Computer Society}, author={Grawinkel, Matthias and Schäfer, Thorsten and Brinkmann, André and Hagemeyer, Jens and Porrmann, Mario}, year={2011}, pages={297–306} }' chicago: Grawinkel, Matthias, Thorsten Schäfer, André Brinkmann, Jens Hagemeyer, and Mario Porrmann. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” In Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 297–306. IEEE Computer Society, 2011. https://doi.org/10.1109/mascots.2011.13. ieee: M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, and M. Porrmann, “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability,” in Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011, pp. 297–306. mla: Grawinkel, Matthias, et al. “Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability.” Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306, doi:10.1109/mascots.2011.13. short: 'M. Grawinkel, T. Schäfer, A. Brinkmann, J. Hagemeyer, M. Porrmann, in: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), IEEE Computer Society, 2011, pp. 297–306.' date_created: 2018-04-03T15:01:31Z date_updated: 2022-01-06T06:55:21Z department: - _id: '27' doi: 10.1109/mascots.2011.13 page: 297-306 publication: Proc. Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) publisher: IEEE Computer Society status: public title: Evaluation of Applied Intra-Disk Redundancy Schemes to Improve Single Disk Reliability type: conference user_id: '24135' year: '2011' ... --- _id: '2197' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Ákos full_name: Balaskó, Ákos last_name: Balaskó - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Lars full_name: Packschies, Lars last_name: Packschies - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Bernd full_name: Schuller, Bernd last_name: Schuller - first_name: Johannes full_name: Schuster, Johannes last_name: Schuster - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Anna full_name: Szikszay Fabri, Anna last_name: Szikszay Fabri - first_name: Martin full_name: Wewior, Martin last_name: Wewior - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: 'Gesing S, Grunzke R, Balaskó Á, et al. Granular Security for a Science Gateway in Structural Bioinformatics. In: Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA; 2011.' apa: Gesing, S., Grunzke, R., Balaskó, Á., Birkenheuer, G., Blunk, D., Breuers, S., … Kohlbacher, O. (2011). Granular Security for a Science Gateway in Structural Bioinformatics. In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA. bibtex: '@inproceedings{Gesing_Grunzke_Balaskó_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Herres-Pawlis_Kacsuk_et al._2011, title={Granular Security for a Science Gateway in Structural Bioinformatics}, booktitle={Proc. Int. Workshop on Scientific Gateways (IWSG)}, publisher={Consorzio COMETA}, author={Gesing, Sandra and Grunzke, Richard and Balaskó, Ákos and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Herres-Pawlis, Sonja and Kacsuk, Peter and et al.}, year={2011} }' chicago: Gesing, Sandra, Richard Grunzke, Ákos Balaskó, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André Brinkmann, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” In Proc. Int. Workshop on Scientific Gateways (IWSG). Consorzio COMETA, 2011. ieee: S. Gesing et al., “Granular Security for a Science Gateway in Structural Bioinformatics,” in Proc. Int. Workshop on Scientific Gateways (IWSG), 2011. mla: Gesing, Sandra, et al. “Granular Security for a Science Gateway in Structural Bioinformatics.” Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011. short: 'S. Gesing, R. Grunzke, Á. Balaskó, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Herres-Pawlis, P. Kacsuk, M. Kozlovszky, J. Krüger, L. Packschies, P. Schäfer, B. Schuller, J. Schuster, T. Steinke, A. Szikszay Fabri, M. Wewior, R. Müller-Pfefferkorn, O. Kohlbacher, in: Proc. Int. Workshop on Scientific Gateways (IWSG), Consorzio COMETA, 2011.' date_created: 2018-04-03T15:04:04Z date_updated: 2022-01-06T06:55:21Z department: - _id: '27' publication: Proc. Int. Workshop on Scientific Gateways (IWSG) publisher: Consorzio COMETA status: public title: Granular Security for a Science Gateway in Structural Bioinformatics type: conference user_id: '24135' year: '2011' ... --- _id: '2198' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. In: Proc. Reconfigurable Architectures Workshop (RAW). IEEE Computer Society; 2011:278-285. doi:10.1109/IPDPS.2011.153' apa: Grad, M., & Plessl, C. (2011). Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture. Proc. Reconfigurable Architectures Workshop (RAW), 278–285. https://doi.org/10.1109/IPDPS.2011.153 bibtex: '@inproceedings{Grad_Plessl_2011, title={Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture}, DOI={10.1109/IPDPS.2011.153}, booktitle={Proc. Reconfigurable Architectures Workshop (RAW)}, publisher={IEEE Computer Society}, author={Grad, Mariusz and Plessl, Christian}, year={2011}, pages={278–285} }' chicago: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” In Proc. Reconfigurable Architectures Workshop (RAW), 278–85. IEEE Computer Society, 2011. https://doi.org/10.1109/IPDPS.2011.153. ieee: 'M. Grad and C. Plessl, “Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture,” in Proc. Reconfigurable Architectures Workshop (RAW), 2011, pp. 278–285, doi: 10.1109/IPDPS.2011.153.' mla: Grad, Mariusz, and Christian Plessl. “Just-in-Time Instruction Set Extension – Feasibility and Limitations for an FPGA-Based Reconfigurable ASIP Architecture.” Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–85, doi:10.1109/IPDPS.2011.153. short: 'M. Grad, C. Plessl, in: Proc. Reconfigurable Architectures Workshop (RAW), IEEE Computer Society, 2011, pp. 278–285.' date_created: 2018-04-03T15:05:52Z date_updated: 2023-09-26T13:44:39Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/IPDPS.2011.153 language: - iso: eng page: 278-285 publication: Proc. Reconfigurable Architectures Workshop (RAW) publisher: IEEE Computer Society quality_controlled: '1' status: public title: Just-in-time Instruction Set Extension – Feasibility and Limitations for an FPGA-based Reconfigurable ASIP Architecture type: conference user_id: '15278' year: '2011' ... --- _id: '2189' author: - first_name: Matthias full_name: Grawinkel, Matthias last_name: Grawinkel - first_name: Markus full_name: Pargmann, Markus last_name: Pargmann - first_name: Hubert full_name: Dömer, Hubert last_name: Dömer - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Grawinkel M, Pargmann M, Dömer H, Brinkmann A. Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS). IEEE; 2011:380-387. doi:10.1109/ICPADS.2011.77' apa: 'Grawinkel, M., Pargmann, M., Dömer, H., & Brinkmann, A. (2011). Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) (pp. 380–387). IEEE. https://doi.org/10.1109/ICPADS.2011.77' bibtex: '@inproceedings{Grawinkel_Pargmann_Dömer_Brinkmann_2011, title={Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System}, DOI={10.1109/ICPADS.2011.77}, booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)}, publisher={IEEE}, author={Grawinkel, Matthias and Pargmann, Markus and Dömer, Hubert and Brinkmann, André}, year={2011}, pages={380–387} }' chicago: 'Grawinkel, Matthias, Markus Pargmann, Hubert Dömer, and André Brinkmann. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” In Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 380–87. IEEE, 2011. https://doi.org/10.1109/ICPADS.2011.77.' ieee: 'M. Grawinkel, M. Pargmann, H. Dömer, and A. Brinkmann, “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), 2011, pp. 380–387.' mla: 'Grawinkel, Matthias, et al. “Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System.” Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–87, doi:10.1109/ICPADS.2011.77.' short: 'M. Grawinkel, M. Pargmann, H. Dömer, A. Brinkmann, in: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2011, pp. 380–387.' date_created: 2018-04-03T14:32:23Z date_updated: 2022-01-06T06:55:18Z department: - _id: '27' doi: 10.1109/ICPADS.2011.77 page: 380-387 publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS) publisher: IEEE status: public title: 'Lonestar: An Energy-Aware Disk Based Long-Term Archival Storage System' type: conference user_id: '24135' year: '2011' ... --- _id: '656' abstract: - lang: eng text: In the next decades, hybrid multi-cores will be the predominant architecture for reconfigurable FPGA-based systems. Temperature-aware thread mapping strategies are key for providing dependability in such systems. These strategies rely on measuring the temperature distribution and redicting the thermal behavior of the system when there are changes to the hardware and software running on the FPGA. While there are a number of tools that use thermal models to predict temperature distributions at design time, these tools lack the flexibility to autonomously adjust to changing FPGA configurations. To address this problem we propose a temperature-aware system that empowers FPGA-based reconfigurable multi-cores to autonomously predict the on-chip temperature distribution for pro-active thread remapping. Our system obtains temperature measurements through a self-calibrating grid of sensors and uses area constrained heat-generating circuits in order to generate spatial and temporal temperature gradients. The generated temperature variations are then used to learn the free parameters of the system's thermal model. The system thus acquires an understanding of its own thermal characteristics. We implemented an FPGA system containing a net of 144 temperature sensors on a Xilinx Virtex-6 LX240T FPGA that is aware of its thermal model. Finally, we show that the temperature predictions vary less than 0.72 degree C on average compared to the measured temperature distributions at run-time. author: - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Happe M, Agne A, Plessl C. Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. In: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2011:55-60. doi:10.1109/ReConFig.2011.59' apa: Happe, M., Agne, A., & Plessl, C. (2011). Measuring and Predicting Temperature Distributions on FPGAs at Run-Time. Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. https://doi.org/10.1109/ReConFig.2011.59 bibtex: '@inproceedings{Happe_Agne_Plessl_2011, title={Measuring and Predicting Temperature Distributions on FPGAs at Run-Time}, DOI={10.1109/ReConFig.2011.59}, booktitle={Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2011}, pages={55–60} }' chicago: Happe, Markus, Andreas Agne, and Christian Plessl. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” In Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 55–60. IEEE, 2011. https://doi.org/10.1109/ReConFig.2011.59. ieee: 'M. Happe, A. Agne, and C. Plessl, “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time,” in Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2011, pp. 55–60, doi: 10.1109/ReConFig.2011.59.' mla: Happe, Markus, et al. “Measuring and Predicting Temperature Distributions on FPGAs at Run-Time.” Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60, doi:10.1109/ReConFig.2011.59. short: 'M. Happe, A. Agne, C. Plessl, in: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2011, pp. 55–60.' date_created: 2017-10-17T12:42:59Z date_updated: 2023-09-26T13:46:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2011.59 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-14T13:49:39Z date_updated: 2018-03-14T13:49:39Z file_id: '1220' file_name: 656-2011_happe_reconfig.pdf file_size: 502244 relation: main_file success: 1 file_date_updated: 2018-03-14T13:49:39Z has_accepted_license: '1' language: - iso: eng page: 55-60 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Measuring and Predicting Temperature Distributions on FPGAs at Run-Time type: conference user_id: '15278' year: '2011' ... --- _id: '2205' author: - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ulrich full_name: Lang, Ulrich last_name: Lang - first_name: Lars full_name: Packschies, Lars last_name: Packschies - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Johannes full_name: Schuster, Johannes last_name: Schuster - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: Klaus-Dieter full_name: Warzecha, Klaus-Dieter last_name: Warzecha - first_name: Martin full_name: Wewior, Martin last_name: Wewior citation: ama: 'Birkenheuer G, Blunk D, Breuers S, et al. MoSGrid: Progress of Workflow driven Chemical Simulations. In: Proc. of Grid Workflow Workshop (GWW). Vol 829. CEUR Workshop Proceedings. ; 2011.' apa: 'Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Fels, G., Gesing, S., … Wewior, M. (2011). MoSGrid: Progress of Workflow driven Chemical Simulations. In Proc. of Grid Workflow Workshop (GWW) (Vol. 829).' bibtex: '@inproceedings{Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Gesing_Grunzke_Herres-Pawlis_Kohlbacher_Krüger_et al._2011, series={CEUR Workshop Proceedings}, title={MoSGrid: Progress of Workflow driven Chemical Simulations}, volume={829}, booktitle={Proc. of Grid Workflow Workshop (GWW)}, author={Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André and Fels, Gregor and Gesing, Sandra and Grunzke, Richard and Herres-Pawlis, Sonja and Kohlbacher, Oliver and Krüger, Jens and et al.}, year={2011}, collection={CEUR Workshop Proceedings} }' chicago: 'Birkenheuer, Georg, Dirk Blunk, Sebastian Breuers, André Brinkmann, Gregor Fels, Sandra Gesing, Richard Grunzke, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” In Proc. of Grid Workflow Workshop (GWW), Vol. 829. CEUR Workshop Proceedings, 2011.' ieee: 'G. Birkenheuer et al., “MoSGrid: Progress of Workflow driven Chemical Simulations,” in Proc. of Grid Workflow Workshop (GWW), 2011, vol. 829.' mla: 'Birkenheuer, Georg, et al. “MoSGrid: Progress of Workflow Driven Chemical Simulations.” Proc. of Grid Workflow Workshop (GWW), vol. 829, 2011.' short: 'G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, G. Fels, S. Gesing, R. Grunzke, S. Herres-Pawlis, O. Kohlbacher, J. Krüger, U. Lang, L. Packschies, R. Müller-Pfefferkorn, P. Schäfer, J. Schuster, T. Steinke, K.-D. Warzecha, M. Wewior, in: Proc. of Grid Workflow Workshop (GWW), 2011.' date_created: 2018-04-04T09:34:24Z date_updated: 2022-01-06T06:55:23Z department: - _id: '27' intvolume: ' 829' publication: Proc. of Grid Workflow Workshop (GWW) series_title: CEUR Workshop Proceedings status: public title: 'MoSGrid: Progress of Workflow driven Chemical Simulations' type: conference user_id: '24135' volume: 829 year: '2011' ... --- _id: '2204' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Ulf full_name: Lorenz, Ulf last_name: Lorenz - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers citation: ama: 'Graf T, Lorenz U, Platzner M, Schaefers L. Parallel Monte-Carlo Tree Search for HPC Systems. In: Proc. European Conf. on Parallel Processing (Euro-Par). Vol 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer; 2011. doi:10.1007/978-3-642-23397-5_36' apa: 'Graf, T., Lorenz, U., Platzner, M., & Schaefers, L. (2011). Parallel Monte-Carlo Tree Search for HPC Systems. In Proc. European Conf. on Parallel Processing (Euro-Par) (Vol. 6853). Berlin / Heidelberg: Springer. https://doi.org/10.1007/978-3-642-23397-5_36' bibtex: '@inproceedings{Graf_Lorenz_Platzner_Schaefers_2011, place={Berlin / Heidelberg}, series={Lecture Notes in Computer Science (LNCS)}, title={Parallel Monte-Carlo Tree Search for HPC Systems}, volume={6853}, DOI={10.1007/978-3-642-23397-5_36}, booktitle={Proc. European Conf. on Parallel Processing (Euro-Par)}, publisher={Springer}, author={Graf, Tobias and Lorenz, Ulf and Platzner, Marco and Schaefers, Lars}, year={2011}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: 'Graf, Tobias, Ulf Lorenz, Marco Platzner, and Lars Schaefers. “Parallel Monte-Carlo Tree Search for HPC Systems.” In Proc. European Conf. on Parallel Processing (Euro-Par), Vol. 6853. Lecture Notes in Computer Science (LNCS). Berlin / Heidelberg: Springer, 2011. https://doi.org/10.1007/978-3-642-23397-5_36.' ieee: T. Graf, U. Lorenz, M. Platzner, and L. Schaefers, “Parallel Monte-Carlo Tree Search for HPC Systems,” in Proc. European Conf. on Parallel Processing (Euro-Par), 2011, vol. 6853. mla: Graf, Tobias, et al. “Parallel Monte-Carlo Tree Search for HPC Systems.” Proc. European Conf. on Parallel Processing (Euro-Par), vol. 6853, Springer, 2011, doi:10.1007/978-3-642-23397-5_36. short: 'T. Graf, U. Lorenz, M. Platzner, L. Schaefers, in: Proc. European Conf. on Parallel Processing (Euro-Par), Springer, Berlin / Heidelberg, 2011.' date_created: 2018-04-03T15:14:56Z date_updated: 2022-01-06T06:55:23Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-642-23397-5_36 intvolume: ' 6853' place: Berlin / Heidelberg publication: Proc. European Conf. on Parallel Processing (Euro-Par) publisher: Springer series_title: Lecture Notes in Computer Science (LNCS) status: public title: Parallel Monte-Carlo Tree Search for HPC Systems type: conference user_id: '24135' volume: 6853 year: '2011' ... --- _id: '2200' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Michael full_name: Kauschke, Michael last_name: Kauschke citation: ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448' apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448 bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={10.1145/1950413.1950448}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }' chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.' ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi: 10.1145/1950413.1950448.' mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448. short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.' date_created: 2018-04-03T15:08:13Z date_updated: 2023-09-26T13:45:04Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/1950413.1950448 keyword: - design space exploration - LLVM - partitioning - performance - estimation - funding-intel language: - iso: eng page: 177-180 place: New York, NY, USA publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) publication_identifier: isbn: - 978-1-4503-0554-9 publisher: ACM quality_controlled: '1' status: public title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures type: conference user_id: '15278' year: '2011' ... --- _id: '2188' author: - first_name: Alberto full_name: Miranda, Alberto last_name: Miranda - first_name: Sascha full_name: Effert, Sascha last_name: Effert - first_name: Yangwook full_name: Kang, Yangwook last_name: Kang - first_name: Ethan full_name: Miller, Ethan last_name: Miller - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Toni full_name: Cortes, Toni last_name: Cortes citation: ama: 'Miranda A, Effert S, Kang Y, Miller E, Brinkmann A, Cortes T. Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In: Proc. Int. Conf. on High Performance Computing (HIPC). Washington, DC: IEEE Computer Society; 2011:1-10. doi:10.1109/HiPC.2011.6152745' apa: 'Miranda, A., Effert, S., Kang, Y., Miller, E., Brinkmann, A., & Cortes, T. (2011). Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems. In Proc. Int. Conf. on High Performance Computing (HIPC) (pp. 1–10). Washington, DC: IEEE Computer Society. https://doi.org/10.1109/HiPC.2011.6152745' bibtex: '@inproceedings{Miranda_Effert_Kang_Miller_Brinkmann_Cortes_2011, place={Washington, DC}, title={Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems}, DOI={10.1109/HiPC.2011.6152745}, booktitle={Proc. Int. Conf. on High Performance Computing (HIPC)}, publisher={IEEE Computer Society}, author={Miranda, Alberto and Effert, Sascha and Kang, Yangwook and Miller, Ethan and Brinkmann, André and Cortes, Toni}, year={2011}, pages={1–10} }' chicago: 'Miranda, Alberto, Sascha Effert, Yangwook Kang, Ethan Miller, André Brinkmann, and Toni Cortes. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” In Proc. Int. Conf. on High Performance Computing (HIPC), 1–10. Washington, DC: IEEE Computer Society, 2011. https://doi.org/10.1109/HiPC.2011.6152745.' ieee: A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, and T. Cortes, “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems,” in Proc. Int. Conf. on High Performance Computing (HIPC), 2011, pp. 1–10. mla: Miranda, Alberto, et al. “Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems.” Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, 2011, pp. 1–10, doi:10.1109/HiPC.2011.6152745. short: 'A. Miranda, S. Effert, Y. Kang, E. Miller, A. Brinkmann, T. Cortes, in: Proc. Int. Conf. on High Performance Computing (HIPC), IEEE Computer Society, Washington, DC, 2011, pp. 1–10.' date_created: 2018-04-03T14:30:39Z date_updated: 2022-01-06T06:55:18Z department: - _id: '27' doi: 10.1109/HiPC.2011.6152745 page: 1-10 place: Washington, DC publication: Proc. Int. Conf. on High Performance Computing (HIPC) publisher: IEEE Computer Society status: public title: Reliable and Randomized Data Distribution Strategies for Large Scale Storage Systems type: conference user_id: '24135' year: '2011' ... --- _id: '2196' author: - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Yan full_name: Gao, Yan last_name: Gao - first_name: Miroslaw full_name: Korzeniowski, Miroslaw last_name: Korzeniowski - first_name: Dirk full_name: Meister, Dirk last_name: Meister citation: ama: 'Brinkmann A, Gao Y, Korzeniowski M, Meister D. Request Load Balancing for Highly Skewed Traffic in P2P Networks. In: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS). IEEE; 2011:53-62. doi:10.1109/NAS.2011.25' apa: Brinkmann, A., Gao, Y., Korzeniowski, M., & Meister, D. (2011). Request Load Balancing for Highly Skewed Traffic in P2P Networks. In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) (pp. 53–62). IEEE. https://doi.org/10.1109/NAS.2011.25 bibtex: '@inproceedings{Brinkmann_Gao_Korzeniowski_Meister_2011, title={Request Load Balancing for Highly Skewed Traffic in P2P Networks}, DOI={10.1109/NAS.2011.25}, booktitle={Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE}, author={Brinkmann, André and Gao, Yan and Korzeniowski, Miroslaw and Meister, Dirk}, year={2011}, pages={53–62} }' chicago: Brinkmann, André, Yan Gao, Miroslaw Korzeniowski, and Dirk Meister. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” In Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 53–62. IEEE, 2011. https://doi.org/10.1109/NAS.2011.25. ieee: A. Brinkmann, Y. Gao, M. Korzeniowski, and D. Meister, “Request Load Balancing for Highly Skewed Traffic in P2P Networks,” in Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), 2011, pp. 53–62. mla: Brinkmann, André, et al. “Request Load Balancing for Highly Skewed Traffic in P2P Networks.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62, doi:10.1109/NAS.2011.25. short: 'A. Brinkmann, Y. Gao, M. Korzeniowski, D. Meister, in: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS), IEEE, 2011, pp. 53–62.' date_created: 2018-04-03T15:03:17Z date_updated: 2022-01-06T06:55:21Z department: - _id: '27' doi: 10.1109/NAS.2011.25 page: 53-62 publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS) publisher: IEEE status: public title: Request Load Balancing for Highly Skewed Traffic in P2P Networks type: conference user_id: '24135' year: '2011' ... --- _id: '1968' abstract: - lang: eng text: 'Infrastructure as a Service providers use virtualization to abstract their hardware and to create a dynamic data center. Virtualization enables the consolidation of virtual machines as well as the migration of them to other hosts during runtime. Each provider has its own strategy to efficiently operate a data center. We present a rule based mapping algorithm for VMs, which is able to automatically adapt the mapping between VMs and physical hosts. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. We extended the open source IaaS solution Eucalyptus and we evaluated it with typical policies: maximizing the compute performance and VM locality to achieve a high performance and minimizing energy consumption. The evaluation was done on state-of-the-art servers in our own data center and by simulations using a workload of the Parallel Workload Archive. The results show that our algorithm performs well in dynamic data centers environments.' author: - first_name: Christoph full_name: Kleineweber, Christoph last_name: Kleineweber - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Kleineweber C, Keller A, Niehörster O, Brinkmann A. Rule Based Mapping of Virtual Machines in Clouds. In: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). ; 2011. doi:10.1109/PDP.2011.69' apa: Kleineweber, C., Keller, A., Niehörster, O., & Brinkmann, A. (2011). Rule Based Mapping of Virtual Machines in Clouds. In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP). https://doi.org/10.1109/PDP.2011.69 bibtex: '@inproceedings{Kleineweber_Keller_Niehörster_Brinkmann_2011, title={Rule Based Mapping of Virtual Machines in Clouds}, DOI={10.1109/PDP.2011.69}, booktitle={Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP)}, author={Kleineweber, Christoph and Keller, Axel and Niehörster, Oliver and Brinkmann, André}, year={2011} }' chicago: Kleineweber, Christoph, Axel Keller, Oliver Niehörster, and André Brinkmann. “Rule Based Mapping of Virtual Machines in Clouds.” In Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. https://doi.org/10.1109/PDP.2011.69. ieee: C. Kleineweber, A. Keller, O. Niehörster, and A. Brinkmann, “Rule Based Mapping of Virtual Machines in Clouds,” in Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011. mla: Kleineweber, Christoph, et al. “Rule Based Mapping of Virtual Machines in Clouds.” Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011, doi:10.1109/PDP.2011.69. short: 'C. Kleineweber, A. Keller, O. Niehörster, A. Brinkmann, in: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP), 2011.' date_created: 2018-03-29T11:21:05Z date_updated: 2022-01-06T06:54:10Z department: - _id: '27' doi: 10.1109/PDP.2011.69 language: - iso: eng publication: Proc. Int. Conf. on Parallel, Distributed and Network-Based Computing (PDP) publication_status: published status: public title: Rule Based Mapping of Virtual Machines in Clouds type: conference user_id: '15274' year: '2011' ... --- _id: '2194' author: - first_name: Björn full_name: Meyer, Björn last_name: Meyer - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: 'Meyer B, Plessl C, Förstner J. Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. In: Symp. on Application Accelerators in High Performance Computing (SAAHPC). IEEE Computer Society; 2011:60-63. doi:10.1109/SAAHPC.2011.12' apa: 'Meyer, B., Plessl, C., & Förstner, J. (2011). Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend. Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. https://doi.org/10.1109/SAAHPC.2011.12' bibtex: '@inproceedings{Meyer_Plessl_Förstner_2011, title={Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend}, DOI={10.1109/SAAHPC.2011.12}, booktitle={Symp. on Application Accelerators in High Performance Computing (SAAHPC)}, publisher={IEEE Computer Society}, author={Meyer, Björn and Plessl, Christian and Förstner, Jens}, year={2011}, pages={60–63} }' chicago: 'Meyer, Björn, Christian Plessl, and Jens Förstner. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” In Symp. on Application Accelerators in High Performance Computing (SAAHPC), 60–63. IEEE Computer Society, 2011. https://doi.org/10.1109/SAAHPC.2011.12.' ieee: 'B. Meyer, C. Plessl, and J. Förstner, “Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend,” in Symp. on Application Accelerators in High Performance Computing (SAAHPC), 2011, pp. 60–63, doi: 10.1109/SAAHPC.2011.12.' mla: 'Meyer, Björn, et al. “Transformation of Scientific Algorithms to Parallel Computing Code: Subdomain Support in a MPI-Multi-GPU Backend.” Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63, doi:10.1109/SAAHPC.2011.12.' short: 'B. Meyer, C. Plessl, J. Förstner, in: Symp. on Application Accelerators in High Performance Computing (SAAHPC), IEEE Computer Society, 2011, pp. 60–63.' date_created: 2018-04-03T14:55:57Z date_updated: 2023-09-26T13:44:11Z department: - _id: '27' - _id: '518' - _id: '15' - _id: '78' doi: 10.1109/SAAHPC.2011.12 keyword: - tet_topic_hpc language: - iso: eng page: 60-63 project: - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Symp. on Application Accelerators in High Performance Computing (SAAHPC) publisher: IEEE Computer Society quality_controlled: '1' status: public title: 'Transformation of scientific algorithms to parallel computing code: subdomain support in a MPI-multi-GPU backend' type: conference user_id: '15278' year: '2011' ... --- _id: '2224' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Grad M, Plessl C. An Open Source Circuit Library with Benchmarking Facilities. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:144-150.' apa: Grad, M., & Plessl, C. (2010). An Open Source Circuit Library with Benchmarking Facilities. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–150. bibtex: '@inproceedings{Grad_Plessl_2010, title={An Open Source Circuit Library with Benchmarking Facilities}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Grad, Mariusz and Plessl, Christian}, year={2010}, pages={144–150} }' chicago: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 144–50. CSREA Press, 2010. ieee: M. Grad and C. Plessl, “An Open Source Circuit Library with Benchmarking Facilities,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, pp. 144–150. mla: Grad, Mariusz, and Christian Plessl. “An Open Source Circuit Library with Benchmarking Facilities.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–50. short: 'M. Grad, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, pp. 144–150.' date_created: 2018-04-05T16:28:38Z date_updated: 2023-09-26T13:48:59Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: 144-150 publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: An Open Source Circuit Library with Benchmarking Facilities type: conference user_id: '15278' year: '2010' ... --- _id: '2229' author: - first_name: Petra full_name: Berenbrink, Petra last_name: Berenbrink - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tom full_name: Friedetzky, Tom last_name: Friedetzky - first_name: Lars full_name: Nagel, Lars last_name: Nagel citation: ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Nagel L. Balls into Bins with Related Random Choices. In: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA). New York: ACM; 2010:100-105. doi:10.1145/1810479.1810500' apa: 'Berenbrink, P., Brinkmann, A., Friedetzky, T., & Nagel, L. (2010). Balls into Bins with Related Random Choices. In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) (pp. 100–105). New York: ACM. https://doi.org/10.1145/1810479.1810500' bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Nagel_2010, place={New York}, title={Balls into Bins with Related Random Choices}, DOI={10.1145/1810479.1810500}, booktitle={Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA)}, publisher={ACM}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}, year={2010}, pages={100–105} }' chicago: 'Berenbrink, Petra, André Brinkmann, Tom Friedetzky, and Lars Nagel. “Balls into Bins with Related Random Choices.” In Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 100–105. New York: ACM, 2010. https://doi.org/10.1145/1810479.1810500.' ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, and L. Nagel, “Balls into Bins with Related Random Choices,” in Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), 2010, pp. 100–105. mla: Berenbrink, Petra, et al. “Balls into Bins with Related Random Choices.” Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, 2010, pp. 100–05, doi:10.1145/1810479.1810500. short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA), ACM, New York, 2010, pp. 100–105.' date_created: 2018-04-05T16:45:55Z date_updated: 2022-01-06T06:55:30Z department: - _id: '27' doi: 10.1145/1810479.1810500 page: 100-105 place: New York publication: Proc. Int. Symp. on Parallelism in Algorithms and Architectures (SPAA) publisher: ACM status: public title: Balls into Bins with Related Random Choices type: conference user_id: '24135' year: '2010' ... --- _id: '2232' author: - first_name: Petra full_name: Berenbrink, Petra last_name: Berenbrink - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Tom full_name: Friedetzky, Tom last_name: Friedetzky - first_name: Lars full_name: Nagel, Lars last_name: Nagel citation: ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Nagel L. Balls into Non-uniform Bins. In: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS). IEEE; 2010:1-10. doi:10.1109/IPDPS.2010.5470355' apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., & Nagel, L. (2010). Balls into Non-uniform Bins. In Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) (pp. 1–10). IEEE. https://doi.org/10.1109/IPDPS.2010.5470355 bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Nagel_2010, title={Balls into Non-uniform Bins}, DOI={10.1109/IPDPS.2010.5470355}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS)}, publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky, Tom and Nagel, Lars}, year={2010}, pages={1–10} }' chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, and Lars Nagel. “Balls into Non-Uniform Bins.” In Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), 1–10. IEEE, 2010. https://doi.org/10.1109/IPDPS.2010.5470355. ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, and L. Nagel, “Balls into Non-uniform Bins,” in Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), 2010, pp. 1–10. mla: Berenbrink, Petra, et al. “Balls into Non-Uniform Bins.” Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2010, pp. 1–10, doi:10.1109/IPDPS.2010.5470355. short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, L. Nagel, in: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS), IEEE, 2010, pp. 1–10.' date_created: 2018-04-05T16:50:03Z date_updated: 2022-01-06T06:55:31Z department: - _id: '27' doi: 10.1109/IPDPS.2010.5470355 page: 1-10 publication: Proc. Int. Symp. on Parallel and Distributed Processing (IPDPS) publisher: IEEE status: public title: Balls into Non-uniform Bins type: conference user_id: '24135' year: '2010' ... --- _id: '2220' author: - first_name: David full_name: Andrews, David last_name: Andrews - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Andrews D, Plessl C. Configurable Processor Architectures: History and Trends. In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA). CSREA Press; 2010:165.' apa: 'Andrews, D., & Plessl, C. (2010). Configurable Processor Architectures: History and Trends. Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165.' bibtex: '@inproceedings{Andrews_Plessl_2010, title={Configurable Processor Architectures: History and Trends}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Andrews, David and Plessl, Christian}, year={2010}, pages={165} }' chicago: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” In Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 165. CSREA Press, 2010.' ieee: 'D. Andrews and C. Plessl, “Configurable Processor Architectures: History and Trends,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), 2010, p. 165.' mla: 'Andrews, David, and Christian Plessl. “Configurable Processor Architectures: History and Trends.” Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.' short: 'D. Andrews, C. Plessl, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2010, p. 165.' date_created: 2018-04-05T14:57:07Z date_updated: 2023-09-26T13:47:33Z department: - _id: '27' - _id: '518' - _id: '78' language: - iso: eng page: '165' publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA) publication_identifier: isbn: - 1-60132-140-6 publisher: CSREA Press quality_controlled: '1' status: public title: 'Configurable Processor Architectures: History and Trends' type: conference user_id: '15278' year: '2010' ... --- _id: '2230' author: - first_name: Dirk full_name: Meister, Dirk last_name: Meister - first_name: André full_name: Brinkmann, André last_name: Brinkmann citation: ama: 'Meister D, Brinkmann A. dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD). In: Proc. Symp. on Mass Storage Systems and Technologies (MSST). Washington, DC: IEEE Computer Society; 2010:1-6. doi:10.1109/MSST.2010.5496992' apa: 'Meister, D., & Brinkmann, A. (2010). dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD). In Proc. Symp. on Mass Storage Systems and Technologies (MSST) (pp. 1–6). Washington, DC: IEEE Computer Society. https://doi.org/10.1109/MSST.2010.5496992' bibtex: '@inproceedings{Meister_Brinkmann_2010, place={Washington, DC}, title={dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)}, DOI={10.1109/MSST.2010.5496992}, booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE Computer Society}, author={Meister, Dirk and Brinkmann, André}, year={2010}, pages={1–6} }' chicago: 'Meister, Dirk, and André Brinkmann. “Dedupv1: Improving Deduplication Throughput Using Solid State Drives (SSD).” In Proc. Symp. on Mass Storage Systems and Technologies (MSST), 1–6. Washington, DC: IEEE Computer Society, 2010. https://doi.org/10.1109/MSST.2010.5496992.' ieee: 'D. Meister and A. Brinkmann, “dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD),” in Proc. Symp. on Mass Storage Systems and Technologies (MSST), 2010, pp. 1–6.' mla: 'Meister, Dirk, and André Brinkmann. “Dedupv1: Improving Deduplication Throughput Using Solid State Drives (SSD).” Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE Computer Society, 2010, pp. 1–6, doi:10.1109/MSST.2010.5496992.' short: 'D. Meister, A. Brinkmann, in: Proc. Symp. on Mass Storage Systems and Technologies (MSST), IEEE Computer Society, Washington, DC, 2010, pp. 1–6.' date_created: 2018-04-05T16:47:23Z date_updated: 2022-01-06T06:55:30Z department: - _id: '27' doi: 10.1109/MSST.2010.5496992 page: 1-6 place: Washington, DC publication: Proc. Symp. on Mass Storage Systems and Technologies (MSST) publisher: IEEE Computer Society status: public title: 'dedupv1: Improving Deduplication Throughput using Solid State Drives (SSD)' type: conference user_id: '24135' year: '2010' ... --- _id: '2237' author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon citation: ama: 'Niehörster O, Brinkmann A, Fels G, Krüger J, Simon J. Enforcing SLAs in Scientific Clouds. In: Proc. Int. Conf. on Cluster Computing (CLUSTER). IEEE; 2010:178-187. doi:10.1109/CLUSTER.2010.42' apa: Niehörster, O., Brinkmann, A., Fels, G., Krüger, J., & Simon, J. (2010). Enforcing SLAs in Scientific Clouds. In Proc. Int. Conf. on Cluster Computing (CLUSTER) (pp. 178–187). IEEE. https://doi.org/10.1109/CLUSTER.2010.42 bibtex: '@inproceedings{Niehörster_Brinkmann_Fels_Krüger_Simon_2010, title={Enforcing SLAs in Scientific Clouds}, DOI={10.1109/CLUSTER.2010.42}, booktitle={Proc. Int. Conf. on Cluster Computing (CLUSTER)}, publisher={IEEE}, author={Niehörster, Oliver and Brinkmann, André and Fels, Gregor and Krüger, Jens and Simon, Jens}, year={2010}, pages={178–187} }' chicago: Niehörster, Oliver, André Brinkmann, Gregor Fels, Jens Krüger, and Jens Simon. “Enforcing SLAs in Scientific Clouds.” In Proc. Int. Conf. on Cluster Computing (CLUSTER), 178–87. IEEE, 2010. https://doi.org/10.1109/CLUSTER.2010.42. ieee: O. Niehörster, A. Brinkmann, G. Fels, J. Krüger, and J. Simon, “Enforcing SLAs in Scientific Clouds,” in Proc. Int. Conf. on Cluster Computing (CLUSTER), 2010, pp. 178–187. mla: Niehörster, Oliver, et al. “Enforcing SLAs in Scientific Clouds.” Proc. Int. Conf. on Cluster Computing (CLUSTER), IEEE, 2010, pp. 178–87, doi:10.1109/CLUSTER.2010.42. short: 'O. Niehörster, A. Brinkmann, G. Fels, J. Krüger, J. Simon, in: Proc. Int. Conf. on Cluster Computing (CLUSTER), IEEE, 2010, pp. 178–187.' date_created: 2018-04-05T17:05:44Z date_updated: 2022-01-06T06:55:32Z department: - _id: '27' doi: 10.1109/CLUSTER.2010.42 page: 178-187 publication: Proc. Int. Conf. on Cluster Computing (CLUSTER) publication_identifier: issn: - 1552-5244 publisher: IEEE status: public title: Enforcing SLAs in Scientific Clouds type: conference user_id: '24135' year: '2010' ...