---
_id: '2103'
author:
- first_name: Martin
full_name: Wistuba, Martin
last_name: Wistuba
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction
Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence
and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143'
apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian
Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143
bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian
Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143},
booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE},
author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012},
pages={91–99} }'
chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian
Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.
ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction
Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence
and Games (CIG), 2012, pp. 91–99.
mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for
Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG),
IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.
short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.'
date_created: 2018-03-29T14:59:35Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/CIG.2012.6374143
page: 91-99
publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG)
publisher: IEEE
status: public
title: Comparison of Bayesian Move Prediction Systems for Computer Go
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2106'
abstract:
- lang: eng
text: "Although the benefits of FPGAs for accelerating scientific codes are widely
acknowledged, the use of FPGA accelerators in scientific computing is not widespread
because reaping these benefits requires knowledge of hardware design methods and
tools that is typically not available with domain scientists. A promising but
hardly investigated approach is to develop tool flows that keep the common languages
for scientific code (C,C++, and Fortran) and allow the developer to augment the
source code with OpenMPlike directives for instructing the compiler which parts
of the application shall be offloaded the FPGA accelerator.\r\nIn this work we
study whether the promise of effective FPGA acceleration with an OpenMP-like programming
effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable
computer for which an OpenMP-like\r\nprogramming environment exists. As case study
we use an application from computational nanophotonics. Our results\r\nshow that
a developer without previous FPGA experience could create an FPGA-accelerated
application that is competitive to an optimized OpenMP-parallelized CPU version
running on a two socket quad-core server. Finally, we discuss our experiences
with this tool flow and the Convey HC-1 from a productivity and economic point
of view."
author:
- first_name: Björn
full_name: Meyer, Björn
last_name: Meyer
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: 'Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities –
FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field
Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370'
apa: Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector
Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf.
on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370
bibtex: '@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector
Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian
and Förstner, Jens}, year={2012}, pages={189–196} }'
chicago: Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey
Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE,
2012. https://doi.org/10.1109/FPL.2012.6339370.
ieee: 'B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities
– FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field
Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.'
mla: Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with
an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications
(FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.
short: 'B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on
Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.'
conference:
name: 22nd International Conference on Field Programmable Logic and Applicaitons
(FPL)
date_created: 2018-03-29T15:04:25Z
date_updated: 2023-09-26T13:39:13Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '15'
- _id: '78'
doi: 10.1109/FPL.2012.6339370
file:
- access_level: closed
content_type: application/pdf
creator: fossie
date_created: 2019-02-13T09:04:46Z
date_updated: 2019-02-13T09:04:46Z
file_id: '7638'
file_name: 2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA
acceleratin with an openmp-like programming effort.pdf
file_size: 2148787
relation: main_file
success: 1
file_date_updated: 2019-02-13T09:04:46Z
has_accepted_license: '1'
keyword:
- funding-upb-forschungspreis
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 189-196
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: IEEE
quality_controlled: '1'
status: public
title: Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '1789'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Sascha
full_name: Effert, Sascha
last_name: Effert
citation:
ama: 'Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication
cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST).
IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380'
apa: Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of
an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems
and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380
bibtex: '@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an
exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380},
booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE},
author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha},
year={2012}, pages={1–12} }'
chicago: Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design
of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems
and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380.
ieee: J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data
deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies
(MSST), 2012, pp. 1–12.
mla: Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc.
Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12,
doi:10.1109/MSST.2012.6232380.
short: 'J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass
Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.'
date_created: 2018-03-26T15:12:01Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
doi: 10.1109/MSST.2012.6232380
page: 1-12
publication: Proc. Symp. on Mass Storage Systems and Technologies (MSST)
publisher: IEEE
status: public
title: Design of an exact data deduplication cluster
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '615'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, the accuracy of the simulations
is to some extent questionable and they require a high computational effort if
a detailed thermal model is used.For experimental evaluation of real-world temperature
management methods, often synthetic heat sources are employed. Therefore, in this
paper we investigated the question if we can create significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments in contrast to simulations. Therefore, we have developed eight
different heat-generating cores that use different subsets of the FPGA resources.
Our experimental results show that, according to the built-in thermal diode of
our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C
in less than 12 minutes by only utilizing about 21% of the slices.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire
– A Systematic Study of Heat Generators. In: Proceedings of the International
Conference on Reconfigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8.
doi:10.1109/ReConFig.2012.6416745'
apa: Happe, M., Hangmann, H., Agne, A., & Plessl, C. (2012). Eight Ways to put
your FPGA on Fire – A Systematic Study of Heat Generators. Proceedings of the
International Conference on Reconfigurable Computing and FPGAs (ReConFig),
1–8. https://doi.org/10.1109/ReConFig.2012.6416745
bibtex: '@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put
your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={10.1109/ReConFig.2012.6416745},
booktitle={Proceedings of the International Conference on Reconfigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik
and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }'
chicago: Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight
Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In Proceedings
of the International Conference on Reconfigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2012. https://doi.org/10.1109/ReConFig.2012.6416745.
ieee: 'M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA
on Fire – A Systematic Study of Heat Generators,” in Proceedings of the International
Conference on Reconfigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8,
doi: 10.1109/ReConFig.2012.6416745.'
mla: Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study
of Heat Generators.” Proceedings of the International Conference on Reconfigurable
Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416745.
short: 'M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International
Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.'
date_created: 2017-10-17T12:42:51Z
date_updated: 2023-09-26T13:42:26Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2012.6416745
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T06:48:32Z
date_updated: 2018-03-15T06:48:32Z
file_id: '1246'
file_name: 615-ReConFig12_01.pdf
file_size: 730144
relation: main_file
success: 1
file_date_updated: 2018-03-15T06:48:32Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the International Conference on Reconfigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2098'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Tim
full_name: Hartung, Tim
last_name: Hartung
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device.
In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS).
IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34'
apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2
Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems
(ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34'
bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2
Split Block Device}, DOI={10.1109/ICPADS.2012.34},
booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)},
publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and
Brinkmann, André}, year={2012}, pages={181–188} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB:
Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed
Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.'
ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block
Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS),
2012, pp. 181–188.'
mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int.
Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88,
doi:10.1109/ICPADS.2012.34.'
short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.'
date_created: 2018-03-29T14:40:04Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ICPADS.2012.34
page: 181-188
publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)
publisher: IEEE
status: public
title: 'ESB: Ext2 Split Block Device'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '612'
abstract:
- lang: eng
text: While numerous publications have presented ring oscillator designs for temperature
measurements a detailed study of the ring oscillator's design space is still missing.
In this work, we introduce metrics for comparing the performance and area efficiency
of ring oscillators and a methodology for determining these metrics. As a result,
we present a systematic study of the design space for ring oscillators for a Xilinx
Virtex-5 platform FPGA.
author:
- first_name: Christoph
full_name: Rüthing, Christoph
last_name: Rüthing
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design
Space for Temperature Measurements on FPGAs. In: Proceedings of the International
Conference on Field Programmable Logic and Applications (FPL). IEEE; 2012:559-562.
doi:10.1109/FPL.2012.6339370'
apa: Rüthing, C., Happe, M., Agne, A., & Plessl, C. (2012). Exploration of Ring
Oscillator Design Space for Temperature Measurements on FPGAs. Proceedings
of the International Conference on Field Programmable Logic and Applications (FPL),
559–562. https://doi.org/10.1109/FPL.2012.6339370
bibtex: '@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring
Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={10.1109/FPL.2012.6339370},
booktitle={Proceedings of the International Conference on Field Programmable Logic
and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe,
Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562}
}'
chicago: Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration
of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In Proceedings
of the International Conference on Field Programmable Logic and Applications (FPL),
559–62. IEEE, 2012. https://doi.org/10.1109/FPL.2012.6339370.
ieee: 'C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator
Design Space for Temperature Measurements on FPGAs,” in Proceedings of the
International Conference on Field Programmable Logic and Applications (FPL),
2012, pp. 559–562, doi: 10.1109/FPL.2012.6339370.'
mla: Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for
Temperature Measurements on FPGAs.” Proceedings of the International Conference
on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–62,
doi:10.1109/FPL.2012.6339370.
short: 'C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International
Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp.
559–562.'
date_created: 2017-10-17T12:42:51Z
date_updated: 2023-09-26T13:42:03Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPL.2012.6339370
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T06:49:03Z
date_updated: 2018-03-15T06:49:03Z
file_id: '1247'
file_name: 612-ruething_fpl12.pdf
file_size: 202923
relation: main_file
success: 1
file_date_updated: 2018-03-15T06:49:03Z
has_accepted_license: '1'
language:
- iso: eng
page: 559-562
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the International Conference on Field Programmable Logic
and Applications (FPL)
publisher: IEEE
quality_controlled: '1'
status: public
title: Exploration of Ring Oscillator Design Space for Temperature Measurements on
FPGAs
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2100'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind
signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG).
; 2012.'
apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive
blind signal separation algorithm. In Int. Architecture and Engineering Symp.
(ARCHENG).
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order
convolutive blind signal separation algorithm}, booktitle={Int. Architecture and
Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering
Symp. (ARCHENG), 2012.
ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive
blind signal separation algorithm,” in Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG),
2012.'
date_created: 2018-03-29T14:43:18Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
publication: Int. Architecture and Engineering Symp. (ARCHENG)
status: public
title: FPGA implementation of a second-order convolutive blind signal separation algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2097'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial
matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology
(ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125'
apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of
an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field
Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation
of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation
of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on
Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012.
https://doi.org/10.1109/FPT.2012.6412125.
ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate
polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable
Technology (ICFPT), 2012, pp. 135–140.
mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an
Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2012, pp. 135–140.'
date_created: 2018-03-29T14:34:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/FPT.2012.6412125
page: 135-140
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: FPGA-based design and implementation of an approximate polynomial matrix EVD
algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2104'
author:
- first_name: Tobias
full_name: Schlemmer, Tobias
last_name: Schlemmer
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
citation:
ama: 'Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science
Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.'
apa: Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn,
R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways
via Virtual Organizations. In Proc. EGI Technical Forum.
bibtex: '@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012,
title={Generic User Management for Science Gateways via Virtual Organizations},
booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke,
Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn,
Ralph and Kohlbacher, Oliver}, year={2012} }'
chicago: Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer,
Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for
Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum,
2012.
ieee: T. Schlemmer et al., “Generic User Management for Science Gateways
via Virtual Organizations,” in Proc. EGI Technical Forum, 2012.
mla: Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via
Virtual Organizations.” Proc. EGI Technical Forum, 2012.
short: 'T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn,
O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.'
date_created: 2018-03-29T15:00:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
publication: Proc. EGI Technical Forum
status: public
title: Generic User Management for Science Gateways via Virtual Organizations
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '609'
abstract:
- lang: eng
text: Today's design and operation principles and methods do not scale well with
future reconfigurable computing systems due to an increased complexity in system
architectures and applications, run-time dynamics and corresponding requirements.
Hence, novel design and operation principles and methods are needed that possibly
break drastically with the static ones we have built into our systems and the
fixed abstraction layers we have cherished over the last decades. Thus, we propose
a HW/SW platform that collects and maintains information about its state and progress
which enables the system to reason about its behavior (self-awareness) and utilizes
its knowledge to effectively and autonomously adapt its behavior to changing requirements
(self-expression).To enable self-awareness, our compute nodes collect information
using a variety of sensors, i.e. performance counters and thermal diodes, and
use internal self-awareness models that process these information. For self-awareness,
on-line learning is crucial such that the node learns and continuously updates
its models at run-time to react to changing conditions. To enable self-expression,
we break with the classic design-time abstraction layers of hardware, operating
system and software. In contrast, our system is able to vertically migrate functionalities
between the layers at run-time to exploit trade-offs between abstraction and optimization.This
paper presents a heterogeneous multi-core architecture, that enables self-awareness
and self-expression, an operating system for our proposed hardware/software platform
and a novel self-expression method.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware
Compute Nodes. In: Proceedings of the Workshop on Self-Awareness in Reconfigurable
Computing Systems (SRCS). ; 2012:8-9.'
apa: Happe, M., Agne, A., Plessl, C., & Platzner, M. (2012). Hardware/Software
Platform for Self-aware Compute Nodes. Proceedings of the Workshop on Self-Awareness
in Reconfigurable Computing Systems (SRCS), 8–9.
bibtex: '@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software
Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop
on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe,
Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012},
pages={8–9} }'
chicago: Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software
Platform for Self-Aware Compute Nodes.” In Proceedings of the Workshop on Self-Awareness
in Reconfigurable Computing Systems (SRCS), 8–9, 2012.
ieee: M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform
for Self-aware Compute Nodes,” in Proceedings of the Workshop on Self-Awareness
in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.
mla: Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.”
Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems
(SRCS), 2012, pp. 8–9.
short: 'M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop
on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.'
date_created: 2017-10-17T12:42:50Z
date_updated: 2023-09-26T13:41:36Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:14:17Z
date_updated: 2018-03-15T08:14:17Z
file_id: '1249'
file_name: 609-happe12_fpl_awareness.pdf
file_size: 146789
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:14:17Z
has_accepted_license: '1'
language:
- iso: eng
page: 8-9
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing
Systems (SRCS)
quality_controlled: '1'
status: public
title: Hardware/Software Platform for Self-aware Compute Nodes
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2105'
author:
- first_name: Giuseppe
full_name: Congiu, Giuseppe
last_name: Congiu
- first_name: Matthias
full_name: Grawinkel, Matthias
last_name: Grawinkel
- first_name: Sai
full_name: Narasimhamurthy, Sai
last_name: Narasimhamurthy
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A
Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc.
Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS).
IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16'
apa: 'Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012).
One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services. In Proc. Workshop on Interfaces and Architectures for Scientific
Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16'
bibtex: '@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One
Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services}, DOI={10.1109/ClusterW.2012.16},
booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data
Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias
and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }'
chicago: 'Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann.
“One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services.” In Proc. Workshop on Interfaces and Architectures for Scientific
Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.'
ieee: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase
Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,”
in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage
(IASDS), 2012, pp. 16–24.'
mla: 'Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment
Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and
Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24,
doi:10.1109/ClusterW.2012.16.'
short: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop
on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012,
pp. 16–24.'
date_created: 2018-03-29T15:02:15Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ClusterW.2012.16
page: 16-24
publication: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage
(IASDS)
publisher: IEEE
status: public
title: 'One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '591'
abstract:
- lang: eng
text: One major obstacle for a wide spread FPGA usage in general-purpose computing
is the development tool flow that requires much higher effort than for pure software
solutions. Convey Computer promises a solution to this problem for their HC-1
platform, where the FPGAs are configured to run as a vector processor and the software
source code can be annotated with pragmas that guide an automated vectorization
process. We investigate this approach for a stereo matching algorithm that has
abundant parallelism and a number of different computational patterns. We note
that for this case study the automated vectorization in its current state doesn’t
hold its productivity promise. However, we also show that using the Vector Personality
can yield a significant speedups compared to CPU implementations in two of three
investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations,
but can come with much reduced development effort.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
citation:
ama: 'Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware
efficiency for ease of use? In: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2012:1-8. doi:10.1109/ReConFig.2012.6416773'
apa: Kenter, T., Plessl, C., & Schmitz, H. (2012). Pragma based parallelization
- Trading hardware efficiency for ease of use? Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2012.6416773
bibtex: '@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization
- Trading hardware efficiency for ease of use?}, DOI={10.1109/ReConFig.2012.6416773},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian
and Schmitz, Henning}, year={2012}, pages={1–8} }'
chicago: Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization
- Trading Hardware Efficiency for Ease of Use?” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2012.
https://doi.org/10.1109/ReConFig.2012.6416773.
ieee: 'T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading
hardware efficiency for ease of use?,” in Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 2012, pp. 1–8,
doi: 10.1109/ReConFig.2012.6416773.'
mla: Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency
for Ease of Use?” Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8, doi:10.1109/ReConFig.2012.6416773.
short: 'T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.'
date_created: 2017-10-17T12:42:47Z
date_updated: 2023-09-26T13:41:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2012.6416773
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T08:33:18Z
date_updated: 2018-03-15T08:33:18Z
file_id: '1257'
file_name: 591-ReConFig2012Kenter_Schmitz_Plessl.pdf
file_size: 371235
relation: main_file
success: 1
file_date_updated: 2018-03-15T08:33:18Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Pragma based parallelization - Trading hardware efficiency for ease of use?
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2180'
author:
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model
for Supporting Heterogeneous Accelerators in Linux. In: Proc. Workshop on Computer
Architecture and Operating System Co-Design (CAOS). ; 2012.'
apa: Beisel, T., Wiersema, T., Plessl, C., & Brinkmann, A. (2012). Programming
and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. Proc.
Workshop on Computer Architecture and Operating System Co-Design (CAOS).
bibtex: '@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming
and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc.
Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel,
Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012}
}'
chicago: Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann.
“Programming and Scheduling Model for Supporting Heterogeneous Accelerators in
Linux.” In Proc. Workshop on Computer Architecture and Operating System Co-Design
(CAOS), 2012.
ieee: T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling
Model for Supporting Heterogeneous Accelerators in Linux,” 2012.
mla: Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous
Accelerators in Linux.” Proc. Workshop on Computer Architecture and Operating
System Co-Design (CAOS), 2012.
short: 'T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer
Architecture and Operating System Co-Design (CAOS), 2012.'
date_created: 2018-04-03T09:18:33Z
date_updated: 2023-09-26T13:40:17Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
keyword:
- funding-enhance
language:
- iso: eng
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Workshop on Computer Architecture and Operating System Co-design
(CAOS)
quality_controlled: '1'
status: public
title: Programming and Scheduling Model for Supporting Heterogeneous Accelerators
in Linux
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2171'
author:
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Sonja
full_name: Herres-Pawlis, Sonja
last_name: Herres-Pawlis
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Peter
full_name: Kacsuk, Peter
last_name: Kacsuk
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
- first_name: Miklos
full_name: Kozlovszky, Miklos
last_name: Kozlovszky
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Patrick
full_name: Schäfer, Patrick
last_name: Schäfer
- first_name: Thomas
full_name: Steinke, Thomas
last_name: Steinke
citation:
ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From
National to International Scale. In: Proc. EGI Community Forum. ; 2012.'
apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R.,
Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International
Scale. In Proc. EGI Community Forum.
bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et
al._2012, title={The MoSGrid Community From National to International Scale},
booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis,
Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk,
Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn,
Ralph and et al.}, year={2012} }'
chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann,
Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community
From National to International Scale.” In Proc. EGI Community Forum, 2012.
ieee: S. Gesing et al., “The MoSGrid Community From National to International
Scale,” in Proc. EGI Community Forum, 2012.
mla: Gesing, Sandra, et al. “The MoSGrid Community From National to International
Scale.” Proc. EGI Community Forum, 2012.
short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P.
Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer,
T. Steinke, in: Proc. EGI Community Forum, 2012.'
date_created: 2018-04-03T09:01:19Z
date_updated: 2022-01-06T06:55:11Z
department:
- _id: '27'
publication: Proc. EGI Community Forum
status: public
title: The MoSGrid Community From National to International Scale
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2101'
author:
- first_name: Matthias
full_name: Grawinkel, Matthias
last_name: Grawinkel
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Georg
full_name: Best, Georg
last_name: Best
- first_name: Ivan
full_name: Popov, Ivan
last_name: Popov
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted
pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17.
doi:10.1109/SC.Companion.2012.13'
apa: Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards
Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW)
(pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13
bibtex: '@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards
Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13},
booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel,
Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012},
pages={13–17} }'
chicago: Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann.
“Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop
(PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13.
ieee: M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic
Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW),
2012, pp. 13–17.
mla: Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc.
Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13.
short: 'M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel
Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17.'
date_created: 2018-03-29T14:44:24Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/SC.Companion.2012.13
page: 13-17
publication: Proc. Parallel Data Storage Workshop (PDSW)
publisher: IEEE
status: public
title: Towards Dynamic Scripted pNFS Layouts
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '567'
abstract:
- lang: eng
text: Heterogeneous machines are gaining momentum in the High Performance Computing
field, due to the theoretical speedups and power consumption. In practice, while
some applications meet the performance expectations, heterogeneous architectures
still require a tremendous effort from the application developers. This work presents
a code generation method to port codes into heterogeneous platforms, based on
transformations of the control flow into function calls. The results show that
the cost of the function-call mechanism is affordable for the tested HPC kernels.
The complete toolchain, based on the LLVM compiler infrastructure, is fully automated
once the sequential specification is provided.
author:
- first_name: Pablo
full_name: Barrio, Pablo
last_name: Barrio
- first_name: Carlos
full_name: Carreras, Carlos
last_name: Carreras
- first_name: Roberto
full_name: Sierra, Roberto
last_name: Sierra
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs
into function calls: Code generation for heterogeneous architectures. In: Proceedings
of the International Conference on High Performance Computing and Simulation (HPCS).
IEEE; 2012:559-565. doi:10.1109/HPCSim.2012.6266973'
apa: 'Barrio, P., Carreras, C., Sierra, R., Kenter, T., & Plessl, C. (2012).
Turning control flow graphs into function calls: Code generation for heterogeneous
architectures. Proceedings of the International Conference on High Performance
Computing and Simulation (HPCS), 559–565. https://doi.org/10.1109/HPCSim.2012.6266973'
bibtex: '@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning
control flow graphs into function calls: Code generation for heterogeneous architectures},
DOI={10.1109/HPCSim.2012.6266973},
booktitle={Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras,
Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012},
pages={559–565} }'
chicago: 'Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian
Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for
Heterogeneous Architectures.” In Proceedings of the International Conference
on High Performance Computing and Simulation (HPCS), 559–65. IEEE, 2012. https://doi.org/10.1109/HPCSim.2012.6266973.'
ieee: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control
flow graphs into function calls: Code generation for heterogeneous architectures,”
in Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS), 2012, pp. 559–565, doi: 10.1109/HPCSim.2012.6266973.'
mla: 'Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code
Generation for Heterogeneous Architectures.” Proceedings of the International
Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012,
pp. 559–65, doi:10.1109/HPCSim.2012.6266973.'
short: 'P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings
of the International Conference on High Performance Computing and Simulation (HPCS),
IEEE, 2012, pp. 559–565.'
date_created: 2017-10-17T12:42:42Z
date_updated: 2023-09-26T13:42:54Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/HPCSim.2012.6266973
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:20:24Z
date_updated: 2018-03-15T10:20:24Z
file_id: '1275'
file_name: 567-ba-ca-12a.pdf
file_size: 288508
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:20:24Z
has_accepted_license: '1'
language:
- iso: eng
page: 559-565
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the International Conference on High Performance Computing
and Simulation (HPCS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Turning control flow graphs into function calls: Code generation for heterogeneous
architectures'
type: conference
user_id: '15278'
year: '2012'
...
---
_id: '2199'
author:
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Peter
full_name: Kacsuk, Peter
last_name: Kacsuk
- first_name: Miklos
full_name: Kozlovszky, Miklos
last_name: Kozlovszky
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: Dirk
full_name: Blunk, Dirk
last_name: Blunk
- first_name: Sebastian
full_name: Breuers, Sebastian
last_name: Breuers
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Gregor
full_name: Fels, Gregor
last_name: Fels
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Sonja
full_name: Herres-Pawlis, Sonja
last_name: Herres-Pawlis
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Lars
full_name: Packschies, Lars
last_name: Packschies
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Patrick
full_name: Schäfer, Patrick
last_name: Schäfer
- first_name: Thomas
full_name: Steinke, Thomas
last_name: Steinke
- first_name: Anna
full_name: Szikszay Fabri, Anna
last_name: Szikszay Fabri
- first_name: Klaus-Dieter
full_name: Warzecha, Klaus-Dieter
last_name: Warzecha
- first_name: Martin
full_name: Wewior, Martin
last_name: Wewior
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
citation:
ama: 'Gesing S, Kacsuk P, Kozlovszky M, et al. A Science Gateway for Molecular Simulations.
In: Proc. EGI User Forum. ; 2011:94-95.'
apa: Gesing, S., Kacsuk, P., Kozlovszky, M., Birkenheuer, G., Blunk, D., Breuers,
S., … Kohlbacher, O. (2011). A Science Gateway for Molecular Simulations. In Proc.
EGI User Forum (pp. 94–95).
bibtex: '@inproceedings{Gesing_Kacsuk_Kozlovszky_Birkenheuer_Blunk_Breuers_Brinkmann_Fels_Grunzke_Herres-Pawlis_et
al._2011, title={A Science Gateway for Molecular Simulations}, booktitle={Proc.
EGI User Forum}, author={Gesing, Sandra and Kacsuk, Peter and Kozlovszky, Miklos
and Birkenheuer, Georg and Blunk, Dirk and Breuers, Sebastian and Brinkmann, André
and Fels, Gregor and Grunzke, Richard and Herres-Pawlis, Sonja and et al.}, year={2011},
pages={94–95} }'
chicago: Gesing, Sandra, Peter Kacsuk, Miklos Kozlovszky, Georg Birkenheuer, Dirk
Blunk, Sebastian Breuers, André Brinkmann, et al. “A Science Gateway for Molecular
Simulations.” In Proc. EGI User Forum, 94–95, 2011.
ieee: S. Gesing et al., “A Science Gateway for Molecular Simulations,” in
Proc. EGI User Forum, 2011, pp. 94–95.
mla: Gesing, Sandra, et al. “A Science Gateway for Molecular Simulations.” Proc.
EGI User Forum, 2011, pp. 94–95.
short: 'S. Gesing, P. Kacsuk, M. Kozlovszky, G. Birkenheuer, D. Blunk, S. Breuers,
A. Brinkmann, G. Fels, R. Grunzke, S. Herres-Pawlis, J. Krüger, L. Packschies,
R. Müller-Pfefferkorn, P. Schäfer, T. Steinke, A. Szikszay Fabri, K.-D. Warzecha,
M. Wewior, O. Kohlbacher, in: Proc. EGI User Forum, 2011, pp. 94–95.'
date_created: 2018-04-03T15:07:11Z
date_updated: 2022-01-06T06:55:22Z
department:
- _id: '27'
page: 94-95
publication: Proc. EGI User Forum
status: public
title: A Science Gateway for Molecular Simulations
type: conference
user_id: '24135'
year: '2011'
...
---
_id: '1972'
abstract:
- lang: eng
text: We present a multi-agent system on top of the IaaS layer consisting of a scheduler
agent and multiple worker agents. Each job is controlled by an autonomous worker
agent, which is equipped with application specific knowledge (e.g., performance
functions) allowing it to estimate the type and number of necessary resources.
During runtime, the worker agent monitors the job and adapts its resources to
ensure the specified quality of service - even in noisy clouds where the job instances
are influenced by other jobs. All worker agents interact with the scheduler agent,
which takes care of limited resources and does a cost-aware scheduling by assigning
jobs to times with low energy costs. The whole architecture is self-optimizing
and able to use public or private clouds.
author:
- first_name: Oliver
full_name: Niehörster, Oliver
last_name: Niehörster
- first_name: Axel
full_name: Keller, Axel
id: '15274'
last_name: Keller
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Niehörster O, Keller A, Brinkmann A. An Energy-Aware SaaS Stack. In: Proc.
Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer
and Telecommunication Systems (MASCOTS). ; 2011. doi:10.1109/MASCOTS.2011.52'
apa: Niehörster, O., Keller, A., & Brinkmann, A. (2011). An Energy-Aware SaaS
Stack. In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and
Simulation of Computer and Telecommunication Systems (MASCOTS). https://doi.org/10.1109/MASCOTS.2011.52
bibtex: '@inproceedings{Niehörster_Keller_Brinkmann_2011, title={An Energy-Aware
SaaS Stack}, DOI={10.1109/MASCOTS.2011.52},
booktitle={Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and
Simulation of Computer and Telecommunication Systems (MASCOTS)}, author={Niehörster,
Oliver and Keller, Axel and Brinkmann, André}, year={2011} }'
chicago: Niehörster, Oliver, Axel Keller, and André Brinkmann. “An Energy-Aware
SaaS Stack.” In Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis
and Simulation of Computer and Telecommunication Systems (MASCOTS), 2011.
https://doi.org/10.1109/MASCOTS.2011.52.
ieee: O. Niehörster, A. Keller, and A. Brinkmann, “An Energy-Aware SaaS Stack,”
in Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation
of Computer and Telecommunication Systems (MASCOTS), 2011.
mla: Niehörster, Oliver, et al. “An Energy-Aware SaaS Stack.” Proc. Int. Meeting
of the IEEE Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication
Systems (MASCOTS), 2011, doi:10.1109/MASCOTS.2011.52.
short: 'O. Niehörster, A. Keller, A. Brinkmann, in: Proc. Int. Meeting of the IEEE
Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication
Systems (MASCOTS), 2011.'
date_created: 2018-03-29T11:23:22Z
date_updated: 2022-01-06T06:54:10Z
department:
- _id: '27'
doi: 10.1109/MASCOTS.2011.52
language:
- iso: eng
publication: Proc. Int. Meeting of the IEEE Int. Symp. on Modeling, Analysis and Simulation
of Computer and Telecommunication Systems (MASCOTS)
publication_status: published
status: public
title: An Energy-Aware SaaS Stack
type: conference
user_id: '15274'
year: '2011'
...
---
_id: '2190'
author:
- first_name: Oliver
full_name: Niehörster, Oliver
last_name: Niehörster
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Niehörster O, Brinkmann A. Autonomic Resource Management Handling Delayed
Configuration Effects. In: Proc. IEEE Int. Conf. on Cloud Computing Technology
and Science (CloudCom). Washington DC, USA: IEEE Computer Society; 2011:138-145.
doi:10.1109/CloudCom.2011.28'
apa: 'Niehörster, O., & Brinkmann, A. (2011). Autonomic Resource Management
Handling Delayed Configuration Effects. In Proc. IEEE Int. Conf. on Cloud Computing
Technology and Science (CloudCom) (pp. 138–145). Washington DC, USA: IEEE
Computer Society. https://doi.org/10.1109/CloudCom.2011.28'
bibtex: '@inproceedings{Niehörster_Brinkmann_2011, place={Washington DC, USA}, title={Autonomic
Resource Management Handling Delayed Configuration Effects}, DOI={10.1109/CloudCom.2011.28},
booktitle={Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)},
publisher={IEEE Computer Society}, author={Niehörster, Oliver and Brinkmann, André},
year={2011}, pages={138–145} }'
chicago: 'Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management
Handling Delayed Configuration Effects.” In Proc. IEEE Int. Conf. on Cloud
Computing Technology and Science (CloudCom), 138–45. Washington DC, USA: IEEE
Computer Society, 2011. https://doi.org/10.1109/CloudCom.2011.28.'
ieee: O. Niehörster and A. Brinkmann, “Autonomic Resource Management Handling Delayed
Configuration Effects,” in Proc. IEEE Int. Conf. on Cloud Computing Technology
and Science (CloudCom), 2011, pp. 138–145.
mla: Niehörster, Oliver, and André Brinkmann. “Autonomic Resource Management Handling
Delayed Configuration Effects.” Proc. IEEE Int. Conf. on Cloud Computing Technology
and Science (CloudCom), IEEE Computer Society, 2011, pp. 138–45, doi:10.1109/CloudCom.2011.28.
short: 'O. Niehörster, A. Brinkmann, in: Proc. IEEE Int. Conf. on Cloud Computing
Technology and Science (CloudCom), IEEE Computer Society, Washington DC, USA,
2011, pp. 138–145.'
date_created: 2018-04-03T14:33:50Z
date_updated: 2022-01-06T06:55:19Z
department:
- _id: '27'
doi: 10.1109/CloudCom.2011.28
page: 138-145
place: Washington DC, USA
publication: Proc. IEEE Int. Conf. on Cloud Computing Technology and Science (CloudCom)
publisher: IEEE Computer Society
status: public
title: Autonomic Resource Management Handling Delayed Configuration Effects
type: conference
user_id: '24135'
year: '2011'
...
---
_id: '2203'
author:
- first_name: Oliver
full_name: Niehörster, Oliver
last_name: Niehörster
- first_name: Jens
full_name: Simon, Jens
id: '15273'
last_name: Simon
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Alexaner
full_name: Krieger, Alexaner
last_name: Krieger
citation:
ama: 'Niehörster O, Simon J, Brinkmann A, Krieger A. Autonomic Resource Management
with Support Vector Machines. In: Proc. IEEE/ACM Int. Conf. on Grid Computing
(GRID). Washington, DC, USA: IEEE Computer Society; 2011:157-164. doi:10.1109/Grid.2011.28'
apa: 'Niehörster, O., Simon, J., Brinkmann, A., & Krieger, A. (2011). Autonomic
Resource Management with Support Vector Machines. In Proc. IEEE/ACM Int. Conf.
on Grid Computing (GRID) (pp. 157–164). Washington, DC, USA: IEEE Computer
Society. https://doi.org/10.1109/Grid.2011.28'
bibtex: '@inproceedings{Niehörster_Simon_Brinkmann_Krieger_2011, place={Washington,
DC, USA}, title={Autonomic Resource Management with Support Vector Machines},
DOI={10.1109/Grid.2011.28},
booktitle={Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)}, publisher={IEEE
Computer Society}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André
and Krieger, Alexaner}, year={2011}, pages={157–164} }'
chicago: 'Niehörster, Oliver, Jens Simon, André Brinkmann, and Alexaner Krieger.
“Autonomic Resource Management with Support Vector Machines.” In Proc. IEEE/ACM
Int. Conf. on Grid Computing (GRID), 157–64. Washington, DC, USA: IEEE Computer
Society, 2011. https://doi.org/10.1109/Grid.2011.28.'
ieee: O. Niehörster, J. Simon, A. Brinkmann, and A. Krieger, “Autonomic Resource
Management with Support Vector Machines,” in Proc. IEEE/ACM Int. Conf. on Grid
Computing (GRID), 2011, pp. 157–164.
mla: Niehörster, Oliver, et al. “Autonomic Resource Management with Support Vector
Machines.” Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID), IEEE Computer
Society, 2011, pp. 157–64, doi:10.1109/Grid.2011.28.
short: 'O. Niehörster, J. Simon, A. Brinkmann, A. Krieger, in: Proc. IEEE/ACM Int.
Conf. on Grid Computing (GRID), IEEE Computer Society, Washington, DC, USA, 2011,
pp. 157–164.'
date_created: 2018-04-03T15:13:42Z
date_updated: 2022-01-06T06:55:23Z
department:
- _id: '27'
doi: 10.1109/Grid.2011.28
page: 157-164
place: Washington, DC, USA
publication: Proc. IEEE/ACM Int. Conf. on Grid Computing (GRID)
publication_identifier:
isbn:
- 978-0-7695-4572-1
publisher: IEEE Computer Society
status: public
title: Autonomic Resource Management with Support Vector Machines
type: conference
user_id: '24135'
year: '2011'
...