--- _id: '1592' abstract: - lang: eng text: Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL. In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE; 2017. doi:10.23919/FPL.2017.8056844' apa: Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). https://doi.org/10.23919/FPL.2017.8056844 bibtex: '@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian}, year={2017} }' chicago: Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844. ieee: 'T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.' mla: Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017, doi:10.23919/FPL.2017.8056844. short: 'T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017.' date_created: 2018-03-22T11:10:23Z date_updated: 2023-09-26T13:24:38Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '61' doi: 10.23919/FPL.2017.8056844 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:02:28Z date_updated: 2018-11-02T15:02:28Z file_id: '5291' file_name: 08056844.pdf file_size: 230235 relation: main_file success: 1 file_date_updated: 2018-11-02T15:02:28Z has_accepted_license: '1' keyword: - tet_topic_hpc language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '33' grant_number: 01|H16005A name: HighPerMeshes - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL) publisher: IEEE quality_controlled: '1' status: public title: Flexible FPGA design for FDTD using OpenCL type: conference user_id: '15278' year: '2017' ... --- _id: '34' author: - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz - first_name: Julian full_name: Eckstein, Julian last_name: Eckstein - first_name: Kathrin full_name: Flaßkamp, Kathrin last_name: Flaßkamp - first_name: Patrick full_name: Friedel, Patrick last_name: Friedel - first_name: Christian full_name: Horenkamp, Christian last_name: Horenkamp - first_name: Ulrich full_name: Köhler, Ulrich last_name: Köhler - first_name: Sina full_name: Ober-Blöbaum, Sina last_name: Ober-Blöbaum - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Sebastian full_name: Tiemeyer, Sebastian last_name: Tiemeyer citation: ama: 'Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In: Progress in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham: Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87' apa: 'Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler, U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control. In Progress in Industrial Mathematics at ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87' bibtex: '@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016, place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control}, volume={22}, DOI={10.1007/978-3-319-23413-7_87}, booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum, Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641}, collection={Mathematics in Industry} }' chicago: 'Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel, Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41. Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.' ieee: M. Dellnitz et al., “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics at ECMI, 2016, vol. 22, pp. 633–641. mla: Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI, vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87. short: 'M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler, S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.' date_created: 2017-07-26T15:25:33Z date_updated: 2022-01-06T06:59:14Z department: - _id: '27' - _id: '101' doi: 10.1007/978-3-319-23413-7_87 intvolume: ' 22' page: 633-641 place: Cham publication: Progress in Industrial Mathematics at ECMI publication_identifier: issn: - 2212-0173 publisher: Springer International Publishing series_title: Mathematics in Industry status: public title: Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control type: conference user_id: '24135' volume: 22 year: '2016' ... --- _id: '19' abstract: - lang: eng text: "Version Control Systems (VCS) are a valuable tool for software development\r\nand document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular. Their distributed nature introduces complications,\r\nespecially concerning security: it is hard to control the dissemination of\r\ncontents stored in distributed VCS as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe overcome this issue by designing and implementing a concept for\r\ncryptography-enforced access control which is transparent to the user. Use\r\nof field-tested schemes (end-to-end encryption, digital signatures) allows\r\nfor strong security, while adoption of convergent encryption and\r\ncontent-defined chunking retains storage efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting its distributed storage\r\nconcept---to ensure practical usability and compatibility to existing\r\ndeployments." author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Dominik full_name: Leibenger, Dominik last_name: Leibenger - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11' apa: Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11 bibtex: '@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11}, booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE}, author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016} }' chicago: Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016. https://doi.org/10.1109/lcn.2016.11. ieee: M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st Conference on Local Computer Networks (LCN), 2016. mla: Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11. short: 'M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer Networks (LCN), IEEE, 2016.' date_created: 2017-07-25T14:36:16Z date_updated: 2022-01-06T06:53:56Z department: - _id: '27' - _id: '518' doi: 10.1109/lcn.2016.11 keyword: - access control - distributed version control systems - mercurial - peer-to-peer - convergent encryption - confidentiality - authenticity language: - iso: eng publication: Proc. 41st Conference on Local Computer Networks (LCN) publication_identifier: isbn: - 978-1-5090-2054-6 publication_status: published publisher: IEEE status: public title: Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension type: conference user_id: '24135' year: '2016' ... --- _id: '31' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Ettore M. G. full_name: Trainiti, Ettore M. G. last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. ieee: H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016. mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.' date_created: 2017-07-26T15:16:31Z date_updated: 2023-09-26T13:25:59Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: deffel date_created: 2019-01-11T11:56:55Z date_updated: 2019-01-11T11:56:55Z file_id: '6626' file_name: wrc_upb_polimi_final.pdf file_size: 394563 relation: main_file success: 1 file_date_updated: 2019-01-11T11:56:55Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '24' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.' apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016. mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.' date_created: 2017-07-26T15:00:43Z date_updated: 2023-09-26T13:26:17Z ddc: - '004' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: kenter date_created: 2018-11-14T12:38:45Z date_updated: 2018-11-14T12:38:45Z file_id: '5602' file_name: paper_26.pdf file_size: 129552 relation: main_file success: 1 file_date_updated: 2018-11-14T12:38:45Z has_accepted_license: '1' language: - iso: eng project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) quality_controlled: '1' status: public title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL type: conference user_id: '15278' year: '2016' ... --- _id: '25' author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.' apa: Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC). bibtex: '@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }' chicago: Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016. ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016. mla: Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016. short: 'M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.' date_created: 2017-07-26T15:02:20Z date_updated: 2023-09-26T13:25:17Z department: - _id: '27' - _id: '518' - _id: '304' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Workshop on Approximate Computing (AC) quality_controlled: '1' status: public title: Using Approximate Computing in Scientific Codes type: conference user_id: '15278' year: '2016' ... --- _id: '138' abstract: - lang: eng text: Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: 'Ettore M. G. ' full_name: 'Trainiti, Ettore M. G. ' last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Emanuele full_name: Del Sozzo, Emanuele last_name: Del Sozzo - first_name: 'Marco D. ' full_name: 'Santambrogio, Marco D. ' last_name: Santambrogio - first_name: Christina full_name: Bolchini, Christina last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545 bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545. ieee: 'H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.' mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.' date_created: 2017-10-17T12:41:18Z date_updated: 2023-09-26T13:28:11Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1109/RTSI.2016.7740545 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:01:09Z date_updated: 2018-03-21T13:01:09Z file_id: '1560' file_name: 138-07740545.pdf file_size: 184334 relation: main_file success: 1 file_date_updated: 2018-03-21T13:01:09Z has_accepted_license: '1' language: - iso: eng page: 1-5 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) publisher: IEEE quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '168' abstract: - lang: eng text: The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.' apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917. bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }' chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016. ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917. mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17. short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.' date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:27:00Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:41:55Z date_updated: 2018-03-21T12:41:55Z file_id: '1541' file_name: 168-07459438.pdf file_size: 261356 relation: main_file success: 1 file_date_updated: 2018-03-21T12:41:55Z has_accepted_license: '1' language: - iso: eng page: 912-917 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center type: conference user_id: '15278' year: '2016' ... --- _id: '171' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.' apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC). bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016. ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016. mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016. short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.' date_created: 2017-10-17T12:41:25Z date_updated: 2023-09-26T13:27:21Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:39:46Z date_updated: 2018-03-21T12:39:46Z file_id: '1538' file_name: 171-plessl16_fpl_wrc.pdf file_size: 54421 relation: main_file success: 1 file_date_updated: 2018-03-21T12:39:46Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Workshop on Reconfigurable Computing (WRC) quality_controlled: '1' status: public title: Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) type: conference user_id: '15278' year: '2016' ... --- _id: '303' abstract: - lang: eng text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.' apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }' chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015. mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.' date_created: 2017-10-17T12:41:51Z date_updated: 2023-09-26T13:29:59Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' external_id: arxiv: - '1412.3906' file: - access_level: open_access content_type: application/pdf creator: florida date_created: 2018-03-20T07:46:46Z date_updated: 2019-08-01T09:10:44Z file_id: '1442' file_name: 303-plessl15_adapt.pdf file_size: 1176620 relation: main_file file_date_updated: 2019-08-01T09:10:44Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) quality_controlled: '1' status: public title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores type: conference user_id: '15278' year: '2015' ... --- _id: '1773' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: J. full_name: T. Anderson, J. last_name: T. Anderson - first_name: A. full_name: Borga, A. last_name: Borga - first_name: H. full_name: Boterenbrood, H. last_name: Boterenbrood - first_name: H. full_name: Chen, H. last_name: Chen - first_name: K. full_name: Chen, K. last_name: Chen - first_name: G. full_name: Drake, G. last_name: Drake - first_name: D. full_name: Francis, D. last_name: Francis - first_name: B. full_name: Gorini, B. last_name: Gorini - first_name: F. full_name: Lanni, F. last_name: Lanni - first_name: Giovanna full_name: Lehmann-Miotto, Giovanna last_name: Lehmann-Miotto - first_name: L. full_name: Levinson, L. last_name: Levinson - first_name: J. full_name: Narevicius, J. last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A. full_name: Roich, A. last_name: Roich - first_name: S. full_name: Ryu, S. last_name: Ryu - first_name: F. full_name: P. Schreuder, F. last_name: P. Schreuder - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J. full_name: Vermeulen, J. last_name: Vermeulen - first_name: J. full_name: Zhang, J. last_name: Zhang citation: ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824' apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824 bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }' chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824. ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.' mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824. short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.' date_created: 2018-03-23T14:09:33Z date_updated: 2023-09-26T13:31:01Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/2675743.2771824 language: - iso: eng publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) publisher: ACM quality_controlled: '1' status: public title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm type: conference user_id: '15278' year: '2015' ... --- _id: '238' abstract: - lang: eng text: In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083. doi:10.7873/DATE.2015.1124' apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083. https://doi.org/10.7873/DATE.2015.1124 bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }' chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124. ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015, pp. 1078–1083, doi: 10.7873/DATE.2015.1124.' mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83, doi:10.7873/DATE.2015.1124. short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.' date_created: 2017-10-17T12:41:38Z date_updated: 2023-09-26T13:31:44Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.7873/DATE.2015.1124 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T10:29:49Z date_updated: 2018-03-21T10:29:49Z file_id: '1500' file_name: 238-plessl15_date.pdf file_size: 380552 relation: main_file success: 1 file_date_updated: 2018-03-21T10:29:49Z has_accepted_license: '1' language: - iso: eng page: 1078-1083 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Transparent offloading of computational hotspots from binary code to Xeon Phi type: conference user_id: '15278' year: '2015' ... --- _id: '1781' abstract: - lang: eng text: In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment. author: - first_name: Tobias full_name: Steinle, Tobias last_name: Steinle - first_name: Jadran full_name: Vrabec, Jadran last_name: Vrabec - first_name: Andrea full_name: Walther, Andrea last_name: Walther citation: ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC). Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19' apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang, R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing. https://doi.org/10.1007/978-3-319-09063-4_19 bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19}, booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)}, publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec, Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243} }' chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19. ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), 2014, pp. 233–243. mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg Bock et al., Springer International Publishing, 2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19. short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher, J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC), Springer International Publishing, 2014, pp. 233–243.' date_created: 2018-03-26T13:47:16Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '104' - _id: '155' doi: 10.1007/978-3-319-09063-4_19 editor: - first_name: Hans Georg full_name: Bock, Hans Georg last_name: Bock - first_name: Xuan Phu full_name: Hoang, Xuan Phu last_name: Hoang - first_name: Rolf full_name: Rannacher, Rolf last_name: Rannacher - first_name: Johannes P. full_name: Schlöder, Johannes P. last_name: Schlöder page: 233-243 publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC) publication_identifier: isbn: - 978-3-319-09063-4 publisher: Springer International Publishing status: public title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres type: conference user_id: '24135' year: '2014' ... --- _id: '1782' author: - first_name: Tobias full_name: Graf, Tobias last_name: Graf - first_name: Lars full_name: Schaefers, Lars last_name: Schaefers - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In: Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science. Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2' apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25). Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2' bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2}, number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer}, author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25}, collection={Lecture Notes in Computer Science} }' chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25. Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.' ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25. mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf. on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2. short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games (CG), Springer, Switzerland, 2014, pp. 14–25.' date_created: 2018-03-26T13:50:37Z date_updated: 2022-01-06T06:53:20Z department: - _id: '27' - _id: '78' doi: 10.1007/978-3-319-09165-5_2 issue: '8427' page: 14-25 place: Switzerland publication: Proc. Conf. on Computers and Games (CG) publisher: Springer series_title: Lecture Notes in Computer Science status: public title: On Semeai Detection in Monte-Carlo Go type: conference user_id: '24135' year: '2014' ... --- _id: '388' abstract: - lang: eng text: In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13' apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13' bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }' chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.' ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.' mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.' short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.' date_created: 2017-10-17T12:42:07Z date_updated: 2023-09-26T13:34:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_13 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:02:02Z date_updated: 2018-03-20T07:02:02Z file_id: '1387' file_name: 388-plessl14_arc.pdf file_size: 330193 relation: main_file success: 1 file_date_updated: 2018-03-20T07:02:02Z has_accepted_license: '1' intvolume: ' 8405' language: - iso: eng page: 144-155 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)' publisher: Springer International Publishing quality_controlled: '1' series_title: Lecture Notes in Computer Science (LNCS) status: public title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer type: conference user_id: '15278' volume: 8405 year: '2014' ... --- _id: '377' abstract: - lang: eng text: In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Christoph full_name: Sorge, Christoph last_name: Sorge citation: ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67' apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67 bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }' chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014. https://doi.org/10.1109/FCCM.2014.67. ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.' mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67. short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.' date_created: 2017-10-17T12:42:05Z date_updated: 2023-09-26T13:33:50Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/FCCM.2014.67 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:14:20Z date_updated: 2018-03-20T07:14:20Z file_id: '1397' file_name: 377-FCCM14.pdf file_size: 1003907 relation: main_file success: 1 file_date_updated: 2018-03-20T07:14:20Z has_accepted_license: '1' keyword: - coldboot language: - iso: eng page: 222-229 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM) publisher: IEEE quality_controlled: '1' status: public title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs type: conference user_id: '15278' year: '2014' ... --- _id: '1778' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Pogliani, Marcello last_name: Pogliani - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27' apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–149. https://doi.org/10.1109/ISPA.2014.27' bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={10.1109/ISPA.2014.27}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }' chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.' ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.' mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.' short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.' date_created: 2018-03-26T13:40:14Z date_updated: 2023-09-26T13:35:40Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ISPA.2014.27 language: - iso: eng page: 142-149 project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA) publisher: IEEE quality_controlled: '1' status: public title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach' type: conference user_id: '15278' year: '2014' ... --- _id: '439' abstract: - lang: eng text: Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509' apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509 bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509. ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.' mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509. short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:17Z date_updated: 2023-09-26T13:37:02Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032509 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:29:52Z date_updated: 2018-03-16T11:29:52Z file_id: '1353' file_name: 439-plessl14a_reconfig.pdf file_size: 557362 relation: main_file success: 1 file_date_updated: 2018-03-16T11:29:52Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Deferring Accelerator Offloading Decisions to Application Runtime type: conference user_id: '15278' year: '2014' ... --- _id: '406' abstract: - lang: eng text: Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design. author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535' apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535 bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032535. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.' mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535. short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.' date_created: 2017-10-17T12:42:11Z date_updated: 2023-09-26T13:36:40Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/ReConFig.2014.7032535 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:37:42Z date_updated: 2018-03-16T11:37:42Z file_id: '1366' file_name: 406-ReConFig14.pdf file_size: 932852 relation: main_file success: 1 file_date_updated: 2018-03-16T11:37:42Z has_accepted_license: '1' language: - iso: eng page: 1-8 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) publisher: IEEE quality_controlled: '1' status: public title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching type: conference user_id: '15278' year: '2014' ... --- _id: '1780' author: - first_name: Gianluca full_name: C. Durelli, Gianluca last_name: C. Durelli - first_name: Marcello full_name: Copolla, Marcello last_name: Copolla - first_name: Karim full_name: Djafarian, Karim last_name: Djafarian - first_name: George full_name: Koranaros, George last_name: Koranaros - first_name: Antonio full_name: Miele, Antonio last_name: Miele - first_name: Michele full_name: Paolino, Michele last_name: Paolino - first_name: Oliver full_name: Pell, Oliver last_name: Pell - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: D. Santambrogio, Marco last_name: D. Santambrogio - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38' apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino, M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE: Towards efficient resource management in heterogeneous system architectures. Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). https://doi.org/10.1007/978-3-319-05960-0_38' bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D. Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38}, booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014} }' chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros, Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio, and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.' ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.' mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.' short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino, O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC), Springer, 2014.' date_created: 2018-03-26T13:45:35Z date_updated: 2023-09-26T13:36:20Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1007/978-3-319-05960-0_38 language: - iso: eng project: - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC)' publisher: Springer quality_controlled: '1' status: public title: 'SAVE: Towards efficient resource management in heterogeneous system architectures' type: conference user_id: '15278' year: '2014' ...