---
_id: '1773'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: J.
full_name: T. Anderson, J.
last_name: T. Anderson
- first_name: A.
full_name: Borga, A.
last_name: Borga
- first_name: H.
full_name: Boterenbrood, H.
last_name: Boterenbrood
- first_name: H.
full_name: Chen, H.
last_name: Chen
- first_name: K.
full_name: Chen, K.
last_name: Chen
- first_name: G.
full_name: Drake, G.
last_name: Drake
- first_name: D.
full_name: Francis, D.
last_name: Francis
- first_name: B.
full_name: Gorini, B.
last_name: Gorini
- first_name: F.
full_name: Lanni, F.
last_name: Lanni
- first_name: Giovanna
full_name: Lehmann-Miotto, Giovanna
last_name: Lehmann-Miotto
- first_name: L.
full_name: Levinson, L.
last_name: Levinson
- first_name: J.
full_name: Narevicius, J.
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A.
full_name: Roich, A.
last_name: Roich
- first_name: S.
full_name: Ryu, S.
last_name: Ryu
- first_name: F.
full_name: P. Schreuder, F.
last_name: P. Schreuder
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J.
full_name: Vermeulen, J.
last_name: Vermeulen
- first_name: J.
full_name: Zhang, J.
last_name: Zhang
citation:
ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015.
doi:10.1145/2675743.2771824'
apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen,
K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson,
L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli,
W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et
al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project
– Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824},
booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM},
author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H.
and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni,
F. and et al.}, year={2015} }'
chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K.
Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX
Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.
ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in
the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”
2015, doi: 10.1145/2675743.2771824.'
mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS
FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen,
G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J.
Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen,
J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM,
2015.'
date_created: 2018-03-23T14:09:33Z
date_updated: 2023-09-26T13:31:01Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/2675743.2771824
language:
- iso: eng
publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)
publisher: ACM
quality_controlled: '1'
status: public
title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis
and Optimization of a Memory-Bounded Algorithm
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1781'
abstract:
- lang: eng
text: In light of an increasing awareness of environmental challenges, extensive
research is underway to develop new light-weight materials. A problem arising
with these materials is their increased response to vibration. This can be solved
using a new composite material that contains embedded hollow spheres that are
partially filled with particles. Progress on the adaptation of molecular dynamics
towards a particle-based numerical simulation of this material is reported. This
includes the treatment of specific boundary conditions and the adaption of the
force computation. First results are presented that showcase the damping properties
of such particle-filled spheres in a bouncing experiment.
author:
- first_name: Tobias
full_name: Steinle, Tobias
last_name: Steinle
- first_name: Jadran
full_name: Vrabec, Jadran
last_name: Vrabec
- first_name: Andrea
full_name: Walther, Andrea
last_name: Walther
citation:
ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior
of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder
JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC).
Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19'
apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of
the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang,
R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization
of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing.
https://doi.org/10.1007/978-3-319-09063-4_19
bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19},
booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)},
publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec,
Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and
Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243}
}'
chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling,
Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg
Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer
International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.
ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping
Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation
and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.
mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled
Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), edited by Hans Georg Bock et al., Springer International Publishing,
2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.
short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher,
J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), Springer International Publishing, 2014, pp. 233–243.'
date_created: 2018-03-26T13:47:16Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '104'
- _id: '155'
doi: 10.1007/978-3-319-09063-4_19
editor:
- first_name: Hans Georg
full_name: Bock, Hans Georg
last_name: Bock
- first_name: Xuan Phu
full_name: Hoang, Xuan Phu
last_name: Hoang
- first_name: Rolf
full_name: Rannacher, Rolf
last_name: Rannacher
- first_name: Johannes P.
full_name: Schlöder, Johannes P.
last_name: Schlöder
page: 233-243
publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)
publication_identifier:
isbn:
- 978-3-319-09063-4
publisher: Springer International Publishing
status: public
title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '1782'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science.
Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2'
apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in
Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25).
Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2'
bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture
Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2},
number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer},
author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25},
collection={Lecture Notes in Computer Science} }'
chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection
in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25.
Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.'
ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf.
on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games
(CG), Springer, Switzerland, 2014, pp. 14–25.'
date_created: 2018-03-26T13:50:37Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1007/978-3-319-09165-5_2
issue: '8427'
page: 14-25
place: Switzerland
publication: Proc. Conf. on Computers and Games (CG)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: On Semeai Detection in Monte-Carlo Go
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1784'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Viktor
full_name: Gottfried, Viktor
last_name: Gottfried
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download
Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture
and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97.
doi:10.1109/NAS.2013.18'
apa: 'Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming
the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer
Society. https://doi.org/10.1109/NAS.2013.18'
bibtex: '@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington
DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers},
DOI={10.1109/NAS.2013.18}, booktitle={Proc.
IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE
Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor
and Brinkmann, André}, year={2013}, pages={88–97} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD:
Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int.
Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC,
USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.'
ieee: 'J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the
Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS), 2013, pp. 88–97.'
mla: 'Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data
Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS),
IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.'
short: 'J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington
DC, USA, 2013, pp. 88–97.'
date_created: 2018-03-26T14:43:38Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
doi: 10.1109/NAS.2013.18
page: 88-97
place: Washington DC, USA
publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)
publisher: IEEE Computer Society
status: public
title: 'MCD: Overcoming the Data Download Bottleneck in Data Centers'
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1788'
author:
- first_name: Petra
full_name: Berenbrink, Petra
last_name: Berenbrink
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tom
full_name: Friedetzky, Tom
last_name: Friedetzky
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Lars
full_name: Nagel, Lars
last_name: Nagel
citation:
ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing
Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148'
apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L.
(2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148
bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing
Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky,
Tom and Meister, Dirk and Nagel, Lars}, year={2013} }'
chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars
Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148.
ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing
Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013.
mla: Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE,
2013, doi:10.1109/IPDPSW.2013.148.
short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.'
date_created: 2018-03-26T14:52:56Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
doi: 10.1109/IPDPSW.2013.148
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publisher: IEEE
status: public
title: Distributing Storage in Cloud Environments
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1793'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
citation:
ama: 'Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication
Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST).
USENIX Association; 2013:175-182.'
apa: Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in
Data Deduplication Systems. In Proc. USENIX Conference on File and Storage
Technologies (FAST) (pp. 175–182). USENIX Association.
bibtex: '@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression
in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and
Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister,
Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }'
chicago: Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in
Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage
Technologies (FAST), 175–82. USENIX Association, 2013.
ieee: D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication
Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST),
2013, pp. 175–182.
mla: Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.”
Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX
Association, 2013, pp. 175–82.
short: 'D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and
Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.'
date_created: 2018-03-26T15:16:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
page: 175-182
publication: Proc. USENIX Conference on File and Storage Technologies (FAST)
publisher: USENIX Association
status: public
title: File Recipe Compression in Data Deduplication Systems
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '505'
abstract:
- lang: eng
text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT
services that will be provided by assembling modular software components available
on world-wide markets. After suitable components have been found, they are automatically
integrated, configured and brought to execution in an On-The-Fly Compute Center.
We envision that these future compute centers will continue to leverage three
current trends in large scale computing which are an increasing amount of parallel
processing, a trend to use heterogeneous computing resources, and—in the light
of rising energy cost—energy-efficiency as a primary goal in the design and operation
of computing systems. In this paper, we point out three research challenges and
our current work in these areas.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
citation:
ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings
of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous
Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232'
apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide,
F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232'
bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232},
booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus
and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide,
Friedhelm}, year={2013} }'
chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm
Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology
for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.'
ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.'
mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for
Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.'
short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in:
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS), IEEE, 2013.'
date_created: 2017-10-17T12:42:30Z
date_updated: 2023-09-26T13:38:20Z
ddc:
- '040'
department:
- _id: '63'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISORC.2013.6913232
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T13:38:56Z
date_updated: 2018-03-15T13:38:56Z
file_id: '1308'
file_name: 505-Plessl13_seus.pdf
file_size: 1040834
relation: main_file
success: 1
file_date_updated: 2018-03-15T13:38:56Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services'
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '1787'
author:
- first_name: Tim
full_name: Suess, Tim
last_name: Suess
- first_name: Andrew
full_name: Schoenrock, Andrew
last_name: Schoenrock
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the
Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136'
apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro
Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel
and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136
bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington,
DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer},
DOI={10.1109/IPDPSW.2013.136},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and
Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }'
chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl.
“Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int.
Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington,
DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.'
ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining
on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.'
mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”
Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW),
IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.
short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society,
Washington, DC, USA, 2013, pp. 64–73.'
date_created: 2018-03-26T14:51:05Z
date_updated: 2023-09-26T13:38:05Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
- _id: '63'
doi: 10.1109/IPDPSW.2013.136
language:
- iso: eng
page: 64-73
place: Washington, DC, USA
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publication_identifier:
isbn:
- 978-0-7695-4979-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '2097'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial
matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology
(ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125'
apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of
an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field
Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation
of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation
of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on
Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012.
https://doi.org/10.1109/FPT.2012.6412125.
ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate
polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable
Technology (ICFPT), 2012, pp. 135–140.
mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an
Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2012, pp. 135–140.'
date_created: 2018-03-29T14:34:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/FPT.2012.6412125
page: 135-140
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: FPGA-based design and implementation of an approximate polynomial matrix EVD
algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2098'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Tim
full_name: Hartung, Tim
last_name: Hartung
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device.
In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS).
IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34'
apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2
Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems
(ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34'
bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2
Split Block Device}, DOI={10.1109/ICPADS.2012.34},
booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)},
publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and
Brinkmann, André}, year={2012}, pages={181–188} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB:
Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed
Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.'
ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block
Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS),
2012, pp. 181–188.'
mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int.
Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88,
doi:10.1109/ICPADS.2012.34.'
short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.'
date_created: 2018-03-29T14:40:04Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ICPADS.2012.34
page: 181-188
publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)
publisher: IEEE
status: public
title: 'ESB: Ext2 Split Block Device'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2099'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Michael
full_name: Kuhn, Michael
last_name: Kuhn
- first_name: Julian
full_name: Kunkel, Julian
last_name: Kunkel
- first_name: Toni
full_name: Cortes, Toni
last_name: Cortes
citation:
ama: 'Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data
Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing
(SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14'
apa: 'Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes,
T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int.
Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer
Society. https://doi.org/10.1109/SC.2012.14'
bibtex: '@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los
Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems},
DOI={10.1109/SC.2012.14}, booktitle={Proc.
Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister,
Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian
and Cortes, Toni}, year={2012}, pages={7:1-7:11} }'
chicago: 'Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel,
and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc.
Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer
Society, 2012. https://doi.org/10.1109/SC.2012.14.'
ieee: D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A
Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on
Supercomputing (SC), 2012, pp. 7:1-7:11.
mla: Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.”
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp.
7:1-7:11, doi:10.1109/SC.2012.14.
short: 'D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in:
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos,
CA, USA, 2012, pp. 7:1-7:11.'
date_created: 2018-03-29T14:41:55Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/SC.2012.14
page: 7:1-7:11
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on Supercomputing (SC)
publisher: IEEE Computer Society
status: public
title: A Study on Data Deduplication in HPC Storage Systems
type: conference
user_id: '24135'
year: '2012'
...