---
_id: '46195'
author:
- first_name: Martin
full_name: Karp, Martin
last_name: Karp
- first_name: Artur
full_name: Podobas, Artur
last_name: Podobas
- first_name: Niclas
full_name: Jansson, Niclas
last_name: Jansson
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Philipp
full_name: Schlatter, Philipp
last_name: Schlatter
- first_name: Stefano
full_name: Markidis, Stefano
last_name: Markidis
citation:
ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods
on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.
In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS).
IEEE; 2021. doi:10.1109/ipdps49936.2021.00116'
apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P.,
& Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE
International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116'
bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021,
title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays :
Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116},
booktitle={2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson,
Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis,
Stefano}, year={2021} }'
chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian
Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element
Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future
Projection.” In 2021 IEEE International Parallel and Distributed Processing
Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.'
ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.'
mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE
International Parallel and Distributed Processing Symposium (IPDPS), IEEE,
2021, doi:10.1109/ipdps49936.2021.00116.'
short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S.
Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS), IEEE, 2021.'
date_created: 2023-07-28T12:04:27Z
date_updated: 2023-07-28T12:05:15Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/ipdps49936.2021.00116
language:
- iso: eng
publication: 2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays
: Implementation, Evaluation, and Future Projection'
type: conference
user_id: '3145'
year: '2021'
...
---
_id: '29937'
author:
- first_name: Martin
full_name: Karp, Martin
last_name: Karp
- first_name: Artur
full_name: Podobas, Artur
last_name: Podobas
- first_name: Niclas
full_name: Jansson, Niclas
last_name: Jansson
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Philipp
full_name: Schlatter, Philipp
last_name: Schlatter
- first_name: Stefano
full_name: Markidis, Stefano
last_name: Markidis
citation:
ama: 'Karp M, Podobas A, Jansson N, et al. High-Performance Spectral Element Methods
on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection.
In: 2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS).
IEEE; 2021. doi:10.1109/ipdps49936.2021.00116'
apa: 'Karp, M., Podobas, A., Jansson, N., Kenter, T., Plessl, C., Schlatter, P.,
& Markidis, S. (2021). High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection. 2021 IEEE
International Parallel and Distributed Processing Symposium (IPDPS). https://doi.org/10.1109/ipdps49936.2021.00116'
bibtex: '@inproceedings{Karp_Podobas_Jansson_Kenter_Plessl_Schlatter_Markidis_2021,
title={High-Performance Spectral Element Methods on Field-Programmable Gate Arrays :
Implementation, Evaluation, and Future Projection}, DOI={10.1109/ipdps49936.2021.00116},
booktitle={2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS)}, publisher={IEEE}, author={Karp, Martin and Podobas, Artur and Jansson,
Niclas and Kenter, Tobias and Plessl, Christian and Schlatter, Philipp and Markidis,
Stefano}, year={2021} }'
chicago: 'Karp, Martin, Artur Podobas, Niclas Jansson, Tobias Kenter, Christian
Plessl, Philipp Schlatter, and Stefano Markidis. “High-Performance Spectral Element
Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future
Projection.” In 2021 IEEE International Parallel and Distributed Processing
Symposium (IPDPS). IEEE, 2021. https://doi.org/10.1109/ipdps49936.2021.00116.'
ieee: 'M. Karp et al., “High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection,” 2021, doi: 10.1109/ipdps49936.2021.00116.'
mla: 'Karp, Martin, et al. “High-Performance Spectral Element Methods on Field-Programmable
Gate Arrays : Implementation, Evaluation, and Future Projection.” 2021 IEEE
International Parallel and Distributed Processing Symposium (IPDPS), IEEE,
2021, doi:10.1109/ipdps49936.2021.00116.'
short: 'M. Karp, A. Podobas, N. Jansson, T. Kenter, C. Plessl, P. Schlatter, S.
Markidis, in: 2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS), IEEE, 2021.'
date_created: 2022-02-21T14:26:37Z
date_updated: 2024-01-22T09:59:13Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/ipdps49936.2021.00116
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2021 IEEE International Parallel and Distributed Processing Symposium
(IPDPS)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'High-Performance Spectral Element Methods on Field-Programmable Gate Arrays
: Implementation, Evaluation, and Future Projection'
type: conference
user_id: '3145'
year: '2021'
...
---
_id: '32242'
abstract:
- lang: eng
text: "We consider a resource-aware variant of the classical multi-armed bandit\r\nproblem:
In each round, the learner selects an arm and determines a resource\r\nlimit.
It then observes a corresponding (random) reward, provided the (random)\r\namount
of consumed resources remains below the limit. Otherwise, the\r\nobservation is
censored, i.e., no reward is obtained. For this problem setting,\r\nwe introduce
a measure of regret, which incorporates the actual amount of\r\nallocated resources
of each learning round as well as the optimality of\r\nrealizable rewards. Thus,
to minimize regret, the learner needs to set a\r\nresource limit and choose an
arm in such a way that the chance to realize a\r\nhigh reward within the predefined
resource limit is high, while the resource\r\nlimit itself should be kept as low
as possible. We derive the theoretical lower\r\nbound on the cumulative regret
and propose a learning algorithm having a regret\r\nupper bound that matches the
lower bound. In a simulation study, we show that\r\nour learning algorithm outperforms
straightforward extensions of standard\r\nmulti-armed bandit algorithms."
author:
- first_name: Viktor
full_name: Bengs, Viktor
last_name: Bengs
- first_name: Eyke
full_name: Hüllermeier, Eyke
last_name: Hüllermeier
citation:
ama: Bengs V, Hüllermeier E. Multi-Armed Bandits with Censored Consumption of Resources.
arXiv:201100813. Published online 2020.
apa: Bengs, V., & Hüllermeier, E. (2020). Multi-Armed Bandits with Censored
Consumption of Resources. In arXiv:2011.00813.
bibtex: '@article{Bengs_Hüllermeier_2020, title={Multi-Armed Bandits with Censored
Consumption of Resources}, journal={arXiv:2011.00813}, author={Bengs, Viktor and
Hüllermeier, Eyke}, year={2020} }'
chicago: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored
Consumption of Resources.” ArXiv:2011.00813, 2020.
ieee: V. Bengs and E. Hüllermeier, “Multi-Armed Bandits with Censored Consumption
of Resources,” arXiv:2011.00813. 2020.
mla: Bengs, Viktor, and Eyke Hüllermeier. “Multi-Armed Bandits with Censored Consumption
of Resources.” ArXiv:2011.00813, 2020.
short: V. Bengs, E. Hüllermeier, ArXiv:2011.00813 (2020).
date_created: 2022-06-28T07:26:54Z
date_updated: 2022-06-28T07:27:19Z
department:
- _id: '27'
external_id:
arxiv:
- '2011.00813'
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: arXiv:2011.00813
status: public
title: Multi-Armed Bandits with Censored Consumption of Resources
type: preprint
user_id: '15278'
year: '2020'
...
---
_id: '16898'
abstract:
- lang: eng
text: "Electronic structure calculations based on density-functional theory (DFT)\r\nrepresent
a significant part of today's HPC workloads and pose high demands on\r\nhigh-performance
computing resources. To perform these quantum-mechanical DFT\r\ncalculations on
complex large-scale systems, so-called linear scaling methods\r\ninstead of conventional
cubic scaling methods are required. In this work, we\r\ntake up the idea of the
submatrix method and apply it to the DFT computations\r\nin the software package
CP2K. For that purpose, we transform the underlying\r\nnumeric operations on distributed,
large, sparse matrices into computations on\r\nlocal, much smaller and nearly
dense matrices. This allows us to exploit the\r\nfull floating-point performance
of modern CPUs and to make use of dedicated\r\naccelerator hardware, where performance
has been limited by memory bandwidth\r\nbefore. We demonstrate both functionality
and performance of our implementation\r\nand show how it can be accelerated with
GPUs and FPGAs."
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Robert
full_name: Schade, Robert
id: '75963'
last_name: Schade
orcid: 0000-0002-6268-539
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Lass M, Schade R, Kühne T, Plessl C. A Submatrix-Based Method for Approximate
Matrix Function Evaluation in the Quantum Chemistry Code CP2K. In: Proc. International
Conference for High Performance Computing, Networking, Storage and Analysis (SC).
IEEE Computer Society; 2020:1127-1140. doi:10.1109/SC41405.2020.00084'
apa: Lass, M., Schade, R., Kühne, T., & Plessl, C. (2020). A Submatrix-Based
Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code
CP2K. Proc. International Conference for High Performance Computing, Networking,
Storage and Analysis (SC), 1127–1140. https://doi.org/10.1109/SC41405.2020.00084
bibtex: '@inproceedings{Lass_Schade_Kühne_Plessl_2020, place={Los Alamitos, CA,
USA}, title={A Submatrix-Based Method for Approximate Matrix Function Evaluation
in the Quantum Chemistry Code CP2K}, DOI={10.1109/SC41405.2020.00084},
booktitle={Proc. International Conference for High Performance Computing, Networking,
Storage and Analysis (SC)}, publisher={IEEE Computer Society}, author={Lass, Michael
and Schade, Robert and Kühne, Thomas and Plessl, Christian}, year={2020}, pages={1127–1140}
}'
chicago: 'Lass, Michael, Robert Schade, Thomas Kühne, and Christian Plessl. “A Submatrix-Based
Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code
CP2K.” In Proc. International Conference for High Performance Computing, Networking,
Storage and Analysis (SC), 1127–40. Los Alamitos, CA, USA: IEEE Computer Society,
2020. https://doi.org/10.1109/SC41405.2020.00084.'
ieee: 'M. Lass, R. Schade, T. Kühne, and C. Plessl, “A Submatrix-Based Method for
Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K,” in
Proc. International Conference for High Performance Computing, Networking,
Storage and Analysis (SC), Atlanta, GA, US, 2020, pp. 1127–1140, doi: 10.1109/SC41405.2020.00084.'
mla: Lass, Michael, et al. “A Submatrix-Based Method for Approximate Matrix Function
Evaluation in the Quantum Chemistry Code CP2K.” Proc. International Conference
for High Performance Computing, Networking, Storage and Analysis (SC), IEEE
Computer Society, 2020, pp. 1127–40, doi:10.1109/SC41405.2020.00084.
short: 'M. Lass, R. Schade, T. Kühne, C. Plessl, in: Proc. International Conference
for High Performance Computing, Networking, Storage and Analysis (SC), IEEE Computer
Society, Los Alamitos, CA, USA, 2020, pp. 1127–1140.'
conference:
location: Atlanta, GA, US
name: 'SC20: International Conference for High Performance Computing, Networking,
Storage and Analysis (SC)'
date_created: 2020-04-28T14:44:21Z
date_updated: 2023-08-02T14:55:59Z
department:
- _id: '27'
- _id: '518'
- _id: '304'
doi: 10.1109/SC41405.2020.00084
external_id:
arxiv:
- '2004.10811'
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9355245
page: 1127-1140
place: Los Alamitos, CA, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
- _id: '32'
grant_number: PL 595/2-1 / 320898746
name: Performance and Efficiency in HPC with Custom Computing
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proc. International Conference for High Performance Computing, Networking,
Storage and Analysis (SC)
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: A Submatrix-Based Method for Approximate Matrix Function Evaluation in the
Quantum Chemistry Code CP2K
type: conference
user_id: '75963'
year: '2020'
...
---
_id: '21632'
abstract:
- lang: eng
text: FPGAs have found increasing adoption in data center applications since a new
generation of high-level tools have become available which noticeably reduce development
time for FPGA accelerators and still provide high-quality results. There is, however,
no high-level benchmark suite available, which specifically enables a comparison
of FPGA architectures, programming tools, and libraries for HPC applications.
To fill this gap, we have developed an OpenCL-based open-source implementation
of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve
to analyze the current capabilities of FPGA devices, cards, and development tool
flows, track progress over time, and point out specific difficulties for FPGA
acceleration in the HPC domain. Additionally, the benchmark documents proven performance
optimization patterns. We will continue optimizing and porting the benchmark for
new generations of FPGAs and design tools and encourage active participation to
create a valuable tool for the community. To fill this gap, we have developed
an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx
and Intel FPGAs. This benchmark can serve to analyze the current capabilities
of FPGA devices, cards, and development tool flows, track progress over time,
and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally,
the benchmark documents proven performance optimization patterns. We will continue
optimizing and porting the benchmark for new generations of FPGAs and design tools
and encourage active participation to create a valuable tool for the community.
author:
- first_name: Marius
full_name: Meyer, Marius
id: '40778'
last_name: Meyer
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Meyer M, Kenter T, Plessl C. Evaluating FPGA Accelerator Performance with
a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark
Suite. In: 2020 IEEE/ACM International Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC). ; 2020. doi:10.1109/h2rc51942.2020.00007'
apa: Meyer, M., Kenter, T., & Plessl, C. (2020). Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite. 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC). https://doi.org/10.1109/h2rc51942.2020.00007
bibtex: '@inproceedings{Meyer_Kenter_Plessl_2020, title={Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite}, DOI={10.1109/h2rc51942.2020.00007},
booktitle={2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)}, author={Meyer, Marius and Kenter, Tobias and
Plessl, Christian}, year={2020} }'
chicago: Meyer, Marius, Tobias Kenter, and Christian Plessl. “Evaluating FPGA Accelerator
Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the
HPCChallenge Benchmark Suite.” In 2020 IEEE/ACM International Workshop on Heterogeneous
High-Performance Reconfigurable Computing (H2RC), 2020. https://doi.org/10.1109/h2rc51942.2020.00007.
ieee: 'M. Meyer, T. Kenter, and C. Plessl, “Evaluating FPGA Accelerator Performance
with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge
Benchmark Suite,” 2020, doi: 10.1109/h2rc51942.2020.00007.'
mla: Meyer, Marius, et al. “Evaluating FPGA Accelerator Performance with a Parameterized
OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite.”
2020 IEEE/ACM International Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC), 2020, doi:10.1109/h2rc51942.2020.00007.
short: 'M. Meyer, T. Kenter, C. Plessl, in: 2020 IEEE/ACM International Workshop
on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2020.'
date_created: 2021-04-16T10:17:22Z
date_updated: 2023-09-26T11:42:53Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/h2rc51942.2020.00007
keyword:
- FPGA
- OpenCL
- High Level Synthesis
- HPC benchmarking
language:
- iso: eng
main_file_link:
- url: https://ieeexplore.ieee.org/document/9306963
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2020 IEEE/ACM International Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)
publication_identifier:
isbn:
- '9781665415927'
publication_status: published
quality_controlled: '1'
related_material:
link:
- description: Official repository of the benchmark suite on GitHub
relation: supplementary_material
url: https://github.com/pc2/HPCC_FPGA
status: public
title: Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation
of Selected Benchmarks of the HPCChallenge Benchmark Suite
type: conference
user_id: '15278'
year: '2020'
...
---
_id: '15478'
abstract:
- lang: eng
text: Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads
since the Stratix 10 product line introduces devices with a large number of DSP
and memory blocks. The high level synthesis of OpenCL codes can play a fundamental
role for FPGAs in HPC, because it allows to implement different designs with lower
development effort compared to hand optimized HDL. However, Stratix 10 cards are
still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation
of designs with thousands of concurrent arithmetic operations often suffers from
place and route problems that limit the maximum frequency or entirely prevent
a successful synthesis. In order to overcome these issues for the implementation
of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm
with regard to its efficient synthesis within the FPGA logic. We obtain a two-level
block algorithm, where the lower level sub-matrices are multiplied using our Cannon's
algorithm implementation. Following this design approach with multiple compute
units, we are able to get maximum frequencies close to and above 300 MHz with
high utilization of DSP and memory blocks. This allows for performance results
above 1 TeraFLOPS.
author:
- first_name: Paolo
full_name: Gorlani, Paolo
id: '72045'
last_name: Gorlani
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Gorlani P, Kenter T, Plessl C. OpenCL Implementation of Cannon’s Matrix Multiplication
Algorithm on Intel Stratix 10 FPGAs. In: Proceedings of the International Conference
on Field-Programmable Technology (FPT). IEEE; 2019. doi:10.1109/ICFPT47387.2019.00020'
apa: Gorlani, P., Kenter, T., & Plessl, C. (2019). OpenCL Implementation of
Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. In Proceedings
of the International Conference on Field-Programmable Technology (FPT). IEEE.
https://doi.org/10.1109/ICFPT47387.2019.00020
bibtex: '@inproceedings{Gorlani_Kenter_Plessl_2019, title={OpenCL Implementation
of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs}, DOI={10.1109/ICFPT47387.2019.00020},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Gorlani, Paolo and Kenter, Tobias and Plessl,
Christian}, year={2019} }'
chicago: Gorlani, Paolo, Tobias Kenter, and Christian Plessl. “OpenCL Implementation
of Cannon’s Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT). IEEE,
2019. https://doi.org/10.1109/ICFPT47387.2019.00020.
ieee: P. Gorlani, T. Kenter, and C. Plessl, “OpenCL Implementation of Cannon’s Matrix
Multiplication Algorithm on Intel Stratix 10 FPGAs,” in Proceedings of the
International Conference on Field-Programmable Technology (FPT), 2019.
mla: Gorlani, Paolo, et al. “OpenCL Implementation of Cannon’s Matrix Multiplication
Algorithm on Intel Stratix 10 FPGAs.” Proceedings of the International Conference
on Field-Programmable Technology (FPT), IEEE, 2019, doi:10.1109/ICFPT47387.2019.00020.
short: 'P. Gorlani, T. Kenter, C. Plessl, in: Proceedings of the International Conference
on Field-Programmable Technology (FPT), IEEE, 2019.'
conference:
name: International Conference on Field-Programmable Technology (FPT)
date_created: 2020-01-09T12:54:48Z
date_updated: 2022-01-06T06:52:26Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
doi: 10.1109/ICFPT47387.2019.00020
file:
- access_level: closed
content_type: application/pdf
creator: plessl
date_created: 2020-01-09T12:53:57Z
date_updated: 2020-01-09T12:53:57Z
file_id: '15479'
file_name: gorlani19_fpt.pdf
file_size: 250559
relation: main_file
success: 1
file_date_updated: 2020-01-09T12:53:57Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '33'
grant_number: 01|H16005
name: HighPerMeshes
- _id: '32'
grant_number: PL 595/2-1
name: Performance and Efficiency in HPC with Custom Computing
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel
Stratix 10 FPGAs
type: conference
user_id: '3145'
year: '2019'
...
---
_id: '22'
abstract:
- lang: eng
text: This paper describes a data structure and a heuristic to plan and map arbitrary
resources in complex combinations while applying time dependent constraints. The
approach is used in the planning based workload manager OpenCCS at the Paderborn
Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with
up to 10000 cores. We also show performance results derived from four years of
operation.
author:
- first_name: Axel
full_name: Keller, Axel
id: '15274'
last_name: Keller
citation:
ama: 'Keller A. A Data Structure for Planning Based Workload Management of Heterogeneous
HPC Systems. In: Klusáček D, Cirne W, Desai N, eds. Proc. Workshop on Job Scheduling
Strategies for Parallel Processing (JSSPP). Vol 10773. Lecture Notes in Computer
Science. Springer; 2018:132-151. doi:10.1007/978-3-319-77398-8_8'
apa: 'Keller, A. (2018). A Data Structure for Planning Based Workload Management
of Heterogeneous HPC Systems. In D. Klusáček, W. Cirne, & N. Desai (Eds.),
Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)
(Vol. 10773, pp. 132–151). Orlando, FL, USA: Springer. https://doi.org/10.1007/978-3-319-77398-8_8'
bibtex: '@inproceedings{Keller_2018, series={Lecture Notes in Computer Science},
title={A Data Structure for Planning Based Workload Management of Heterogeneous
HPC Systems}, volume={10773}, DOI={10.1007/978-3-319-77398-8_8},
booktitle={Proc. Workshop on Job Scheduling Strategies for Parallel Processing
(JSSPP)}, publisher={Springer}, author={Keller, Axel}, editor={Klusáček, D. and
Cirne, W. and Desai, N.Editors}, year={2018}, pages={132–151}, collection={Lecture
Notes in Computer Science} }'
chicago: Keller, Axel. “A Data Structure for Planning Based Workload Management
of Heterogeneous HPC Systems.” In Proc. Workshop on Job Scheduling Strategies
for Parallel Processing (JSSPP), edited by D. Klusáček, W. Cirne, and N. Desai,
10773:132–51. Lecture Notes in Computer Science. Springer, 2018. https://doi.org/10.1007/978-3-319-77398-8_8.
ieee: A. Keller, “A Data Structure for Planning Based Workload Management of Heterogeneous
HPC Systems,” in Proc. Workshop on Job Scheduling Strategies for Parallel Processing
(JSSPP), Orlando, FL, USA, 2018, vol. 10773, pp. 132–151.
mla: Keller, Axel. “A Data Structure for Planning Based Workload Management of Heterogeneous
HPC Systems.” Proc. Workshop on Job Scheduling Strategies for Parallel Processing
(JSSPP), edited by D. Klusáček et al., vol. 10773, Springer, 2018, pp. 132–51,
doi:10.1007/978-3-319-77398-8_8.
short: 'A. Keller, in: D. Klusáček, W. Cirne, N. Desai (Eds.), Proc. Workshop on
Job Scheduling Strategies for Parallel Processing (JSSPP), Springer, 2018, pp.
132–151.'
conference:
end_date: 2017-06-02
location: Orlando, FL, USA
name: 21st Workshop on Job Scheduling Strategies for Parallel Processing
start_date: 2017-06-02
date_created: 2017-07-25T14:54:08Z
date_updated: 2022-01-06T06:55:22Z
department:
- _id: '27'
doi: 10.1007/978-3-319-77398-8_8
editor:
- first_name: D.
full_name: Klusáček, D.
last_name: Klusáček
- first_name: W.
full_name: Cirne, W.
last_name: Cirne
- first_name: N.
full_name: Desai, N.
last_name: Desai
intvolume: ' 10773'
keyword:
- Scheduling Planning Mapping Workload management
language:
- iso: eng
page: 132-151
publication: Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP)
publication_identifier:
isbn:
- 978-3-319-77398-8
- 978-3-319-77397-1
publication_status: published
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: A Data Structure for Planning Based Workload Management of Heterogeneous HPC
Systems
type: conference
user_id: '15274'
volume: 10773
year: '2018'
...
---
_id: '1588'
abstract:
- lang: eng
text: The exploration of FPGAs as accelerators for scientific simulations has so
far mostly been focused on small kernels of methods working on regular data structures,
for example in the form of stencil computations for finite difference methods.
In computational sciences, often more advanced methods are employed that promise
better stability, convergence, locality and scaling. Unstructured meshes are shown
to be more effective and more accurate, compared to regular grids, in representing
computation domains of various shapes. Using unstructured meshes, the discontinuous
Galerkin method preserves the ability to perform explicit local update operations
for simulations in the time domain. In this work, we investigate FPGAs as target
platform for an implementation of the nodal discontinuous Galerkin method to find
time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing
data reuse and fitting constant coefficients into suitably partitioned on-chip
memory, high computational intensity allows us to implement and feed wide data
paths with hundreds of floating point operators. By decoupling off-chip memory
accesses from the computations, high memory bandwidth can be sustained, even for
the irregular access pattern required by parts of the application. Using the Intel/Altera
OpenCL SDK for FPGAs, we present different implementation variants for different
polynomial orders of the method. In different phases of the algorithm, either
computational or bandwidth limits of the Arria 10 platform are almost reached,
thus outperforming a highly multithreaded CPU implementation by around 2x.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gopinath
full_name: Mahale, Gopinath
last_name: Mahale
- first_name: Samer
full_name: Alhaddad, Samer
id: '42456'
last_name: Alhaddad
- first_name: Yevgen
full_name: Grynko, Yevgen
id: '26059'
last_name: Grynko
- first_name: Christian
full_name: Schmitt, Christian
last_name: Schmitt
- first_name: Ayesha
full_name: Afzal, Ayesha
last_name: Afzal
- first_name: Frank
full_name: Hannig, Frank
last_name: Hannig
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Mahale G, Alhaddad S, et al. OpenCL-based FPGA Design to Accelerate
the Nodal Discontinuous Galerkin Method for Unstructured Meshes. In: Proc.
Int. Symp. on Field-Programmable Custom Computing Machines (FCCM). IEEE; 2018.
doi:10.1109/FCCM.2018.00037'
apa: Kenter, T., Mahale, G., Alhaddad, S., Grynko, Y., Schmitt, C., Afzal, A., Hannig,
F., Förstner, J., & Plessl, C. (2018). OpenCL-based FPGA Design to Accelerate
the Nodal Discontinuous Galerkin Method for Unstructured Meshes. Proc. Int.
Symp. on Field-Programmable Custom Computing Machines (FCCM). Proc. Int. Symp.
on Field-Programmable Custom Computing Machines (FCCM). https://doi.org/10.1109/FCCM.2018.00037
bibtex: '@inproceedings{Kenter_Mahale_Alhaddad_Grynko_Schmitt_Afzal_Hannig_Förstner_Plessl_2018,
title={OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin
Method for Unstructured Meshes}, DOI={10.1109/FCCM.2018.00037},
booktitle={Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Kenter, Tobias and Mahale, Gopinath and Alhaddad, Samer
and Grynko, Yevgen and Schmitt, Christian and Afzal, Ayesha and Hannig, Frank
and Förstner, Jens and Plessl, Christian}, year={2018} }'
chicago: Kenter, Tobias, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian
Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, and Christian Plessl. “OpenCL-Based
FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured
Meshes.” In Proc. Int. Symp. on Field-Programmable Custom Computing Machines
(FCCM). IEEE, 2018. https://doi.org/10.1109/FCCM.2018.00037.
ieee: 'T. Kenter et al., “OpenCL-based FPGA Design to Accelerate the Nodal
Discontinuous Galerkin Method for Unstructured Meshes,” presented at the Proc.
Int. Symp. on Field-Programmable Custom Computing Machines (FCCM), 2018, doi:
10.1109/FCCM.2018.00037.'
mla: Kenter, Tobias, et al. “OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous
Galerkin Method for Unstructured Meshes.” Proc. Int. Symp. on Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2018, doi:10.1109/FCCM.2018.00037.
short: 'T. Kenter, G. Mahale, S. Alhaddad, Y. Grynko, C. Schmitt, A. Afzal, F. Hannig,
J. Förstner, C. Plessl, in: Proc. Int. Symp. on Field-Programmable Custom Computing
Machines (FCCM), IEEE, 2018.'
conference:
name: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
date_created: 2018-03-22T10:48:01Z
date_updated: 2023-09-26T11:47:52Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '61'
doi: 10.1109/FCCM.2018.00037
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T14:45:05Z
date_updated: 2018-11-02T14:45:05Z
file_id: '5282'
file_name: 08457652.pdf
file_size: 269130
relation: main_file
success: 1
file_date_updated: 2018-11-02T14:45:05Z
has_accepted_license: '1'
keyword:
- tet_topic_hpc
language:
- iso: eng
project:
- _id: '33'
grant_number: 01|H16005A
name: HighPerMeshes
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
publication: Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method
for Unstructured Meshes
type: conference
user_id: '15278'
year: '2018'
...
---
_id: '1590'
abstract:
- lang: eng
text: "We present the submatrix method, a highly parallelizable method for the approximate
calculation of inverse p-th roots of large sparse symmetric matrices which are
required in different scientific applications. Following the idea of Approximate
Computing, we allow imprecision in the final result in order to utilize the sparsity
of the input matrix and to allow massively parallel execution. For an n x n matrix,
the proposed algorithm allows to distribute the calculations over n nodes with
only little communication overhead. The result matrix exhibits the same sparsity
pattern as the input matrix, allowing for efficient reuse of allocated data structures.\r\n\r\nWe
evaluate the algorithm with respect to the error that it introduces into calculated
results, as well as its performance and scalability. We demonstrate that the error
is relatively limited for well-conditioned matrices and that results are still
valuable for error-resilient applications like preconditioning even for ill-conditioned
matrices. We discuss the execution time and scaling of the algorithm on a theoretical
level and present a distributed implementation of the algorithm using MPI and
OpenMP. We demonstrate the scalability of this implementation by running it on
a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup
of 665x compared to single-threaded execution."
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Stephan
full_name: Mohr, Stephan
last_name: Mohr
- first_name: Hendrik
full_name: Wiebeler, Hendrik
last_name: Wiebeler
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Lass M, Mohr S, Wiebeler H, Kühne T, Plessl C. A Massively Parallel Algorithm
for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices.
In: Proc. Platform for Advanced Scientific Computing (PASC) Conference.
ACM; 2018. doi:10.1145/3218176.3218231'
apa: Lass, M., Mohr, S., Wiebeler, H., Kühne, T., & Plessl, C. (2018). A Massively
Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large
Sparse Matrices. Proc. Platform for Advanced Scientific Computing (PASC) Conference.
Platform for Advanced Scientific Computing Conference (PASC), Basel, Switzerland.
https://doi.org/10.1145/3218176.3218231
bibtex: '@inproceedings{Lass_Mohr_Wiebeler_Kühne_Plessl_2018, place={New York, NY,
USA}, title={A Massively Parallel Algorithm for the Approximate Calculation of
Inverse p-th Roots of Large Sparse Matrices}, DOI={10.1145/3218176.3218231},
booktitle={Proc. Platform for Advanced Scientific Computing (PASC) Conference},
publisher={ACM}, author={Lass, Michael and Mohr, Stephan and Wiebeler, Hendrik
and Kühne, Thomas and Plessl, Christian}, year={2018} }'
chicago: 'Lass, Michael, Stephan Mohr, Hendrik Wiebeler, Thomas Kühne, and Christian
Plessl. “A Massively Parallel Algorithm for the Approximate Calculation of Inverse
P-Th Roots of Large Sparse Matrices.” In Proc. Platform for Advanced Scientific
Computing (PASC) Conference. New York, NY, USA: ACM, 2018. https://doi.org/10.1145/3218176.3218231.'
ieee: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, and C. Plessl, “A Massively Parallel
Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse
Matrices,” presented at the Platform for Advanced Scientific Computing Conference
(PASC), Basel, Switzerland, 2018, doi: 10.1145/3218176.3218231.'
mla: Lass, Michael, et al. “A Massively Parallel Algorithm for the Approximate Calculation
of Inverse P-Th Roots of Large Sparse Matrices.” Proc. Platform for Advanced
Scientific Computing (PASC) Conference, ACM, 2018, doi:10.1145/3218176.3218231.
short: 'M. Lass, S. Mohr, H. Wiebeler, T. Kühne, C. Plessl, in: Proc. Platform for
Advanced Scientific Computing (PASC) Conference, ACM, New York, NY, USA, 2018.'
conference:
end_date: 2018-07-04
location: Basel, Switzerland
name: Platform for Advanced Scientific Computing Conference (PASC)
start_date: 2018-07-02
date_created: 2018-03-22T10:53:01Z
date_updated: 2023-09-26T11:48:12Z
department:
- _id: '27'
- _id: '518'
- _id: '304'
doi: 10.1145/3218176.3218231
external_id:
arxiv:
- '1710.10899'
keyword:
- approximate computing
- linear algebra
- matrix inversion
- matrix p-th roots
- numeric algorithm
- parallel computing
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '32'
grant_number: PL 595/2-1 / 320898746
name: Performance and Efficiency in HPC with Custom Computing
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proc. Platform for Advanced Scientific Computing (PASC) Conference
publication_identifier:
isbn:
- 978-1-4503-5891-0/18/07
publisher: ACM
quality_controlled: '1'
status: public
title: A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th
Roots of Large Sparse Matrices
type: conference
user_id: '15278'
year: '2018'
...
---
_id: '1204'
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Vaz GF, Kenter T, Plessl C. Automated Code Acceleration Targeting
Heterogeneous OpenCL Devices. In: Proc. ACM SIGPLAN Symposium on Principles
and Practice of Parallel Programming (PPoPP). ACM; 2018. doi:10.1145/3178487.3178534'
apa: Riebler, H., Vaz, G. F., Kenter, T., & Plessl, C. (2018). Automated Code
Acceleration Targeting Heterogeneous OpenCL Devices. Proc. ACM SIGPLAN Symposium
on Principles and Practice of Parallel Programming (PPoPP). https://doi.org/10.1145/3178487.3178534
bibtex: '@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration
Targeting Heterogeneous OpenCL Devices}, DOI={10.1145/3178487.3178534},
booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel
Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin
Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }'
chicago: Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl.
“Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” In Proc.
ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP).
ACM, 2018. https://doi.org/10.1145/3178487.3178534.
ieee: 'H. Riebler, G. F. Vaz, T. Kenter, and C. Plessl, “Automated Code Acceleration
Targeting Heterogeneous OpenCL Devices,” 2018, doi: 10.1145/3178487.3178534.'
mla: Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous
OpenCL Devices.” Proc. ACM SIGPLAN Symposium on Principles and Practice of
Parallel Programming (PPoPP), ACM, 2018, doi:10.1145/3178487.3178534.
short: 'H. Riebler, G.F. Vaz, T. Kenter, C. Plessl, in: Proc. ACM SIGPLAN Symposium
on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.'
date_created: 2018-03-08T14:45:18Z
date_updated: 2023-09-26T11:47:23Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3178487.3178534
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T14:43:37Z
date_updated: 2018-11-02T14:43:37Z
file_id: '5281'
file_name: p417-riebler.pdf
file_size: 447769
relation: main_file
success: 1
file_date_updated: 2018-11-02T14:43:37Z
has_accepted_license: '1'
keyword:
- htrop
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
publication: Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
(PPoPP)
publication_identifier:
isbn:
- '9781450349826'
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: Automated Code Acceleration Targeting Heterogeneous OpenCL Devices
type: conference
user_id: '15278'
year: '2018'
...
---
_id: '1592'
abstract:
- lang: eng
text: Compared to classical HDL designs, generating FPGA with high-level synthesis
from an OpenCL specification promises easier exploration of different design alternatives
and, through ready-to-use infrastructure and common abstractions for host and
memory interfaces, easier portability between different FPGA families. In this
work, we evaluate the extent of this promise. To this end, we present a parameterized
FDTD implementation for photonic microcavity simulations. Our design can trade-off
different forms of parallelism and works for two independent OpenCL-based FPGA
design flows. Hence, we can target FPGAs from different vendors and different
FPGA families. We describe how we used pre-processor macros to achieve this flexibility
and to work around different shortcomings of the current tools. Choosing the right
design configurations, we are able to present two extremely competitive solutions
for very different FPGA targets, reaching up to 172 GFLOPS sustained performance.
With the portability and flexibility demonstrated, code developers not only avoid
vendor lock-in, but can even make best use of real trade-offs between different
architectures.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Förstner J, Plessl C. Flexible FPGA design for FDTD using OpenCL.
In: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL).
IEEE; 2017. doi:10.23919/FPL.2017.8056844'
apa: Kenter, T., Förstner, J., & Plessl, C. (2017). Flexible FPGA design for
FDTD using OpenCL. Proc. Int. Conf. on Field Programmable Logic and Applications
(FPL). https://doi.org/10.23919/FPL.2017.8056844
bibtex: '@inproceedings{Kenter_Förstner_Plessl_2017, title={Flexible FPGA design
for FDTD using OpenCL}, DOI={10.23919/FPL.2017.8056844},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={IEEE}, author={Kenter, Tobias and Förstner, Jens and Plessl, Christian},
year={2017} }'
chicago: Kenter, Tobias, Jens Förstner, and Christian Plessl. “Flexible FPGA Design
for FDTD Using OpenCL.” In Proc. Int. Conf. on Field Programmable Logic and
Applications (FPL). IEEE, 2017. https://doi.org/10.23919/FPL.2017.8056844.
ieee: 'T. Kenter, J. Förstner, and C. Plessl, “Flexible FPGA design for FDTD using
OpenCL,” 2017, doi: 10.23919/FPL.2017.8056844.'
mla: Kenter, Tobias, et al. “Flexible FPGA Design for FDTD Using OpenCL.” Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2017,
doi:10.23919/FPL.2017.8056844.
short: 'T. Kenter, J. Förstner, C. Plessl, in: Proc. Int. Conf. on Field Programmable
Logic and Applications (FPL), IEEE, 2017.'
date_created: 2018-03-22T11:10:23Z
date_updated: 2023-09-26T13:24:38Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '61'
doi: 10.23919/FPL.2017.8056844
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T15:02:28Z
date_updated: 2018-11-02T15:02:28Z
file_id: '5291'
file_name: 08056844.pdf
file_size: 230235
relation: main_file
success: 1
file_date_updated: 2018-11-02T15:02:28Z
has_accepted_license: '1'
keyword:
- tet_topic_hpc
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
- _id: '33'
grant_number: 01|H16005A
name: HighPerMeshes
- _id: '32'
grant_number: PL 595/2-1 / 320898746
name: Performance and Efficiency in HPC with Custom Computing
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: IEEE
quality_controlled: '1'
status: public
title: Flexible FPGA design for FDTD using OpenCL
type: conference
user_id: '15278'
year: '2017'
...
---
_id: '34'
author:
- first_name: Michael
full_name: Dellnitz, Michael
last_name: Dellnitz
- first_name: Julian
full_name: Eckstein, Julian
last_name: Eckstein
- first_name: Kathrin
full_name: Flaßkamp, Kathrin
last_name: Flaßkamp
- first_name: Patrick
full_name: Friedel, Patrick
last_name: Friedel
- first_name: Christian
full_name: Horenkamp, Christian
last_name: Horenkamp
- first_name: Ulrich
full_name: Köhler, Ulrich
last_name: Köhler
- first_name: Sina
full_name: Ober-Blöbaum, Sina
last_name: Ober-Blöbaum
- first_name: Sebastian
full_name: Peitz, Sebastian
last_name: Peitz
- first_name: Sebastian
full_name: Tiemeyer, Sebastian
last_name: Tiemeyer
citation:
ama: 'Dellnitz M, Eckstein J, Flaßkamp K, et al. Multiobjective Optimal Control
Methods for the Development of an Intelligent Cruise Control. In: Progress
in Industrial Mathematics at ECMI. Vol 22. Mathematics in Industry. Cham:
Springer International Publishing; 2016:633-641. doi:10.1007/978-3-319-23413-7_87'
apa: 'Dellnitz, M., Eckstein, J., Flaßkamp, K., Friedel, P., Horenkamp, C., Köhler,
U., … Tiemeyer, S. (2016). Multiobjective Optimal Control Methods for the Development
of an Intelligent Cruise Control. In Progress in Industrial Mathematics at
ECMI (Vol. 22, pp. 633–641). Cham: Springer International Publishing. https://doi.org/10.1007/978-3-319-23413-7_87'
bibtex: '@inproceedings{Dellnitz_Eckstein_Flaßkamp_Friedel_Horenkamp_Köhler_Ober-Blöbaum_Peitz_Tiemeyer_2016,
place={Cham}, series={Mathematics in Industry}, title={Multiobjective Optimal
Control Methods for the Development of an Intelligent Cruise Control}, volume={22},
DOI={10.1007/978-3-319-23413-7_87},
booktitle={Progress in Industrial Mathematics at ECMI}, publisher={Springer International
Publishing}, author={Dellnitz, Michael and Eckstein, Julian and Flaßkamp, Kathrin
and Friedel, Patrick and Horenkamp, Christian and Köhler, Ulrich and Ober-Blöbaum,
Sina and Peitz, Sebastian and Tiemeyer, Sebastian}, year={2016}, pages={633–641},
collection={Mathematics in Industry} }'
chicago: 'Dellnitz, Michael, Julian Eckstein, Kathrin Flaßkamp, Patrick Friedel,
Christian Horenkamp, Ulrich Köhler, Sina Ober-Blöbaum, Sebastian Peitz, and Sebastian
Tiemeyer. “Multiobjective Optimal Control Methods for the Development of an Intelligent
Cruise Control.” In Progress in Industrial Mathematics at ECMI, 22:633–41.
Mathematics in Industry. Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-23413-7_87.'
ieee: M. Dellnitz et al., “Multiobjective Optimal Control Methods for the
Development of an Intelligent Cruise Control,” in Progress in Industrial Mathematics
at ECMI, 2016, vol. 22, pp. 633–641.
mla: Dellnitz, Michael, et al. “Multiobjective Optimal Control Methods for the Development
of an Intelligent Cruise Control.” Progress in Industrial Mathematics at ECMI,
vol. 22, Springer International Publishing, 2016, pp. 633–41, doi:10.1007/978-3-319-23413-7_87.
short: 'M. Dellnitz, J. Eckstein, K. Flaßkamp, P. Friedel, C. Horenkamp, U. Köhler,
S. Ober-Blöbaum, S. Peitz, S. Tiemeyer, in: Progress in Industrial Mathematics
at ECMI, Springer International Publishing, Cham, 2016, pp. 633–641.'
date_created: 2017-07-26T15:25:33Z
date_updated: 2022-01-06T06:59:14Z
department:
- _id: '27'
- _id: '101'
doi: 10.1007/978-3-319-23413-7_87
intvolume: ' 22'
page: 633-641
place: Cham
publication: Progress in Industrial Mathematics at ECMI
publication_identifier:
issn:
- 2212-0173
publisher: Springer International Publishing
series_title: Mathematics in Industry
status: public
title: Multiobjective Optimal Control Methods for the Development of an Intelligent
Cruise Control
type: conference
user_id: '24135'
volume: 22
year: '2016'
...
---
_id: '19'
abstract:
- lang: eng
text: "Version Control Systems (VCS) are a valuable tool for software development\r\nand
document management. Both client/server and distributed (Peer-to-Peer)\r\nmodels
exist, with the latter (e.g., Git and Mercurial) becoming\r\nincreasingly popular.
Their distributed nature introduces complications,\r\nespecially concerning security:
it is hard to control the dissemination of\r\ncontents stored in distributed VCS
as they rely on replication of complete\r\nrepositories to any involved user.\r\n\r\nWe
overcome this issue by designing and implementing a concept for\r\ncryptography-enforced
access control which is transparent to the user. Use\r\nof field-tested schemes
(end-to-end encryption, digital signatures) allows\r\nfor strong security, while
adoption of convergent encryption and\r\ncontent-defined chunking retains storage
efficiency. The concept is\r\nseamlessly integrated into Mercurial---respecting
its distributed storage\r\nconcept---to ensure practical usability and compatibility
to existing\r\ndeployments."
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Dominik
full_name: Leibenger, Dominik
last_name: Leibenger
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Lass M, Leibenger D, Sorge C. Confidentiality and Authenticity for Distributed
Version Control Systems - A Mercurial Extension. In: Proc. 41st Conference
on Local Computer Networks (LCN). IEEE; 2016. doi:10.1109/lcn.2016.11'
apa: Lass, M., Leibenger, D., & Sorge, C. (2016). Confidentiality and Authenticity
for Distributed Version Control Systems - A Mercurial Extension. In Proc. 41st
Conference on Local Computer Networks (LCN). IEEE. https://doi.org/10.1109/lcn.2016.11
bibtex: '@inproceedings{Lass_Leibenger_Sorge_2016, title={Confidentiality and Authenticity
for Distributed Version Control Systems - A Mercurial Extension}, DOI={10.1109/lcn.2016.11},
booktitle={Proc. 41st Conference on Local Computer Networks (LCN)}, publisher={IEEE},
author={Lass, Michael and Leibenger, Dominik and Sorge, Christoph}, year={2016}
}'
chicago: Lass, Michael, Dominik Leibenger, and Christoph Sorge. “Confidentiality
and Authenticity for Distributed Version Control Systems - A Mercurial Extension.”
In Proc. 41st Conference on Local Computer Networks (LCN). IEEE, 2016.
https://doi.org/10.1109/lcn.2016.11.
ieee: M. Lass, D. Leibenger, and C. Sorge, “Confidentiality and Authenticity for
Distributed Version Control Systems - A Mercurial Extension,” in Proc. 41st
Conference on Local Computer Networks (LCN), 2016.
mla: Lass, Michael, et al. “Confidentiality and Authenticity for Distributed Version
Control Systems - A Mercurial Extension.” Proc. 41st Conference on Local Computer
Networks (LCN), IEEE, 2016, doi:10.1109/lcn.2016.11.
short: 'M. Lass, D. Leibenger, C. Sorge, in: Proc. 41st Conference on Local Computer
Networks (LCN), IEEE, 2016.'
date_created: 2017-07-25T14:36:16Z
date_updated: 2022-01-06T06:53:56Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/lcn.2016.11
keyword:
- access control
- distributed version control systems
- mercurial
- peer-to-peer
- convergent encryption
- confidentiality
- authenticity
language:
- iso: eng
publication: Proc. 41st Conference on Local Computer Networks (LCN)
publication_identifier:
isbn:
- 978-1-5090-2054-6
publication_status: published
publisher: IEEE
status: public
title: Confidentiality and Authenticity for Distributed Version Control Systems -
A Mercurial Extension
type: conference
user_id: '24135'
year: '2016'
...
---
_id: '31'
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Ettore M. G.
full_name: Trainiti, Ettore M. G.
last_name: Trainiti
- first_name: Gianluca C.
full_name: Durelli, Gianluca C.
last_name: Durelli
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time
Code Generation for Transparent Resource Management in Heterogeneous Systems.
In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.'
apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &
Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource
Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable
Computing (WRC).
bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using
Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous
Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)},
author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti,
Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }'
chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti,
Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation
for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC
Workshop on Reonfigurable Computing (WRC), 2016.
ieee: H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C.
Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management
in Heterogeneous Systems,” 2016.
mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent
Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable
Computing (WRC), 2016.
short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini,
in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.'
date_created: 2017-07-26T15:16:31Z
date_updated: 2023-09-26T13:25:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: deffel
date_created: 2019-01-11T11:56:55Z
date_updated: 2019-01-11T11:56:55Z
file_id: '6626'
file_name: wrc_upb_polimi_final.pdf
file_size: 394563
relation: main_file
success: 1
file_date_updated: 2019-01-11T11:56:55Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)
quality_controlled: '1'
status: public
title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous
Systems
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '24'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL.
In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing
(H2RC). ; 2016.'
apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA
using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC).
bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation
on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance
Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian},
year={2016} }'
chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation
on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC), 2016.
ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,”
2016.
mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on
FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable
Computing (H2RC), 2016.
short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance
Reconfigurable Computing (H2RC), 2016.'
date_created: 2017-07-26T15:00:43Z
date_updated: 2023-09-26T13:26:17Z
ddc:
- '004'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: kenter
date_created: 2018-11-14T12:38:45Z
date_updated: 2018-11-14T12:38:45Z
file_id: '5602'
file_name: paper_26.pdf
file_size: 129552
relation: main_file
success: 1
file_date_updated: 2018-11-14T12:38:45Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '32'
grant_number: PL 595/2-1 / 320898746
name: Performance and Efficiency in HPC with Custom Computing
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing
(H2RC)
quality_controlled: '1'
status: public
title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '25'
author:
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Thomas
full_name: Kühne, Thomas
id: '49079'
last_name: Kühne
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes.
In: Workshop on Approximate Computing (AC). ; 2016.'
apa: Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in
Scientific Codes. Workshop on Approximate Computing (AC).
bibtex: '@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing
in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass,
Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }'
chicago: Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing
in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016.
ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific
Codes,” 2016.
mla: Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop
on Approximate Computing (AC), 2016.
short: 'M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC),
2016.'
date_created: 2017-07-26T15:02:20Z
date_updated: 2023-09-26T13:25:17Z
department:
- _id: '27'
- _id: '518'
- _id: '304'
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Workshop on Approximate Computing (AC)
quality_controlled: '1'
status: public
title: Using Approximate Computing in Scientific Codes
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '138'
abstract:
- lang: eng
text: Hardware accelerators are becoming popular in academia and industry. To move
one step further from the state-of-the-art multicore plus accelerator approaches,
we present in this paper our innovative SAVEHSA architecture. It comprises of
a heterogeneous hardware platform with three different high-end accelerators attached
over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads
very efficiently whilst being more energy efficient than regular CPU systems.
To leverage the heterogeneity, the workload has to be distributed among the computing
units in a way that each unit is well-suited for the assigned task and executable
code must be available. To tackle this problem we present two software components;
the first can perform resource allocation at runtime while respecting system and
application goals (in terms of throughput, energy, latency, etc.) and the second
is able to analyze an application and generate executable code for an accelerator
at runtime. We demonstrate the first proof-of-concept implementation of our framework
on the heterogeneous platform, discuss different runtime policies and measure
the introduced overheads.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: 'Ettore M. G. '
full_name: 'Trainiti, Ettore M. G. '
last_name: Trainiti
- first_name: Gianluca C.
full_name: Durelli, Gianluca C.
last_name: Durelli
- first_name: Emanuele
full_name: Del Sozzo, Emanuele
last_name: Del Sozzo
- first_name: 'Marco D. '
full_name: 'Santambrogio, Marco D. '
last_name: Santambrogio
- first_name: Christina
full_name: Bolchini, Christina
last_name: Bolchini
citation:
ama: 'Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for
Transparent Resource Management in Heterogeneous Systems. In: Proceedings of
International Forum on Research and Technologies for Society and Industry (RTSI).
IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545'
apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del
Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time
Code Generation for Transparent Resource Management in Heterogeneous Systems.
Proceedings of International Forum on Research and Technologies for Society
and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545
bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016,
title={Using Just-in-Time Code Generation for Transparent Resource Management
in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545},
booktitle={Proceedings of International Forum on Research and Technologies for
Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and
Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli,
Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini,
Christina}, year={2016}, pages={1–5} }'
chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti,
Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina
Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management
in Heterogeneous Systems.” In Proceedings of International Forum on Research
and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545.
ieee: 'H. Riebler et al., “Using Just-in-Time Code Generation for Transparent
Resource Management in Heterogeneous Systems,” in Proceedings of International
Forum on Research and Technologies for Society and Industry (RTSI), 2016,
pp. 1–5, doi: 10.1109/RTSI.2016.7740545.'
mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent
Resource Management in Heterogeneous Systems.” Proceedings of International
Forum on Research and Technologies for Society and Industry (RTSI), IEEE,
2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545.
short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo,
M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research
and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.'
date_created: 2017-10-17T12:41:18Z
date_updated: 2023-09-26T13:28:11Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
doi: 10.1109/RTSI.2016.7740545
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T13:01:09Z
date_updated: 2018-03-21T13:01:09Z
file_id: '1560'
file_name: 138-07740545.pdf
file_size: 184334
relation: main_file
success: 1
file_date_updated: 2018-03-21T13:01:09Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-5
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of International Forum on Research and Technologies for Society
and Industry (RTSI)
publisher: IEEE
quality_controlled: '1'
status: public
title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous
Systems
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '168'
abstract:
- lang: eng
text: The use of heterogeneous computing resources, such as Graphic Processing Units
or other specialized coprocessors, has become widespread in recent years because
of their per- formance and energy efficiency advantages. Approaches for managing
and scheduling tasks to heterogeneous resources are still subject to research.
Although queuing systems have recently been extended to support accelerator resources,
a general solution that manages heterogeneous resources at the operating system-
level to exploit a global view of the system state is still missing.In this paper
we present a user space scheduler that enables task scheduling and migration on
heterogeneous processing resources in Linux. Using run queues for available resources
we perform scheduling decisions based on the system state and on task characterization
from earlier measurements. With a pro- gramming pattern that supports the integration
of checkpoints into applications, we preempt tasks and migrate them between three
very different compute resources. Considering static and dynamic workload scenarios,
we show that this approach can gain up to 17% performance, on average 7%, by effectively
avoiding idle resources. We demonstrate that a work-conserving strategy without
migration is no suitable alternative.
author:
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Tobias
full_name: Beisel, Tobias
last_name: Beisel
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling
with task migration for a heterogeneous compute node in the data center. In: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE). EDA Consortium / IEEE; 2016:912-917.'
apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center.
Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 912–917.
bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center},
booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim
and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco},
year={2016}, pages={912–917} }'
chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco
Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous
Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation
& Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium
/ IEEE, 2016.
ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric
scheduling with task migration for a heterogeneous compute node in the data center,”
in Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE), 2016, pp. 912–917.
mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for
a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design,
Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium
/ IEEE, 2016, pp. 912–17.
short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings
of the 2016 Design, Automation & Test in Europe Conference & Exhibition
(DATE), EDA Consortium / IEEE, 2016, pp. 912–917.'
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:27:00Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:41:55Z
date_updated: 2018-03-21T12:41:55Z
file_id: '1541'
file_name: 168-07459438.pdf
file_size: 261356
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:41:55Z
has_accepted_license: '1'
language:
- iso: eng
page: 912-917
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference
& Exhibition (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Performance-centric scheduling with task migration for a heterogeneous compute
node in the data center
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '171'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application
partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop
on Reconfigurable Computing (WRC). ; 2016.'
apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities
for deferring application partitioning and accelerator synthesis to runtime (extended
abstract). Workshop on Reconfigurable Computing (WRC).
bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for
deferring application partitioning and accelerator synthesis to runtime (extended
abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter,
Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016}
}'
chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl.
“Opportunities for Deferring Application Partitioning and Accelerator Synthesis
to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC),
2016.
ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring
application partitioning and accelerator synthesis to runtime (extended abstract),”
2016.
mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning
and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable
Computing (WRC), 2016.
short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable
Computing (WRC), 2016.'
date_created: 2017-10-17T12:41:25Z
date_updated: 2023-09-26T13:27:21Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:39:46Z
date_updated: 2018-03-21T12:39:46Z
file_id: '1538'
file_name: 171-plessl16_fpl_wrc.pdf
file_size: 54421
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:39:46Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Workshop on Reconfigurable Computing (WRC)
quality_controlled: '1'
status: public
title: Opportunities for deferring application partitioning and accelerator synthesis
to runtime (extended abstract)
type: conference
user_id: '15278'
year: '2016'
...
---
_id: '303'
abstract:
- lang: eng
text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use
on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling
existentsoftware to automatically utilize accelerators at runtime. BAARis based
on the LLVM Compiler Infrastructure and has aclient-server architecture. The client
runs the program to beaccelerated in an environment which allows program analysisand
profiling. Program parts which are identified as suitable forthe available accelerator
are exported and sent to the server.The server optimizes these program parts for
the acceleratorand provides RPC execution for the client. The client transformsits
program to utilize accelerated execution on the server foroffloaded program parts.
We evaluate our work with a proofof-concept implementation of BAAR that uses an
Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading,
parallelization and vectorization of suitable programparts. The practicality of
BAAR for real-world examples is shownbased on a study of stencil codes. Our results
show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints
over the same code compiled with the Intel Compiler atoptimization level O2 and
running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand
evaluation we outline future directions of research, e.g.,offloading more fine-granular
program parts than functions, amore sophisticated communication mechanism or introducing
onstack-replacement.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on
Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning
Computing Systems (ADAPT). ; 2015.'
apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores. Proceedings of the 5th International Workshop on
Adaptive Self-Tuning Computing Systems (ADAPT).
bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International
Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen,
Marvin and Plessl, Christian}, year={2015} }'
chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary
Program Acceleration on Many-Cores.” In Proceedings of the 5th International
Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration
on Many-Cores,” 2015.
mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program
Acceleration on Many-Cores.” Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.
short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop
on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.'
date_created: 2017-10-17T12:41:51Z
date_updated: 2023-09-26T13:29:59Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
external_id:
arxiv:
- '1412.3906'
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:46:46Z
date_updated: 2019-08-01T09:10:44Z
file_id: '1442'
file_name: 303-plessl15_adapt.pdf
file_size: 1176620
relation: main_file
file_date_updated: 2019-08-01T09:10:44Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning
Computing Systems (ADAPT)
quality_controlled: '1'
status: public
title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1773'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: J.
full_name: T. Anderson, J.
last_name: T. Anderson
- first_name: A.
full_name: Borga, A.
last_name: Borga
- first_name: H.
full_name: Boterenbrood, H.
last_name: Boterenbrood
- first_name: H.
full_name: Chen, H.
last_name: Chen
- first_name: K.
full_name: Chen, K.
last_name: Chen
- first_name: G.
full_name: Drake, G.
last_name: Drake
- first_name: D.
full_name: Francis, D.
last_name: Francis
- first_name: B.
full_name: Gorini, B.
last_name: Gorini
- first_name: F.
full_name: Lanni, F.
last_name: Lanni
- first_name: Giovanna
full_name: Lehmann-Miotto, Giovanna
last_name: Lehmann-Miotto
- first_name: L.
full_name: Levinson, L.
last_name: Levinson
- first_name: J.
full_name: Narevicius, J.
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A.
full_name: Roich, A.
last_name: Roich
- first_name: S.
full_name: Ryu, S.
last_name: Ryu
- first_name: F.
full_name: P. Schreuder, F.
last_name: P. Schreuder
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J.
full_name: Vermeulen, J.
last_name: Vermeulen
- first_name: J.
full_name: Zhang, J.
last_name: Zhang
citation:
ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015.
doi:10.1145/2675743.2771824'
apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen,
K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson,
L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli,
W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance
in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.
Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824
bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et
al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project
– Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824},
booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM},
author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H.
and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni,
F. and et al.}, year={2015} }'
chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K.
Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX
Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824.
ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in
the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,”
2015, doi: 10.1145/2675743.2771824.'
mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS
FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc.
Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824.
short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen,
G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J.
Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen,
J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM,
2015.'
date_created: 2018-03-23T14:09:33Z
date_updated: 2023-09-26T13:31:01Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/2675743.2771824
language:
- iso: eng
publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)
publisher: ACM
quality_controlled: '1'
status: public
title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis
and Optimization of a Memory-Bounded Algorithm
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1781'
abstract:
- lang: eng
text: In light of an increasing awareness of environmental challenges, extensive
research is underway to develop new light-weight materials. A problem arising
with these materials is their increased response to vibration. This can be solved
using a new composite material that contains embedded hollow spheres that are
partially filled with particles. Progress on the adaptation of molecular dynamics
towards a particle-based numerical simulation of this material is reported. This
includes the treatment of specific boundary conditions and the adaption of the
force computation. First results are presented that showcase the damping properties
of such particle-filled spheres in a bouncing experiment.
author:
- first_name: Tobias
full_name: Steinle, Tobias
last_name: Steinle
- first_name: Jadran
full_name: Vrabec, Jadran
last_name: Vrabec
- first_name: Andrea
full_name: Walther, Andrea
last_name: Walther
citation:
ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior
of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder
JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC).
Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19'
apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of
the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang,
R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization
of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing.
https://doi.org/10.1007/978-3-319-09063-4_19
bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19},
booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)},
publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec,
Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and
Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243}
}'
chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling,
Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg
Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer
International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.
ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping
Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation
and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.
mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled
Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), edited by Hans Georg Bock et al., Springer International Publishing,
2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.
short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher,
J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), Springer International Publishing, 2014, pp. 233–243.'
date_created: 2018-03-26T13:47:16Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '104'
- _id: '155'
doi: 10.1007/978-3-319-09063-4_19
editor:
- first_name: Hans Georg
full_name: Bock, Hans Georg
last_name: Bock
- first_name: Xuan Phu
full_name: Hoang, Xuan Phu
last_name: Hoang
- first_name: Rolf
full_name: Rannacher, Rolf
last_name: Rannacher
- first_name: Johannes P.
full_name: Schlöder, Johannes P.
last_name: Schlöder
page: 233-243
publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)
publication_identifier:
isbn:
- 978-3-319-09063-4
publisher: Springer International Publishing
status: public
title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '1782'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science.
Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2'
apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in
Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25).
Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2'
bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture
Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2},
number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer},
author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25},
collection={Lecture Notes in Computer Science} }'
chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection
in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25.
Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.'
ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf.
on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games
(CG), Springer, Switzerland, 2014, pp. 14–25.'
date_created: 2018-03-26T13:50:37Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1007/978-3-319-09165-5_2
issue: '8427'
page: 14-25
place: Switzerland
publication: Proc. Conf. on Computers and Games (CG)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: On Semeai Detection in Monte-Carlo Go
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1780'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Copolla, Marcello
last_name: Copolla
- first_name: Karim
full_name: Djafarian, Karim
last_name: Djafarian
- first_name: George
full_name: Koranaros, George
last_name: Koranaros
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Michele
full_name: Paolino, Michele
last_name: Paolino
- first_name: Oliver
full_name: Pell, Oliver
last_name: Pell
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Copolla M, Djafarian K, et al. SAVE: Towards efficient resource
management in heterogeneous system architectures. In: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC). Springer; 2014. doi:10.1007/978-3-319-05960-0_38'
apa: 'C. Durelli, G., Copolla, M., Djafarian, K., Koranaros, G., Miele, A., Paolino,
M., Pell, O., Plessl, C., D. Santambrogio, M., & Bolchini, C. (2014). SAVE:
Towards efficient resource management in heterogeneous system architectures. Proc.
Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications
(ARC). https://doi.org/10.1007/978-3-319-05960-0_38'
bibtex: '@inproceedings{C. Durelli_Copolla_Djafarian_Koranaros_Miele_Paolino_Pell_Plessl_D.
Santambrogio_Bolchini_2014, title={SAVE: Towards efficient resource management
in heterogeneous system architectures}, DOI={10.1007/978-3-319-05960-0_38},
booktitle={Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools
and Applications (ARC)}, publisher={Springer}, author={C. Durelli, Gianluca and
Copolla, Marcello and Djafarian, Karim and Koranaros, George and Miele, Antonio
and Paolino, Michele and Pell, Oliver and Plessl, Christian and D. Santambrogio,
Marco and Bolchini, Cristiana}, year={2014} }'
chicago: 'C. Durelli, Gianluca, Marcello Copolla, Karim Djafarian, George Koranaros,
Antonio Miele, Michele Paolino, Oliver Pell, Christian Plessl, Marco D. Santambrogio,
and Cristiana Bolchini. “SAVE: Towards Efficient Resource Management in Heterogeneous
System Architectures.” In Proc. Int. Conf. on Reconfigurable Computing: Architectures,
Tools and Applications (ARC). Springer, 2014. https://doi.org/10.1007/978-3-319-05960-0_38.'
ieee: 'G. C. Durelli et al., “SAVE: Towards efficient resource management
in heterogeneous system architectures,” 2014, doi: 10.1007/978-3-319-05960-0_38.'
mla: 'C. Durelli, Gianluca, et al. “SAVE: Towards Efficient Resource Management
in Heterogeneous System Architectures.” Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014, doi:10.1007/978-3-319-05960-0_38.'
short: 'G. C. Durelli, M. Copolla, K. Djafarian, G. Koranaros, A. Miele, M. Paolino,
O. Pell, C. Plessl, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Conf. on Reconfigurable
Computing: Architectures, Tools and Applications (ARC), Springer, 2014.'
date_created: 2018-03-26T13:45:35Z
date_updated: 2023-09-26T13:36:20Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_38
language:
- iso: eng
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and
Applications (ARC)'
publisher: Springer
quality_controlled: '1'
status: public
title: 'SAVE: Towards efficient resource management in heterogeneous system architectures'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '1784'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Viktor
full_name: Gottfried, Viktor
last_name: Gottfried
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Gottfried V, Brinkmann A. MCD: Overcoming the Data Download
Bottleneck in Data Centers. In: Proc. IEEE Int. Conf. on Networking, Architecture
and Storage (NAS). Washington DC, USA: IEEE Computer Society; 2013:88-97.
doi:10.1109/NAS.2013.18'
apa: 'Kaiser, J., Meister, D., Gottfried, V., & Brinkmann, A. (2013). MCD: Overcoming
the Data Download Bottleneck in Data Centers. In Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS) (pp. 88–97). Washington DC, USA: IEEE Computer
Society. https://doi.org/10.1109/NAS.2013.18'
bibtex: '@inproceedings{Kaiser_Meister_Gottfried_Brinkmann_2013, place={Washington
DC, USA}, title={MCD: Overcoming the Data Download Bottleneck in Data Centers},
DOI={10.1109/NAS.2013.18}, booktitle={Proc.
IEEE Int. Conf. on Networking, Architecture and Storage (NAS)}, publisher={IEEE
Computer Society}, author={Kaiser, Jürgen and Meister, Dirk and Gottfried, Viktor
and Brinkmann, André}, year={2013}, pages={88–97} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Viktor Gottfried, and André Brinkmann. “MCD:
Overcoming the Data Download Bottleneck in Data Centers.” In Proc. IEEE Int.
Conf. on Networking, Architecture and Storage (NAS), 88–97. Washington DC,
USA: IEEE Computer Society, 2013. https://doi.org/10.1109/NAS.2013.18.'
ieee: 'J. Kaiser, D. Meister, V. Gottfried, and A. Brinkmann, “MCD: Overcoming the
Data Download Bottleneck in Data Centers,” in Proc. IEEE Int. Conf. on Networking,
Architecture and Storage (NAS), 2013, pp. 88–97.'
mla: 'Kaiser, Jürgen, et al. “MCD: Overcoming the Data Download Bottleneck in Data
Centers.” Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS),
IEEE Computer Society, 2013, pp. 88–97, doi:10.1109/NAS.2013.18.'
short: 'J. Kaiser, D. Meister, V. Gottfried, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Networking, Architecture and Storage (NAS), IEEE Computer Society, Washington
DC, USA, 2013, pp. 88–97.'
date_created: 2018-03-26T14:43:38Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
doi: 10.1109/NAS.2013.18
page: 88-97
place: Washington DC, USA
publication: Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS)
publisher: IEEE Computer Society
status: public
title: 'MCD: Overcoming the Data Download Bottleneck in Data Centers'
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1786'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA Implementation of a Second-Order Convolutive Blind
Signal Separation Algorithm. In: Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE; 2013. doi:10.1109/SIU.2013.6531530'
apa: Kasap, S., & Redif, S. (2013). FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm. In Proc. IEEE Signal Processing and Communications
Conf. (SUI). IEEE. https://doi.org/10.1109/SIU.2013.6531530
bibtex: '@inproceedings{Kasap_Redif_2013, title={FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm}, DOI={10.1109/SIU.2013.6531530},
booktitle={Proc. IEEE Signal Processing and Communications Conf. (SUI)}, publisher={IEEE},
author={Kasap, Server and Redif, Soydan}, year={2013} }'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Proc. IEEE Signal Processing
and Communications Conf. (SUI). IEEE, 2013. https://doi.org/10.1109/SIU.2013.6531530.
ieee: S. Kasap and S. Redif, “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm,” in Proc. IEEE Signal Processing and Communications
Conf. (SUI), 2013.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013, doi:10.1109/SIU.2013.6531530.
short: 'S. Kasap, S. Redif, in: Proc. IEEE Signal Processing and Communications
Conf. (SUI), IEEE, 2013.'
date_created: 2018-03-26T14:48:53Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/SIU.2013.6531530
publication: Proc. IEEE Signal Processing and Communications Conf. (SUI)
publisher: IEEE
status: public
title: FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1788'
author:
- first_name: Petra
full_name: Berenbrink, Petra
last_name: Berenbrink
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tom
full_name: Friedetzky, Tom
last_name: Friedetzky
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Lars
full_name: Nagel, Lars
last_name: Nagel
citation:
ama: 'Berenbrink P, Brinkmann A, Friedetzky T, Meister D, Nagel L. Distributing
Storage in Cloud Environments. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE; 2013. doi:10.1109/IPDPSW.2013.148'
apa: Berenbrink, P., Brinkmann, A., Friedetzky, T., Meister, D., & Nagel, L.
(2013). Distributing Storage in Cloud Environments. In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE. https://doi.org/10.1109/IPDPSW.2013.148
bibtex: '@inproceedings{Berenbrink_Brinkmann_Friedetzky_Meister_Nagel_2013, title={Distributing
Storage in Cloud Environments}, DOI={10.1109/IPDPSW.2013.148},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE}, author={Berenbrink, Petra and Brinkmann, André and Friedetzky,
Tom and Meister, Dirk and Nagel, Lars}, year={2013} }'
chicago: Berenbrink, Petra, André Brinkmann, Tom Friedetzky, Dirk Meister, and Lars
Nagel. “Distributing Storage in Cloud Environments.” In Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW). IEEE, 2013. https://doi.org/10.1109/IPDPSW.2013.148.
ieee: P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, and L. Nagel, “Distributing
Storage in Cloud Environments,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013.
mla: Berenbrink, Petra, et al. “Distributing Storage in Cloud Environments.” Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE,
2013, doi:10.1109/IPDPSW.2013.148.
short: 'P. Berenbrink, A. Brinkmann, T. Friedetzky, D. Meister, L. Nagel, in: Proc.
Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW), IEEE, 2013.'
date_created: 2018-03-26T14:52:56Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
doi: 10.1109/IPDPSW.2013.148
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publisher: IEEE
status: public
title: Distributing Storage in Cloud Environments
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '1793'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
citation:
ama: 'Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication
Systems. In: Proc. USENIX Conference on File and Storage Technologies (FAST).
USENIX Association; 2013:175-182.'
apa: Meister, D., Brinkmann, A., & Süß, T. (2013). File Recipe Compression in
Data Deduplication Systems. In Proc. USENIX Conference on File and Storage
Technologies (FAST) (pp. 175–182). USENIX Association.
bibtex: '@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression
in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and
Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister,
Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }'
chicago: Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in
Data Deduplication Systems.” In Proc. USENIX Conference on File and Storage
Technologies (FAST), 175–82. USENIX Association, 2013.
ieee: D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication
Systems,” in Proc. USENIX Conference on File and Storage Technologies (FAST),
2013, pp. 175–182.
mla: Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.”
Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX
Association, 2013, pp. 175–82.
short: 'D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and
Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.'
date_created: 2018-03-26T15:16:03Z
date_updated: 2022-01-06T06:53:23Z
department:
- _id: '27'
page: 175-182
publication: Proc. USENIX Conference on File and Storage Technologies (FAST)
publisher: USENIX Association
status: public
title: File Recipe Compression in Data Deduplication Systems
type: conference
user_id: '24135'
year: '2013'
...
---
_id: '528'
abstract:
- lang: eng
text: Cold-boot attacks exploit the fact that DRAM contents are not immediately
lost when a PC is powered off. Instead the contents decay rather slowly, in particular
if the DRAM chips are cooled to low temperatures. This effect opens an attack
vector on cryptographic applications that keep decrypted keys in DRAM. An attacker
with access to the target computer can reboot it or remove the RAM modules and
quickly copy the RAM contents to non-volatile memory. By exploiting the known
cryptographic structure of the cipher and layout of the key data in memory, in
our application an AES key schedule with redundancy, the resulting memory image
can be searched for sections that could correspond to decayed cryptographic keys;
then, the attacker can attempt to reconstruct the original key. However, the runtime
of these algorithms grows rapidly with increasing memory image size, error rate
and complexity of the bit error model, which limits the practicability of the
approach.In this work, we study how the algorithm for key search can be accelerated
with custom computing machines. We present an FPGA-based architecture on a Maxeler
dataflow computing system that outperforms a software implementation up to 205x,
which significantly improves the practicability of cold-attacks against AES.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot
Attacks against AES. In: Proceedings of the International Conference on Field-Programmable
Technology (FPT). IEEE; 2013:386-389. doi:10.1109/FPT.2013.6718394'
apa: Riebler, H., Kenter, T., Sorge, C., & Plessl, C. (2013). FPGA-accelerated
Key Search for Cold-Boot Attacks against AES. Proceedings of the International
Conference on Field-Programmable Technology (FPT), 386–389. https://doi.org/10.1109/FPT.2013.6718394
bibtex: '@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated
Key Search for Cold-Boot Attacks against AES}, DOI={10.1109/FPT.2013.6718394},
booktitle={Proceedings of the International Conference on Field-Programmable Technology
(FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge,
Christoph and Plessl, Christian}, year={2013}, pages={386–389} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl.
“FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In Proceedings
of the International Conference on Field-Programmable Technology (FPT), 386–89.
IEEE, 2013. https://doi.org/10.1109/FPT.2013.6718394.
ieee: 'H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search
for Cold-Boot Attacks against AES,” in Proceedings of the International Conference
on Field-Programmable Technology (FPT), 2013, pp. 386–389, doi: 10.1109/FPT.2013.6718394.'
mla: Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks
against AES.” Proceedings of the International Conference on Field-Programmable
Technology (FPT), IEEE, 2013, pp. 386–89, doi:10.1109/FPT.2013.6718394.
short: 'H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International
Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.'
date_created: 2017-10-17T12:42:35Z
date_updated: 2023-09-26T13:37:35Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2013.6718394
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T10:36:08Z
date_updated: 2018-03-15T10:36:08Z
file_id: '1294'
file_name: 528-plessl13_fpt.pdf
file_size: 822680
relation: main_file
success: 1
file_date_updated: 2018-03-15T10:36:08Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 386-389
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '13'
name: SFB 901 - Subproject C1
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on Field-Programmable Technology
(FPT)
publisher: IEEE
quality_controlled: '1'
status: public
title: FPGA-accelerated Key Search for Cold-Boot Attacks against AES
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '505'
abstract:
- lang: eng
text: In this paper we introduce “On-The-Fly Computing”, our vision of future IT
services that will be provided by assembling modular software components available
on world-wide markets. After suitable components have been found, they are automatically
integrated, configured and brought to execution in an On-The-Fly Compute Center.
We envision that these future compute centers will continue to leverage three
current trends in large scale computing which are an increasing amount of parallel
processing, a trend to use heterogeneous computing resources, and—in the light
of rising energy cost—energy-efficiency as a primary goal in the design and operation
of computing systems. In this paper, we point out three research challenges and
our current work in these areas.
author:
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Peter
full_name: Kling, Peter
last_name: Kling
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
id: '15523'
last_name: Meyer auf der Heide
citation:
ama: 'Happe M, Kling P, Plessl C, Platzner M, Meyer auf der Heide F. On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services. In: Proceedings
of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous
Systems (SEUS). IEEE; 2013. doi:10.1109/ISORC.2013.6913232'
apa: 'Happe, M., Kling, P., Plessl, C., Platzner, M., & Meyer auf der Heide,
F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS). https://doi.org/10.1109/ISORC.2013.6913232'
bibtex: '@inproceedings{Happe_Kling_Plessl_Platzner_Meyer auf der Heide_2013, title={On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services}, DOI={10.1109/ISORC.2013.6913232},
booktitle={Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)}, publisher={IEEE}, author={Happe, Markus
and Kling, Peter and Plessl, Christian and Platzner, Marco and Meyer auf der Heide,
Friedhelm}, year={2013} }'
chicago: 'Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm
Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” In Proceedings of the 9th IEEE Workshop on Software Technology
for Future Embedded and Ubiquitous Systems (SEUS). IEEE, 2013. https://doi.org/10.1109/ISORC.2013.6913232.'
ieee: 'M. Happe, P. Kling, C. Plessl, M. Platzner, and F. Meyer auf der Heide, “On-The-Fly
Computing: A Novel Paradigm for Individualized IT Services,” 2013, doi: 10.1109/ISORC.2013.6913232.'
mla: 'Happe, Markus, et al. “On-The-Fly Computing: A Novel Paradigm for Individualized
IT Services.” Proceedings of the 9th IEEE Workshop on Software Technology for
Future Embedded and Ubiquitous Systems (SEUS), IEEE, 2013, doi:10.1109/ISORC.2013.6913232.'
short: 'M. Happe, P. Kling, C. Plessl, M. Platzner, F. Meyer auf der Heide, in:
Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded
and Ubiquitous Systems (SEUS), IEEE, 2013.'
date_created: 2017-10-17T12:42:30Z
date_updated: 2023-09-26T13:38:20Z
ddc:
- '040'
department:
- _id: '63'
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISORC.2013.6913232
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-15T13:38:56Z
date_updated: 2018-03-15T13:38:56Z
file_id: '1308'
file_name: 505-Plessl13_seus.pdf
file_size: 1040834
relation: main_file
success: 1
file_date_updated: 2018-03-15T13:38:56Z
has_accepted_license: '1'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: Proceedings of the 9th IEEE Workshop on Software Technology for Future
embedded and Ubiquitous Systems (SEUS)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'On-The-Fly Computing: A Novel Paradigm for Individualized IT Services'
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '1787'
author:
- first_name: Tim
full_name: Suess, Tim
last_name: Suess
- first_name: Andrew
full_name: Schoenrock, Andrew
last_name: Schoenrock
- first_name: Sebastian
full_name: Meisner, Sebastian
last_name: Meisner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Suess T, Schoenrock A, Meisner S, Plessl C. Parallel Macro Pipelining on the
Intel SCC Many-Core Computer. In: Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW). IEEE Computer Society; 2013:64-73. doi:10.1109/IPDPSW.2013.136'
apa: Suess, T., Schoenrock, A., Meisner, S., & Plessl, C. (2013). Parallel Macro
Pipelining on the Intel SCC Many-Core Computer. Proc. Int. Symp. on Parallel
and Distributed Processing Workshops (IPDPSW), 64–73. https://doi.org/10.1109/IPDPSW.2013.136
bibtex: '@inproceedings{Suess_Schoenrock_Meisner_Plessl_2013, place={Washington,
DC, USA}, title={Parallel Macro Pipelining on the Intel SCC Many-Core Computer},
DOI={10.1109/IPDPSW.2013.136},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)},
publisher={IEEE Computer Society}, author={Suess, Tim and Schoenrock, Andrew and
Meisner, Sebastian and Plessl, Christian}, year={2013}, pages={64–73} }'
chicago: 'Suess, Tim, Andrew Schoenrock, Sebastian Meisner, and Christian Plessl.
“Parallel Macro Pipelining on the Intel SCC Many-Core Computer.” In Proc. Int.
Symp. on Parallel and Distributed Processing Workshops (IPDPSW), 64–73. Washington,
DC, USA: IEEE Computer Society, 2013. https://doi.org/10.1109/IPDPSW.2013.136.'
ieee: 'T. Suess, A. Schoenrock, S. Meisner, and C. Plessl, “Parallel Macro Pipelining
on the Intel SCC Many-Core Computer,” in Proc. Int. Symp. on Parallel and Distributed
Processing Workshops (IPDPSW), 2013, pp. 64–73, doi: 10.1109/IPDPSW.2013.136.'
mla: Suess, Tim, et al. “Parallel Macro Pipelining on the Intel SCC Many-Core Computer.”
Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW),
IEEE Computer Society, 2013, pp. 64–73, doi:10.1109/IPDPSW.2013.136.
short: 'T. Suess, A. Schoenrock, S. Meisner, C. Plessl, in: Proc. Int. Symp. on
Parallel and Distributed Processing Workshops (IPDPSW), IEEE Computer Society,
Washington, DC, USA, 2013, pp. 64–73.'
date_created: 2018-03-26T14:51:05Z
date_updated: 2023-09-26T13:38:05Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
- _id: '63'
doi: 10.1109/IPDPSW.2013.136
language:
- iso: eng
page: 64-73
place: Washington, DC, USA
project:
- _id: '30'
grant_number: 01|H11004A
name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling
Models
publication: Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW)
publication_identifier:
isbn:
- 978-0-7695-4979-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: Parallel Macro Pipelining on the Intel SCC Many-Core Computer
type: conference
user_id: '15278'
year: '2013'
...
---
_id: '2097'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA-based design and implementation of an approximate polynomial
matrix EVD algorithm. In: Proc. Int. Conf. on Field Programmable Technology
(ICFPT). IEEE Computer Society; 2012:135-140. doi:10.1109/FPT.2012.6412125'
apa: Kasap, S., & Redif, S. (2012). FPGA-based design and implementation of
an approximate polynomial matrix EVD algorithm. In Proc. Int. Conf. on Field
Programmable Technology (ICFPT) (pp. 135–140). IEEE Computer Society. https://doi.org/10.1109/FPT.2012.6412125
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA-based design and implementation
of an approximate polynomial matrix EVD algorithm}, DOI={10.1109/FPT.2012.6412125},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Kasap, Server and Redif, Soydan}, year={2012}, pages={135–140}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation
of an Approximate Polynomial Matrix EVD Algorithm.” In Proc. Int. Conf. on
Field Programmable Technology (ICFPT), 135–40. IEEE Computer Society, 2012.
https://doi.org/10.1109/FPT.2012.6412125.
ieee: S. Kasap and S. Redif, “FPGA-based design and implementation of an approximate
polynomial matrix EVD algorithm,” in Proc. Int. Conf. on Field Programmable
Technology (ICFPT), 2012, pp. 135–140.
mla: Kasap, Server, and Soydan Redif. “FPGA-Based Design and Implementation of an
Approximate Polynomial Matrix EVD Algorithm.” Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2012, pp. 135–40, doi:10.1109/FPT.2012.6412125.
short: 'S. Kasap, S. Redif, in: Proc. Int. Conf. on Field Programmable Technology
(ICFPT), IEEE Computer Society, 2012, pp. 135–140.'
date_created: 2018-03-29T14:34:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/FPT.2012.6412125
page: 135-140
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: FPGA-based design and implementation of an approximate polynomial matrix EVD
algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2098'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Tim
full_name: Hartung, Tim
last_name: Hartung
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Kaiser J, Meister D, Hartung T, Brinkmann A. ESB: Ext2 Split Block Device.
In: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS).
IEEE; 2012:181-188. doi:10.1109/ICPADS.2012.34'
apa: 'Kaiser, J., Meister, D., Hartung, T., & Brinkmann, A. (2012). ESB: Ext2
Split Block Device. In Proc. IEEE Int. Conf. on Parallel and Distributed Systems
(ICPADS) (pp. 181–188). IEEE. https://doi.org/10.1109/ICPADS.2012.34'
bibtex: '@inproceedings{Kaiser_Meister_Hartung_Brinkmann_2012, title={ESB: Ext2
Split Block Device}, DOI={10.1109/ICPADS.2012.34},
booktitle={Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)},
publisher={IEEE}, author={Kaiser, Jürgen and Meister, Dirk and Hartung, Tim and
Brinkmann, André}, year={2012}, pages={181–188} }'
chicago: 'Kaiser, Jürgen, Dirk Meister, Tim Hartung, and André Brinkmann. “ESB:
Ext2 Split Block Device.” In Proc. IEEE Int. Conf. on Parallel and Distributed
Systems (ICPADS), 181–88. IEEE, 2012. https://doi.org/10.1109/ICPADS.2012.34.'
ieee: 'J. Kaiser, D. Meister, T. Hartung, and A. Brinkmann, “ESB: Ext2 Split Block
Device,” in Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS),
2012, pp. 181–188.'
mla: 'Kaiser, Jürgen, et al. “ESB: Ext2 Split Block Device.” Proc. IEEE Int.
Conf. on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–88,
doi:10.1109/ICPADS.2012.34.'
short: 'J. Kaiser, D. Meister, T. Hartung, A. Brinkmann, in: Proc. IEEE Int. Conf.
on Parallel and Distributed Systems (ICPADS), IEEE, 2012, pp. 181–188.'
date_created: 2018-03-29T14:40:04Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ICPADS.2012.34
page: 181-188
publication: Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS)
publisher: IEEE
status: public
title: 'ESB: Ext2 Split Block Device'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2099'
author:
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Michael
full_name: Kuhn, Michael
last_name: Kuhn
- first_name: Julian
full_name: Kunkel, Julian
last_name: Kunkel
- first_name: Toni
full_name: Cortes, Toni
last_name: Cortes
citation:
ama: 'Meister D, Kaiser J, Brinkmann A, Kuhn M, Kunkel J, Cortes T. A Study on Data
Deduplication in HPC Storage Systems. In: Proc. Int. Conf. on Supercomputing
(SC). Los Alamitos, CA, USA: IEEE Computer Society; 2012:7:1-7:11. doi:10.1109/SC.2012.14'
apa: 'Meister, D., Kaiser, J., Brinkmann, A., Kuhn, M., Kunkel, J., & Cortes,
T. (2012). A Study on Data Deduplication in HPC Storage Systems. In Proc. Int.
Conf. on Supercomputing (SC) (pp. 7:1-7:11). Los Alamitos, CA, USA: IEEE Computer
Society. https://doi.org/10.1109/SC.2012.14'
bibtex: '@inproceedings{Meister_Kaiser_Brinkmann_Kuhn_Kunkel_Cortes_2012, place={Los
Alamitos, CA, USA}, title={A Study on Data Deduplication in HPC Storage Systems},
DOI={10.1109/SC.2012.14}, booktitle={Proc.
Int. Conf. on Supercomputing (SC)}, publisher={IEEE Computer Society}, author={Meister,
Dirk and Kaiser, Jürgen and Brinkmann, André and Kuhn, Michael and Kunkel, Julian
and Cortes, Toni}, year={2012}, pages={7:1-7:11} }'
chicago: 'Meister, Dirk, Jürgen Kaiser, André Brinkmann, Michael Kuhn, Julian Kunkel,
and Toni Cortes. “A Study on Data Deduplication in HPC Storage Systems.” In Proc.
Int. Conf. on Supercomputing (SC), 7:1-7:11. Los Alamitos, CA, USA: IEEE Computer
Society, 2012. https://doi.org/10.1109/SC.2012.14.'
ieee: D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, and T. Cortes, “A
Study on Data Deduplication in HPC Storage Systems,” in Proc. Int. Conf. on
Supercomputing (SC), 2012, pp. 7:1-7:11.
mla: Meister, Dirk, et al. “A Study on Data Deduplication in HPC Storage Systems.”
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, 2012, pp.
7:1-7:11, doi:10.1109/SC.2012.14.
short: 'D. Meister, J. Kaiser, A. Brinkmann, M. Kuhn, J. Kunkel, T. Cortes, in:
Proc. Int. Conf. on Supercomputing (SC), IEEE Computer Society, Los Alamitos,
CA, USA, 2012, pp. 7:1-7:11.'
date_created: 2018-03-29T14:41:55Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/SC.2012.14
page: 7:1-7:11
place: Los Alamitos, CA, USA
publication: Proc. Int. Conf. on Supercomputing (SC)
publisher: IEEE Computer Society
status: public
title: A Study on Data Deduplication in HPC Storage Systems
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2100'
author:
- first_name: Server
full_name: Kasap, Server
last_name: Kasap
- first_name: Soydan
full_name: Redif, Soydan
last_name: Redif
citation:
ama: 'Kasap S, Redif S. FPGA implementation of a second-order convolutive blind
signal separation algorithm. In: Int. Architecture and Engineering Symp. (ARCHENG).
; 2012.'
apa: Kasap, S., & Redif, S. (2012). FPGA implementation of a second-order convolutive
blind signal separation algorithm. In Int. Architecture and Engineering Symp.
(ARCHENG).
bibtex: '@inproceedings{Kasap_Redif_2012, title={FPGA implementation of a second-order
convolutive blind signal separation algorithm}, booktitle={Int. Architecture and
Engineering Symp. (ARCHENG)}, author={Kasap, Server and Redif, Soydan}, year={2012}
}'
chicago: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order
Convolutive Blind Signal Separation Algorithm.” In Int. Architecture and Engineering
Symp. (ARCHENG), 2012.
ieee: S. Kasap and S. Redif, “FPGA implementation of a second-order convolutive
blind signal separation algorithm,” in Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
mla: Kasap, Server, and Soydan Redif. “FPGA Implementation of a Second-Order Convolutive
Blind Signal Separation Algorithm.” Int. Architecture and Engineering Symp.
(ARCHENG), 2012.
short: 'S. Kasap, S. Redif, in: Int. Architecture and Engineering Symp. (ARCHENG),
2012.'
date_created: 2018-03-29T14:43:18Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
publication: Int. Architecture and Engineering Symp. (ARCHENG)
status: public
title: FPGA implementation of a second-order convolutive blind signal separation algorithm
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2101'
author:
- first_name: Matthias
full_name: Grawinkel, Matthias
last_name: Grawinkel
- first_name: Tim
full_name: Süß, Tim
last_name: Süß
- first_name: Georg
full_name: Best, Georg
last_name: Best
- first_name: Ivan
full_name: Popov, Ivan
last_name: Popov
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Grawinkel M, Süß T, Best G, Popov I, Brinkmann A. Towards Dynamic Scripted
pNFS Layouts. In: Proc. Parallel Data Storage Workshop (PDSW). IEEE; 2012:13-17.
doi:10.1109/SC.Companion.2012.13'
apa: Grawinkel, M., Süß, T., Best, G., Popov, I., & Brinkmann, A. (2012). Towards
Dynamic Scripted pNFS Layouts. In Proc. Parallel Data Storage Workshop (PDSW)
(pp. 13–17). IEEE. https://doi.org/10.1109/SC.Companion.2012.13
bibtex: '@inproceedings{Grawinkel_Süß_Best_Popov_Brinkmann_2012, title={Towards
Dynamic Scripted pNFS Layouts}, DOI={10.1109/SC.Companion.2012.13},
booktitle={Proc. Parallel Data Storage Workshop (PDSW)}, publisher={IEEE}, author={Grawinkel,
Matthias and Süß, Tim and Best, Georg and Popov, Ivan and Brinkmann, André}, year={2012},
pages={13–17} }'
chicago: Grawinkel, Matthias, Tim Süß, Georg Best, Ivan Popov, and André Brinkmann.
“Towards Dynamic Scripted PNFS Layouts.” In Proc. Parallel Data Storage Workshop
(PDSW), 13–17. IEEE, 2012. https://doi.org/10.1109/SC.Companion.2012.13.
ieee: M. Grawinkel, T. Süß, G. Best, I. Popov, and A. Brinkmann, “Towards Dynamic
Scripted pNFS Layouts,” in Proc. Parallel Data Storage Workshop (PDSW),
2012, pp. 13–17.
mla: Grawinkel, Matthias, et al. “Towards Dynamic Scripted PNFS Layouts.” Proc.
Parallel Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17, doi:10.1109/SC.Companion.2012.13.
short: 'M. Grawinkel, T. Süß, G. Best, I. Popov, A. Brinkmann, in: Proc. Parallel
Data Storage Workshop (PDSW), IEEE, 2012, pp. 13–17.'
date_created: 2018-03-29T14:44:24Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/SC.Companion.2012.13
page: 13-17
publication: Proc. Parallel Data Storage Workshop (PDSW)
publisher: IEEE
status: public
title: Towards Dynamic Scripted pNFS Layouts
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2103'
author:
- first_name: Martin
full_name: Wistuba, Martin
last_name: Wistuba
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Wistuba M, Schaefers L, Platzner M. Comparison of Bayesian Move Prediction
Systems for Computer Go. In: Proc. IEEE Conf. on Computational Intelligence
and Games (CIG). IEEE; 2012:91-99. doi:10.1109/CIG.2012.6374143'
apa: Wistuba, M., Schaefers, L., & Platzner, M. (2012). Comparison of Bayesian
Move Prediction Systems for Computer Go. In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG) (pp. 91–99). IEEE. https://doi.org/10.1109/CIG.2012.6374143
bibtex: '@inproceedings{Wistuba_Schaefers_Platzner_2012, title={Comparison of Bayesian
Move Prediction Systems for Computer Go}, DOI={10.1109/CIG.2012.6374143},
booktitle={Proc. IEEE Conf. on Computational Intelligence and Games (CIG)}, publisher={IEEE},
author={Wistuba, Martin and Schaefers, Lars and Platzner, Marco}, year={2012},
pages={91–99} }'
chicago: Wistuba, Martin, Lars Schaefers, and Marco Platzner. “Comparison of Bayesian
Move Prediction Systems for Computer Go.” In Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), 91–99. IEEE, 2012. https://doi.org/10.1109/CIG.2012.6374143.
ieee: M. Wistuba, L. Schaefers, and M. Platzner, “Comparison of Bayesian Move Prediction
Systems for Computer Go,” in Proc. IEEE Conf. on Computational Intelligence
and Games (CIG), 2012, pp. 91–99.
mla: Wistuba, Martin, et al. “Comparison of Bayesian Move Prediction Systems for
Computer Go.” Proc. IEEE Conf. on Computational Intelligence and Games (CIG),
IEEE, 2012, pp. 91–99, doi:10.1109/CIG.2012.6374143.
short: 'M. Wistuba, L. Schaefers, M. Platzner, in: Proc. IEEE Conf. on Computational
Intelligence and Games (CIG), IEEE, 2012, pp. 91–99.'
date_created: 2018-03-29T14:59:35Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
- _id: '78'
doi: 10.1109/CIG.2012.6374143
page: 91-99
publication: Proc. IEEE Conf. on Computational Intelligence and Games (CIG)
publisher: IEEE
status: public
title: Comparison of Bayesian Move Prediction Systems for Computer Go
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2104'
author:
- first_name: Tobias
full_name: Schlemmer, Tobias
last_name: Schlemmer
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
citation:
ama: 'Schlemmer T, Grunzke R, Gesing S, et al. Generic User Management for Science
Gateways via Virtual Organizations. In: Proc. EGI Technical Forum. ; 2012.'
apa: Schlemmer, T., Grunzke, R., Gesing, S., Krüger, J., Birkenheuer, G., Müller-Pfefferkorn,
R., & Kohlbacher, O. (2012). Generic User Management for Science Gateways
via Virtual Organizations. In Proc. EGI Technical Forum.
bibtex: '@inproceedings{Schlemmer_Grunzke_Gesing_Krüger_Birkenheuer_Müller-Pfefferkorn_Kohlbacher_2012,
title={Generic User Management for Science Gateways via Virtual Organizations},
booktitle={Proc. EGI Technical Forum}, author={Schlemmer, Tobias and Grunzke,
Richard and Gesing, Sandra and Krüger, Jens and Birkenheuer, Georg and Müller-Pfefferkorn,
Ralph and Kohlbacher, Oliver}, year={2012} }'
chicago: Schlemmer, Tobias, Richard Grunzke, Sandra Gesing, Jens Krüger, Georg Birkenheuer,
Ralph Müller-Pfefferkorn, and Oliver Kohlbacher. “Generic User Management for
Science Gateways via Virtual Organizations.” In Proc. EGI Technical Forum,
2012.
ieee: T. Schlemmer et al., “Generic User Management for Science Gateways
via Virtual Organizations,” in Proc. EGI Technical Forum, 2012.
mla: Schlemmer, Tobias, et al. “Generic User Management for Science Gateways via
Virtual Organizations.” Proc. EGI Technical Forum, 2012.
short: 'T. Schlemmer, R. Grunzke, S. Gesing, J. Krüger, G. Birkenheuer, R. Müller-Pfefferkorn,
O. Kohlbacher, in: Proc. EGI Technical Forum, 2012.'
date_created: 2018-03-29T15:00:48Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
publication: Proc. EGI Technical Forum
status: public
title: Generic User Management for Science Gateways via Virtual Organizations
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2105'
author:
- first_name: Giuseppe
full_name: Congiu, Giuseppe
last_name: Congiu
- first_name: Matthias
full_name: Grawinkel, Matthias
last_name: Grawinkel
- first_name: Sai
full_name: Narasimhamurthy, Sai
last_name: Narasimhamurthy
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
citation:
ama: 'Congiu G, Grawinkel M, Narasimhamurthy S, Brinkmann A. One Phase Commit: A
Low Overhead Atomic Commitment Protocol for Scalable Metadata Services. In: Proc.
Workshop on Interfaces and Architectures for Scientific Data Storage (IASDS).
IEEE; 2012:16-24. doi:10.1109/ClusterW.2012.16'
apa: 'Congiu, G., Grawinkel, M., Narasimhamurthy, S., & Brinkmann, A. (2012).
One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services. In Proc. Workshop on Interfaces and Architectures for Scientific
Data Storage (IASDS) (pp. 16–24). IEEE. https://doi.org/10.1109/ClusterW.2012.16'
bibtex: '@inproceedings{Congiu_Grawinkel_Narasimhamurthy_Brinkmann_2012, title={One
Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services}, DOI={10.1109/ClusterW.2012.16},
booktitle={Proc. Workshop on Interfaces and Architectures for Scientific Data
Storage (IASDS)}, publisher={IEEE}, author={Congiu, Giuseppe and Grawinkel, Matthias
and Narasimhamurthy, Sai and Brinkmann, André}, year={2012}, pages={16–24} }'
chicago: 'Congiu, Giuseppe, Matthias Grawinkel, Sai Narasimhamurthy, and André Brinkmann.
“One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services.” In Proc. Workshop on Interfaces and Architectures for Scientific
Data Storage (IASDS), 16–24. IEEE, 2012. https://doi.org/10.1109/ClusterW.2012.16.'
ieee: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, and A. Brinkmann, “One Phase
Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata Services,”
in Proc. Workshop on Interfaces and Architectures for Scientific Data Storage
(IASDS), 2012, pp. 16–24.'
mla: 'Congiu, Giuseppe, et al. “One Phase Commit: A Low Overhead Atomic Commitment
Protocol for Scalable Metadata Services.” Proc. Workshop on Interfaces and
Architectures for Scientific Data Storage (IASDS), IEEE, 2012, pp. 16–24,
doi:10.1109/ClusterW.2012.16.'
short: 'G. Congiu, M. Grawinkel, S. Narasimhamurthy, A. Brinkmann, in: Proc. Workshop
on Interfaces and Architectures for Scientific Data Storage (IASDS), IEEE, 2012,
pp. 16–24.'
date_created: 2018-03-29T15:02:15Z
date_updated: 2022-01-06T06:54:42Z
department:
- _id: '27'
doi: 10.1109/ClusterW.2012.16
page: 16-24
publication: Proc. Workshop on Interfaces and Architectures for Scientific Data Storage
(IASDS)
publisher: IEEE
status: public
title: 'One Phase Commit: A Low Overhead Atomic Commitment Protocol for Scalable Metadata
Services'
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2107'
author:
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: Dirk
full_name: Blunk, Dirk
last_name: Blunk
- first_name: Sebastian
full_name: Breuers, Sebastian
last_name: Breuers
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Sonja
full_name: Herres-Pawlis, Sonja
last_name: Herres-Pawlis
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Martin
full_name: Kruse, Martin
last_name: Kruse
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Patrick
full_name: Schäfer, Patrick
last_name: Schäfer
- first_name: Bernd
full_name: Schuller, Bernd
last_name: Schuller
- first_name: Thomas
full_name: Steinke, Thomas
last_name: Steinke
- first_name: Andreas
full_name: Zink, Andreas
last_name: Zink
citation:
ama: 'Grunzke R, Birkenheuer G, Blunk D, et al. A Data Driven Science Gateway for
Computational Workflows. In: Proc. UNICORE Summit. ; 2012.'
apa: Grunzke, R., Birkenheuer, G., Blunk, D., Breuers, S., Brinkmann, A., Gesing,
S., … Zink, A. (2012). A Data Driven Science Gateway for Computational Workflows.
In Proc. UNICORE Summit.
bibtex: '@inproceedings{Grunzke_Birkenheuer_Blunk_Breuers_Brinkmann_Gesing_Herres-Pawlis_Kohlbacher_Krüger_Kruse_et
al._2012, title={A Data Driven Science Gateway for Computational Workflows}, booktitle={Proc.
UNICORE Summit}, author={Grunzke, Richard and Birkenheuer, Georg and Blunk, Dirk
and Breuers, Sebastian and Brinkmann, André and Gesing, Sandra and Herres-Pawlis,
Sonja and Kohlbacher, Oliver and Krüger, Jens and Kruse, Martin and et al.}, year={2012}
}'
chicago: Grunzke, Richard, Georg Birkenheuer, Dirk Blunk, Sebastian Breuers, André
Brinkmann, Sandra Gesing, Sonja Herres-Pawlis, et al. “A Data Driven Science Gateway
for Computational Workflows.” In Proc. UNICORE Summit, 2012.
ieee: R. Grunzke et al., “A Data Driven Science Gateway for Computational
Workflows,” in Proc. UNICORE Summit, 2012.
mla: Grunzke, Richard, et al. “A Data Driven Science Gateway for Computational Workflows.”
Proc. UNICORE Summit, 2012.
short: 'R. Grunzke, G. Birkenheuer, D. Blunk, S. Breuers, A. Brinkmann, S. Gesing,
S. Herres-Pawlis, O. Kohlbacher, J. Krüger, M. Kruse, R. Müller-Pfefferkorn, P.
Schäfer, B. Schuller, T. Steinke, A. Zink, in: Proc. UNICORE Summit, 2012.'
date_created: 2018-03-29T15:06:46Z
date_updated: 2022-01-06T06:54:44Z
department:
- _id: '27'
- _id: '518'
publication: Proc. UNICORE Summit
status: public
title: A Data Driven Science Gateway for Computational Workflows
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '1789'
author:
- first_name: Jürgen
full_name: Kaiser, Jürgen
last_name: Kaiser
- first_name: Dirk
full_name: Meister, Dirk
last_name: Meister
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Sascha
full_name: Effert, Sascha
last_name: Effert
citation:
ama: 'Kaiser J, Meister D, Brinkmann A, Effert S. Design of an exact data deduplication
cluster. In: Proc. Symp. on Mass Storage Systems and Technologies (MSST).
IEEE; 2012:1-12. doi:10.1109/MSST.2012.6232380'
apa: Kaiser, J., Meister, D., Brinkmann, A., & Effert, S. (2012). Design of
an exact data deduplication cluster. In Proc. Symp. on Mass Storage Systems
and Technologies (MSST) (pp. 1–12). IEEE. https://doi.org/10.1109/MSST.2012.6232380
bibtex: '@inproceedings{Kaiser_Meister_Brinkmann_Effert_2012, title={Design of an
exact data deduplication cluster}, DOI={10.1109/MSST.2012.6232380},
booktitle={Proc. Symp. on Mass Storage Systems and Technologies (MSST)}, publisher={IEEE},
author={Kaiser, Jürgen and Meister, Dirk and Brinkmann, André and Effert, Sascha},
year={2012}, pages={1–12} }'
chicago: Kaiser, Jürgen, Dirk Meister, André Brinkmann, and Sascha Effert. “Design
of an Exact Data Deduplication Cluster.” In Proc. Symp. on Mass Storage Systems
and Technologies (MSST), 1–12. IEEE, 2012. https://doi.org/10.1109/MSST.2012.6232380.
ieee: J. Kaiser, D. Meister, A. Brinkmann, and S. Effert, “Design of an exact data
deduplication cluster,” in Proc. Symp. on Mass Storage Systems and Technologies
(MSST), 2012, pp. 1–12.
mla: Kaiser, Jürgen, et al. “Design of an Exact Data Deduplication Cluster.” Proc.
Symp. on Mass Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12,
doi:10.1109/MSST.2012.6232380.
short: 'J. Kaiser, D. Meister, A. Brinkmann, S. Effert, in: Proc. Symp. on Mass
Storage Systems and Technologies (MSST), IEEE, 2012, pp. 1–12.'
date_created: 2018-03-26T15:12:01Z
date_updated: 2022-01-06T06:53:22Z
department:
- _id: '27'
doi: 10.1109/MSST.2012.6232380
page: 1-12
publication: Proc. Symp. on Mass Storage Systems and Technologies (MSST)
publisher: IEEE
status: public
title: Design of an exact data deduplication cluster
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2171'
author:
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Sonja
full_name: Herres-Pawlis, Sonja
last_name: Herres-Pawlis
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Peter
full_name: Kacsuk, Peter
last_name: Kacsuk
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
- first_name: Miklos
full_name: Kozlovszky, Miklos
last_name: Kozlovszky
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Patrick
full_name: Schäfer, Patrick
last_name: Schäfer
- first_name: Thomas
full_name: Steinke, Thomas
last_name: Steinke
citation:
ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. The MoSGrid Community From
National to International Scale. In: Proc. EGI Community Forum. ; 2012.'
apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R.,
Kacsuk, P., … Steinke, T. (2012). The MoSGrid Community From National to International
Scale. In Proc. EGI Community Forum.
bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et
al._2012, title={The MoSGrid Community From National to International Scale},
booktitle={Proc. EGI Community Forum}, author={Gesing, Sandra and Herres-Pawlis,
Sonja and Birkenheuer, Georg and Brinkmann, André and Grunzke, Richard and Kacsuk,
Peter and Kohlbacher, Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn,
Ralph and et al.}, year={2012} }'
chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann,
Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “The MoSGrid Community
From National to International Scale.” In Proc. EGI Community Forum, 2012.
ieee: S. Gesing et al., “The MoSGrid Community From National to International
Scale,” in Proc. EGI Community Forum, 2012.
mla: Gesing, Sandra, et al. “The MoSGrid Community From National to International
Scale.” Proc. EGI Community Forum, 2012.
short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P.
Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer,
T. Steinke, in: Proc. EGI Community Forum, 2012.'
date_created: 2018-04-03T09:01:19Z
date_updated: 2022-01-06T06:55:11Z
department:
- _id: '27'
publication: Proc. EGI Community Forum
status: public
title: The MoSGrid Community From National to International Scale
type: conference
user_id: '24135'
year: '2012'
...
---
_id: '2178'
author:
- first_name: Sandra
full_name: Gesing, Sandra
last_name: Gesing
- first_name: Sonja
full_name: Herres-Pawlis, Sonja
last_name: Herres-Pawlis
- first_name: Georg
full_name: Birkenheuer, Georg
last_name: Birkenheuer
- first_name: André
full_name: Brinkmann, André
last_name: Brinkmann
- first_name: Richard
full_name: Grunzke, Richard
last_name: Grunzke
- first_name: Peter
full_name: Kacsuk, Peter
last_name: Kacsuk
- first_name: Oliver
full_name: Kohlbacher, Oliver
last_name: Kohlbacher
- first_name: Miklos
full_name: Kozlovszky, Miklos
last_name: Kozlovszky
- first_name: Jens
full_name: Krüger, Jens
last_name: Krüger
- first_name: Ralph
full_name: Müller-Pfefferkorn, Ralph
last_name: Müller-Pfefferkorn
- first_name: Patrick
full_name: Schäfer, Patrick
last_name: Schäfer
- first_name: Thomas
full_name: Steinke, Thomas
last_name: Steinke
citation:
ama: 'Gesing S, Herres-Pawlis S, Birkenheuer G, et al. A Science Gateway Getting
Ready for Serving the International Molecular Simulation Community. In: Proceedings
of Science. Vol PoS(EGICF12-EMITC2)050. ; 2012.'
apa: Gesing, S., Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Grunzke, R.,
Kacsuk, P., … Steinke, T. (2012). A Science Gateway Getting Ready for Serving
the International Molecular Simulation Community. In Proceedings of Science
(Vol. PoS(EGICF12-EMITC2)050).
bibtex: '@inproceedings{Gesing_Herres-Pawlis_Birkenheuer_Brinkmann_Grunzke_Kacsuk_Kohlbacher_Kozlovszky_Krüger_Müller-Pfefferkorn_et
al._2012, title={A Science Gateway Getting Ready for Serving the International
Molecular Simulation Community}, volume={PoS(EGICF12-EMITC2)050}, booktitle={Proceedings
of Science}, author={Gesing, Sandra and Herres-Pawlis, Sonja and Birkenheuer,
Georg and Brinkmann, André and Grunzke, Richard and Kacsuk, Peter and Kohlbacher,
Oliver and Kozlovszky, Miklos and Krüger, Jens and Müller-Pfefferkorn, Ralph and
et al.}, year={2012} }'
chicago: Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann,
Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting
Ready for Serving the International Molecular Simulation Community.” In Proceedings
of Science, Vol. PoS(EGICF12-EMITC2)050, 2012.
ieee: S. Gesing et al., “A Science Gateway Getting Ready for Serving the
International Molecular Simulation Community,” in Proceedings of Science,
2012, vol. PoS(EGICF12-EMITC2)050.
mla: Gesing, Sandra, et al. “A Science Gateway Getting Ready for Serving the International
Molecular Simulation Community.” Proceedings of Science, vol. PoS(EGICF12-EMITC2)050,
2012.
short: 'S. Gesing, S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, R. Grunzke, P.
Kacsuk, O. Kohlbacher, M. Kozlovszky, J. Krüger, R. Müller-Pfefferkorn, P. Schäfer,
T. Steinke, in: Proceedings of Science, 2012.'
date_created: 2018-04-03T09:15:35Z
date_updated: 2022-01-06T06:55:13Z
department:
- _id: '27'
publication: Proceedings of Science
status: public
title: A Science Gateway Getting Ready for Serving the International Molecular Simulation
Community
type: conference
user_id: '24135'
volume: PoS(EGICF12-EMITC2)050
year: '2012'
...
---
_id: '2106'
abstract:
- lang: eng
text: "Although the benefits of FPGAs for accelerating scientific codes are widely
acknowledged, the use of FPGA accelerators in scientific computing is not widespread
because reaping these benefits requires knowledge of hardware design methods and
tools that is typically not available with domain scientists. A promising but
hardly investigated approach is to develop tool flows that keep the common languages
for scientific code (C,C++, and Fortran) and allow the developer to augment the
source code with OpenMPlike directives for instructing the compiler which parts
of the application shall be offloaded the FPGA accelerator.\r\nIn this work we
study whether the promise of effective FPGA acceleration with an OpenMP-like programming
effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable
computer for which an OpenMP-like\r\nprogramming environment exists. As case study
we use an application from computational nanophotonics. Our results\r\nshow that
a developer without previous FPGA experience could create an FPGA-accelerated
application that is competitive to an optimized OpenMP-parallelized CPU version
running on a two socket quad-core server. Finally, we discuss our experiences
with this tool flow and the Convey HC-1 from a productivity and economic point
of view."
author:
- first_name: Björn
full_name: Meyer, Björn
last_name: Meyer
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: 'Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities –
FPGA Acceleration with an OpenMP-like Effort? In: Proc. Int. Conf. on Field
Programmable Logic and Applications (FPL). IEEE; 2012:189-196. doi:10.1109/FPL.2012.6339370'
apa: Meyer, B., Schumacher, J., Plessl, C., & Förstner, J. (2012). Convey Vector
Personalities – FPGA Acceleration with an OpenMP-like Effort? Proc. Int. Conf.
on Field Programmable Logic and Applications (FPL), 189–196. https://doi.org/10.1109/FPL.2012.6339370
bibtex: '@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector
Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={10.1109/FPL.2012.6339370},
booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian
and Förstner, Jens}, year={2012}, pages={189–196} }'
chicago: Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey
Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In Proc.
Int. Conf. on Field Programmable Logic and Applications (FPL), 189–96. IEEE,
2012. https://doi.org/10.1109/FPL.2012.6339370.
ieee: 'B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities
– FPGA Acceleration with an OpenMP-like Effort?,” in Proc. Int. Conf. on Field
Programmable Logic and Applications (FPL), 2012, pp. 189–196, doi: 10.1109/FPL.2012.6339370.'
mla: Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with
an OpenMP-like Effort?” Proc. Int. Conf. on Field Programmable Logic and Applications
(FPL), IEEE, 2012, pp. 189–96, doi:10.1109/FPL.2012.6339370.
short: 'B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on
Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.'
conference:
name: 22nd International Conference on Field Programmable Logic and Applicaitons
(FPL)
date_created: 2018-03-29T15:04:25Z
date_updated: 2023-09-26T13:39:13Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '15'
- _id: '78'
doi: 10.1109/FPL.2012.6339370
file:
- access_level: closed
content_type: application/pdf
creator: fossie
date_created: 2019-02-13T09:04:46Z
date_updated: 2019-02-13T09:04:46Z
file_id: '7638'
file_name: 2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA
acceleratin with an openmp-like programming effort.pdf
file_size: 2148787
relation: main_file
success: 1
file_date_updated: 2019-02-13T09:04:46Z
has_accepted_license: '1'
keyword:
- funding-upb-forschungspreis
- funding-maxup
- tet_topic_hpc
language:
- iso: eng
page: 189-196
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: IEEE
quality_controlled: '1'
status: public
title: Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?
type: conference
user_id: '15278'
year: '2012'
...