---
_id: '18'
abstract:
- lang: eng
text: "Branch and bound (B&B) algorithms structure the search space as a tree and
eliminate infeasible solutions early by pruning subtrees that cannot lead to a
valid or optimal solution. Custom hardware designs significantly accelerate the
execution of these algorithms. In this article, we demonstrate a high-performance
B&B implementation on FPGAs. First, we identify general elements of B&B algorithms
and describe their implementation as a finite state machine. Then, we introduce
workers that autonomously cooperate using work stealing to allow parallel execution
and full utilization of the target FPGA. Finally, we explore advantages of instance-specific
designs that target a specific problem instance to improve performance.\r\n\r\nWe
evaluate our concepts by applying them to a branch and bound problem, the reconstruction
of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that
our work stealing approach is scalable with the available resources and provides
speedups proportional to the number of workers. Instance-specific designs allow
us to achieve an overall speedup of 47 × compared to the fastest implementation
of AES key reconstruction so far. Finally, we demonstrate how instance-specific
designs can be generated just-in-time such that the provided speedups outweigh
the additional time required for design synthesis."
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Michael
full_name: Lass, Michael
id: '24135'
last_name: Lass
orcid: 0000-0002-5708-7632
- first_name: Robert
full_name: Mittendorf, Robert
last_name: Mittendorf
- first_name: Thomas
full_name: Löcke, Thomas
last_name: Löcke
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound
on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions
on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687
apa: Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017).
Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific
Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS),
10(3), 24:1-24:23. https://doi.org/10.1145/3053687
bibtex: '@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch
and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10},
DOI={10.1145/3053687}, number={3},
journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association
for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and
Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23}
}'
chicago: 'Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and
Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and
Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.'
ieee: 'H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch
and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM
Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no.
3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.'
mla: Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing
and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology
and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM),
2017, p. 24:1-24:23, doi:10.1145/3053687.
short: H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions
on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23.
date_created: 2017-07-25T14:17:32Z
date_updated: 2023-09-26T13:23:58Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3053687
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T16:04:14Z
date_updated: 2018-11-02T16:04:14Z
file_id: '5322'
file_name: a24-riebler.pdf
file_size: 2131617
relation: main_file
success: 1
file_date_updated: 2018-11-02T16:04:14Z
has_accepted_license: '1'
intvolume: ' 10'
issue: '3'
keyword:
- coldboot
language:
- iso: eng
page: 24:1-24:23
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publication_identifier:
issn:
- 1936-7406
publication_status: published
publisher: Association for Computing Machinery (ACM)
quality_controlled: '1'
status: public
title: Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific
Designs
type: journal_article
user_id: '15278'
volume: 10
year: '2017'
...
---
_id: '1589'
article_number: '082003'
author:
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
citation:
ama: 'Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network
Communication with NetIO. Journal of Physics: Conference Series. 2017;898.
doi:10.1088/1742-6596/898/8/082003'
apa: 'Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and
Low-Latency Network Communication with NetIO. Journal of Physics: Conference
Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003'
bibtex: '@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency
Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003},
number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP
Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer},
year={2017} }'
chicago: 'Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput
and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference
Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.'
ieee: 'J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency
Network Communication with NetIO,” Journal of Physics: Conference Series,
vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003.'
mla: 'Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication
with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP
Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.'
short: 'J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series
898 (2017).'
date_created: 2018-03-22T10:51:20Z
date_updated: 2023-09-26T13:24:19Z
department:
- _id: '27'
- _id: '518'
doi: 10.1088/1742-6596/898/8/082003
intvolume: ' 898'
language:
- iso: eng
publication: 'Journal of Physics: Conference Series'
publisher: IOP Publishing
quality_controlled: '1'
status: public
title: High-Throughput and Low-Latency Network Communication with NetIO
type: journal_article
user_id: '15278'
volume: 898
year: '2017'
...
---
_id: '165'
abstract:
- lang: eng
text: A broad spectrum of applications can be accelerated by offloading computation
intensive parts to reconfigurable hardware. However, to achieve speedups, the
number of loop it- erations (trip count) needs to be sufficiently large to amortize
offloading overheads. Trip counts are frequently not known at compile time, but
only at runtime just before entering a loop. Therefore, we propose to generate
code for both the CPU and the coprocessor, and defer the offloading decision to
the application runtime. We demonstrate how a toolflow, based on the LLVM compiler
framework, can automatically embed dynamic offloading de- cisions into the application
code. We perform in-depth static and dynamic analysis of pop- ular benchmarks,
which confirm the general potential of such an approach. We also pro- pose to
optimize the offloading process by decoupling the runtime decision from the loop
execution (decision slack). The feasibility of our approach is demonstrated by
a toolflow that automatically identifies suitable data-parallel loops and generates
code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow
with representative loops executed for different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding
Dynamic Offloading Decisions into Application Code. Computers and Electrical
Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and
Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers
and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021
bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021},
journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz,
Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian},
year={2016}, pages={91–111} }'
chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.'
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for
Embedding Dynamic Offloading Decisions into Application Code,” Computers and
Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.'
mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading
Decisions into Application Code.” Computers and Electrical Engineering,
vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021.
short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering
55 (2016) 91–111.
date_created: 2017-10-17T12:41:24Z
date_updated: 2023-09-26T13:26:38Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
doi: 10.1016/j.compeleceng.2016.04.021
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T12:45:47Z
date_updated: 2018-03-21T12:45:47Z
file_id: '1544'
file_name: 165-1-s2.0-S0045790616301021-main.pdf
file_size: 3037854
relation: main_file
success: 1
file_date_updated: 2018-03-21T12:45:47Z
has_accepted_license: '1'
intvolume: ' 55'
language:
- iso: eng
page: 91-111
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Computers and Electrical Engineering
publication_identifier:
issn:
- 0045-7906
publisher: Elsevier
quality_controlled: '1'
status: public
title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application
Code
type: journal_article
user_id: '15278'
volume: 55
year: '2016'
...
---
_id: '1769'
abstract:
- lang: eng
text: 'Große zylindrische Stahlprüflinge werden mittels der Methode der finiten
Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ
untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei
Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach
Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.'
author:
- first_name: Sebastian
full_name: Hegler, Sebastian
last_name: Hegler
- first_name: Christoph
full_name: Statz, Christoph
last_name: Statz
- first_name: Marco
full_name: Mütze, Marco
last_name: Mütze
- first_name: Hubert
full_name: Mooshofer, Hubert
last_name: Mooshofer
- first_name: Matthias
full_name: Goldammer, Matthias
last_name: Goldammer
- first_name: Karl
full_name: Fendt, Karl
last_name: Fendt
- first_name: Stefan
full_name: Schwarzer, Stefan
last_name: Schwarzer
- first_name: Kim
full_name: Feldhoff, Kim
last_name: Feldhoff
- first_name: Martin
full_name: Flehmig, Martin
last_name: Flehmig
- first_name: Ulf
full_name: Markwardt, Ulf
last_name: Markwardt
- first_name: Wolfgang
full_name: E. Nagel, Wolfgang
last_name: E. Nagel
- first_name: Maria
full_name: Schütte, Maria
last_name: Schütte
- first_name: Andrea
full_name: Walther, Andrea
last_name: Walther
- first_name: Michael
full_name: Meinel, Michael
last_name: Meinel
- first_name: Achim
full_name: Basermann, Achim
last_name: Basermann
- first_name: Dirk
full_name: Plettemeier, Dirk
last_name: Plettemeier
citation:
ama: Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von
Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte
Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031
apa: Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K.,
… Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm
- Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031
bibtex: '@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et
al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82},
DOI={doi:10.1515/teme-2015-0031},
number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter},
author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer,
Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff,
Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450}
}'
chicago: 'Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias
Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung
von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte
Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.'
ieee: S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm
- Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015.
mla: Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen
Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm
- Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50,
doi:doi:10.1515/teme-2015-0031.
short: S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer,
K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M.
Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450.
date_created: 2018-03-23T14:01:39Z
date_updated: 2022-01-06T06:53:17Z
department:
- _id: '27'
- _id: '104'
doi: doi:10.1515/teme-2015-0031
intvolume: ' 82'
issue: '9'
page: 440-450
publication: tm - Technisches Messen
publisher: Walter de Gruyter
status: public
title: Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große
zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung
type: journal_article
user_id: '24135'
volume: 82
year: '2015'
...
---
_id: '1772'
author:
- first_name: Jim
full_name: Torresen, Jim
last_name: Torresen
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Xin
full_name: Yao, Xin
last_name: Yao
citation:
ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest
Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205
apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20.
https://doi.org/10.1109/MC.2015.205
bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205},
number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen,
Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }'
chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive
Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015):
18–20. https://doi.org/10.1109/MC.2015.205.'
ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems
– Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20,
2015.
mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s
Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015,
pp. 18–20, doi:10.1109/MC.2015.205.
short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20.
date_created: 2018-03-23T14:06:12Z
date_updated: 2022-01-06T06:53:19Z
ddc:
- '000'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MC.2015.205
file:
- access_level: closed
content_type: application/pdf
creator: ups
date_created: 2018-11-02T15:47:45Z
date_updated: 2018-11-02T15:47:45Z
file_id: '5313'
file_name: 07163237.pdf
file_size: 5605009
relation: main_file
success: 1
file_date_updated: 2018-11-02T15:47:45Z
has_accepted_license: '1'
intvolume: ' 48'
issue: '7'
keyword:
- self-awareness
- self-expression
language:
- iso: eng
page: 18-20
project:
- _id: '1'
name: SFB 901
- _id: '4'
name: SFB 901 - Project Area C
- _id: '14'
name: SFB 901 - Subproject C2
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: IEEE Computer
publisher: IEEE Computer Society
status: public
title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction
type: journal_article
user_id: '16153'
volume: 48
year: '2015'
...
---
_id: '1774'
abstract:
- lang: eng
text: In this article an efficient numerical method to solve multiobjective optimization
problems for fluid flow governed by the Navier Stokes equations is presented.
In order to decrease the computational effort, a reduced order model is introduced
using Proper Orthogonal Decomposition and a corresponding Galerkin Projection.
A global, derivative free multiobjective optimization algorithm is applied to
compute the Pareto set (i.e. the set of optimal compromises) for the concurrent
objectives minimization of flow field fluctuations and control cost. The method
is illustrated for a 2D flow around a cylinder at Re = 100.
author:
- first_name: Sebastian
full_name: Peitz, Sebastian
last_name: Peitz
- first_name: Michael
full_name: Dellnitz, Michael
last_name: Dellnitz
citation:
ama: Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder
Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296
apa: Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow
Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614.
https://doi.org/10.1002/pamm.201510296
bibtex: '@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the
Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296},
number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian
and Dellnitz, Michael}, year={2015}, pages={613–614} }'
chicago: 'Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of
the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1
(2015): 613–14. https://doi.org/10.1002/pamm.201510296.'
ieee: S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around
a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614,
2015.
mla: Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the
Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no.
1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296.
short: S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614.
date_created: 2018-03-23T14:14:24Z
date_updated: 2022-01-06T06:53:19Z
department:
- _id: '27'
- _id: '101'
doi: 10.1002/pamm.201510296
intvolume: ' 15'
issue: '1'
page: 613-614
publication: PAMM
publication_identifier:
issn:
- 1617-7061
publisher: WILEY-VCH Verlag
status: public
title: Multiobjective Optimization of the Flow Around a Cylinder Using Model Order
Reduction
type: journal_article
user_id: '24135'
volume: 15
year: '2015'
...
---
_id: '296'
abstract:
- lang: eng
text: FPGAs are known to permit huge gains in performance and efficiency for suitable
applications but still require reduced design efforts and shorter development
cycles for wider adoption. In this work, we compare the resulting performance
of two design concepts that in different ways promise such increased productivity.
As common starting point, we employ a kernel-centric design approach, where computational
hotspots in an application are identified and individually accelerated on FPGA.
By means of a complex stereo matching application, we evaluate two fundamentally
different design philosophies and approaches for implementing the required kernels
on FPGAs. In the first implementation approach, we designed individually specialized
data flow kernels in a spatial programming language for a Maxeler FPGA platform;
in the alternative design approach, we target a vector coprocessor with large
vector lengths, which is implemented as a form of programmable overlay on the
application FPGAs of a Convey HC-1. We assess both approaches in terms of overall
system performance, raw kernel performance, and performance relative to invested
resources. After compensating for the effects of the underlying hardware platforms,
the specialized dataflow kernels on the Maxeler platform are around 3x faster
than kernels executing on the Convey vector coprocessor. In our concrete scenario,
due to trade-offs between reconfiguration overheads and exposed parallelism, the
advantage of specialized dataflow kernels is reduced to around 2.5x.
article_number: '859425'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels
and a Reusable Overlay in a Stereo-Matching Case Study. International Journal
of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425
apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International
Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425
bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between
Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015},
DOI={10.1155/2015/859425}, number={859425},
journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi},
author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015}
}'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs
between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.”
International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized
Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International
Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015,
doi: 10.1155/2015/859425.'
mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and
a Reusable Overlay in a Stereo-Matching Case Study.” International Journal
of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425.
short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable
Computing (IJRC) 2015 (2015).
date_created: 2017-10-17T12:41:49Z
date_updated: 2023-09-26T13:29:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1155/2015/859425
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:47:56Z
date_updated: 2018-03-20T07:47:56Z
file_id: '1444'
file_name: 296-859425.pdf
file_size: 2993898
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:47:56Z
has_accepted_license: '1'
intvolume: ' 2015'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: International Journal of Reconfigurable Computing (IJRC)
publisher: Hindawi
quality_controlled: '1'
status: public
title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a
Stereo-Matching Case Study
type: journal_article
user_id: '15278'
volume: 2015
year: '2015'
...
---
_id: '1768'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Peter J.
full_name: Schreier, Peter J.
last_name: Schreier
citation:
ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing.
Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z'
apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort:
Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z'
bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate
Computing}, DOI={10.1007/s00287-015-0911-z},
number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl,
Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399}
}'
chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort:
Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.'
ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate
Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.'
mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik
Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.'
short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399.
date_created: 2018-03-23T13:58:34Z
date_updated: 2023-09-26T13:30:22Z
department:
- _id: '27'
- _id: '518'
- _id: '263'
- _id: '78'
doi: 10.1007/s00287-015-0911-z
issue: '5'
keyword:
- approximate computing
- survey
language:
- iso: eng
page: 396-399
publication: Informatik Spektrum
publisher: Springer
quality_controlled: '1'
status: public
title: 'Aktuelles Schlagwort: Approximate Computing'
type: journal_article
user_id: '15278'
year: '2015'
...
---
_id: '1775'
abstract:
- lang: eng
text: The ATLAS experiment at CERN is planning full deployment of a new unified
optical link technology for connecting detector front end electronics on the timescale
of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver)
links, with transfer rates up to 10.24 Gbps, will replace existing links used
for readout, detector control and distribution of timing and trigger information.
A new class of devices will be needed to interface many GBT links to the rest
of the trigger, data-acquisition and detector control systems. In this paper FELIX
(Front End LInk eXchange) is presented, a PC-based device to route data from and
to multiple GBT links via a high-performance general purpose network capable of
a total throughput up to O(20 Tbps). FELIX implies architectural changes to the
ATLAS data acquisition system, such as the use of industry standard COTS components
early in the DAQ chain. Additionally the design and implementation of a FELIX
demonstration platform is presented and hardware and software aspects will be
discussed.
article_number: '082050'
author:
- first_name: J
full_name: Anderson, J
last_name: Anderson
- first_name: A
full_name: Borga, A
last_name: Borga
- first_name: H
full_name: Boterenbrood, H
last_name: Boterenbrood
- first_name: H
full_name: Chen, H
last_name: Chen
- first_name: K
full_name: Chen, K
last_name: Chen
- first_name: G
full_name: Drake, G
last_name: Drake
- first_name: D
full_name: Francis, D
last_name: Francis
- first_name: B
full_name: Gorini, B
last_name: Gorini
- first_name: F
full_name: Lanni, F
last_name: Lanni
- first_name: G
full_name: Lehmann Miotto, G
last_name: Lehmann Miotto
- first_name: L
full_name: Levinson, L
last_name: Levinson
- first_name: J
full_name: Narevicius, J
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A
full_name: Roich, A
last_name: Roich
- first_name: S
full_name: Ryu, S
last_name: Ryu
- first_name: F
full_name: Schreuder, F
last_name: Schreuder
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J
full_name: Vermeulen, J
last_name: Vermeulen
- first_name: J
full_name: Zhang, J
last_name: Zhang
citation:
ama: 'Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network
Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal
of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050'
apa: 'Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G.,
Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius,
J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W.,
Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach
for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics:
Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050'
bibtex: '@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann
Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing
to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050},
number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP
Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H
and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann
Miotto, G and et al.}, year={2015} }'
chicago: 'Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis,
et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End
Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series
664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.'
ieee: 'J. Anderson et al., “FELIX: a High-Throughput Network Approach for
Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics:
Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.'
mla: 'Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing
to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference
Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.'
short: 'J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis,
B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl,
A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang,
Journal of Physics: Conference Series 664 (2015).'
date_created: 2018-03-23T14:19:27Z
date_updated: 2023-09-26T13:31:23Z
department:
- _id: '27'
- _id: '518'
doi: 10.1088/1742-6596/664/8/082050
intvolume: ' 664'
language:
- iso: eng
publication: 'Journal of Physics: Conference Series'
publisher: IOP Publishing
quality_controlled: '1'
status: public
title: 'FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics
for ATLAS Upgrades'
type: journal_article
user_id: '15278'
volume: 664
year: '2015'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...