--- _id: '18' abstract: - lang: eng text: "Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.\r\n\r\nWe evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis." author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Robert full_name: Mittendorf, Robert last_name: Mittendorf - first_name: Thomas full_name: Löcke, Thomas last_name: Löcke - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Riebler H, Lass M, Mittendorf R, Löcke T, Plessl C. Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2017;10(3):24:1-24:23. doi:10.1145/3053687 apa: Riebler, H., Lass, M., Mittendorf, R., Löcke, T., & Plessl, C. (2017). Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 10(3), 24:1-24:23. https://doi.org/10.1145/3053687 bibtex: '@article{Riebler_Lass_Mittendorf_Löcke_Plessl_2017, title={Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs}, volume={10}, DOI={10.1145/3053687}, number={3}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={Association for Computing Machinery (ACM)}, author={Riebler, Heinrich and Lass, Michael and Mittendorf, Robert and Löcke, Thomas and Plessl, Christian}, year={2017}, pages={24:1-24:23} }' chicago: 'Riebler, Heinrich, Michael Lass, Robert Mittendorf, Thomas Löcke, and Christian Plessl. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10, no. 3 (2017): 24:1-24:23. https://doi.org/10.1145/3053687.' ieee: 'H. Riebler, M. Lass, R. Mittendorf, T. Löcke, and C. Plessl, “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, p. 24:1-24:23, 2017, doi: 10.1145/3053687.' mla: Riebler, Heinrich, et al. “Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 10, no. 3, Association for Computing Machinery (ACM), 2017, p. 24:1-24:23, doi:10.1145/3053687. short: H. Riebler, M. Lass, R. Mittendorf, T. Löcke, C. Plessl, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 10 (2017) 24:1-24:23. date_created: 2017-07-25T14:17:32Z date_updated: 2023-09-26T13:23:58Z ddc: - '000' department: - _id: '27' - _id: '518' doi: 10.1145/3053687 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T16:04:14Z date_updated: 2018-11-02T16:04:14Z file_id: '5322' file_name: a24-riebler.pdf file_size: 2131617 relation: main_file success: 1 file_date_updated: 2018-11-02T16:04:14Z has_accepted_license: '1' intvolume: ' 10' issue: '3' keyword: - coldboot language: - iso: eng page: 24:1-24:23 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS) publication_identifier: issn: - 1936-7406 publication_status: published publisher: Association for Computing Machinery (ACM) quality_controlled: '1' status: public title: Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs type: journal_article user_id: '15278' volume: 10 year: '2017' ... --- _id: '1589' article_number: '082003' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli citation: ama: 'Schumacher J, Plessl C, Vandelli W. High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series. 2017;898. doi:10.1088/1742-6596/898/8/082003' apa: 'Schumacher, J., Plessl, C., & Vandelli, W. (2017). High-Throughput and Low-Latency Network Communication with NetIO. Journal of Physics: Conference Series, 898, Article 082003. https://doi.org/10.1088/1742-6596/898/8/082003' bibtex: '@article{Schumacher_Plessl_Vandelli_2017, title={High-Throughput and Low-Latency Network Communication with NetIO}, volume={898}, DOI={10.1088/1742-6596/898/8/082003}, number={082003}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Schumacher, Jörn and Plessl, Christian and Vandelli, Wainer}, year={2017} }' chicago: 'Schumacher, Jörn, Christian Plessl, and Wainer Vandelli. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series 898 (2017). https://doi.org/10.1088/1742-6596/898/8/082003.' ieee: 'J. Schumacher, C. Plessl, and W. Vandelli, “High-Throughput and Low-Latency Network Communication with NetIO,” Journal of Physics: Conference Series, vol. 898, Art. no. 082003, 2017, doi: 10.1088/1742-6596/898/8/082003.' mla: 'Schumacher, Jörn, et al. “High-Throughput and Low-Latency Network Communication with NetIO.” Journal of Physics: Conference Series, vol. 898, 082003, IOP Publishing, 2017, doi:10.1088/1742-6596/898/8/082003.' short: 'J. Schumacher, C. Plessl, W. Vandelli, Journal of Physics: Conference Series 898 (2017).' date_created: 2018-03-22T10:51:20Z date_updated: 2023-09-26T13:24:19Z department: - _id: '27' - _id: '518' doi: 10.1088/1742-6596/898/8/082003 intvolume: ' 898' language: - iso: eng publication: 'Journal of Physics: Conference Series' publisher: IOP Publishing quality_controlled: '1' status: public title: High-Throughput and Low-Latency Network Communication with NetIO type: journal_article user_id: '15278' volume: 898 year: '2017' ... --- _id: '165' abstract: - lang: eng text: A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021 apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021 bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }' chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.' ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.' mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021. short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111. date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:26:38Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1016/j.compeleceng.2016.04.021 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:45:47Z date_updated: 2018-03-21T12:45:47Z file_id: '1544' file_name: 165-1-s2.0-S0045790616301021-main.pdf file_size: 3037854 relation: main_file success: 1 file_date_updated: 2018-03-21T12:45:47Z has_accepted_license: '1' intvolume: ' 55' language: - iso: eng page: 91-111 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Computers and Electrical Engineering publication_identifier: issn: - 0045-7906 publisher: Elsevier quality_controlled: '1' status: public title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code type: journal_article user_id: '15278' volume: 55 year: '2016' ... --- _id: '1769' abstract: - lang: eng text: 'Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.' author: - first_name: Sebastian full_name: Hegler, Sebastian last_name: Hegler - first_name: Christoph full_name: Statz, Christoph last_name: Statz - first_name: Marco full_name: Mütze, Marco last_name: Mütze - first_name: Hubert full_name: Mooshofer, Hubert last_name: Mooshofer - first_name: Matthias full_name: Goldammer, Matthias last_name: Goldammer - first_name: Karl full_name: Fendt, Karl last_name: Fendt - first_name: Stefan full_name: Schwarzer, Stefan last_name: Schwarzer - first_name: Kim full_name: Feldhoff, Kim last_name: Feldhoff - first_name: Martin full_name: Flehmig, Martin last_name: Flehmig - first_name: Ulf full_name: Markwardt, Ulf last_name: Markwardt - first_name: Wolfgang full_name: E. Nagel, Wolfgang last_name: E. Nagel - first_name: Maria full_name: Schütte, Maria last_name: Schütte - first_name: Andrea full_name: Walther, Andrea last_name: Walther - first_name: Michael full_name: Meinel, Michael last_name: Meinel - first_name: Achim full_name: Basermann, Achim last_name: Basermann - first_name: Dirk full_name: Plettemeier, Dirk last_name: Plettemeier citation: ama: Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031 apa: Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K., … Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm - Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031 bibtex: '@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82}, DOI={doi:10.1515/teme-2015-0031}, number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter}, author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer, Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff, Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450} }' chicago: 'Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.' ieee: S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm - Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015. mla: Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50, doi:doi:10.1515/teme-2015-0031. short: S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450. date_created: 2018-03-23T14:01:39Z date_updated: 2022-01-06T06:53:17Z department: - _id: '27' - _id: '104' doi: doi:10.1515/teme-2015-0031 intvolume: ' 82' issue: '9' page: 440-450 publication: tm - Technisches Messen publisher: Walter de Gruyter status: public title: Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung type: journal_article user_id: '24135' volume: 82 year: '2015' ... --- _id: '1772' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Xin full_name: Yao, Xin last_name: Yao citation: ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205 apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205 bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }' chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.' ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015. mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205. short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20. date_created: 2018-03-23T14:06:12Z date_updated: 2022-01-06T06:53:19Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MC.2015.205 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:47:45Z date_updated: 2018-11-02T15:47:45Z file_id: '5313' file_name: 07163237.pdf file_size: 5605009 relation: main_file success: 1 file_date_updated: 2018-11-02T15:47:45Z has_accepted_license: '1' intvolume: ' 48' issue: '7' keyword: - self-awareness - self-expression language: - iso: eng page: 18-20 project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: IEEE Computer publisher: IEEE Computer Society status: public title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction type: journal_article user_id: '16153' volume: 48 year: '2015' ... --- _id: '1774' abstract: - lang: eng text: In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100. author: - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz citation: ama: Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296 apa: Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296 bibtex: '@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }' chicago: 'Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.' ieee: S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015. mla: Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296. short: S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614. date_created: 2018-03-23T14:14:24Z date_updated: 2022-01-06T06:53:19Z department: - _id: '27' - _id: '101' doi: 10.1002/pamm.201510296 intvolume: ' 15' issue: '1' page: 613-614 publication: PAMM publication_identifier: issn: - 1617-7061 publisher: WILEY-VCH Verlag status: public title: Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction type: journal_article user_id: '24135' volume: 15 year: '2015' ... --- _id: '296' abstract: - lang: eng text: FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. article_number: '859425' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425 apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425 bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.' mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425. short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015). date_created: 2017-10-17T12:41:49Z date_updated: 2023-09-26T13:29:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2015/859425 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:47:56Z date_updated: 2018-03-20T07:47:56Z file_id: '1444' file_name: 296-859425.pdf file_size: 2993898 relation: main_file success: 1 file_date_updated: 2018-03-20T07:47:56Z has_accepted_license: '1' intvolume: ' 2015' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: International Journal of Reconfigurable Computing (IJRC) publisher: Hindawi quality_controlled: '1' status: public title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study type: journal_article user_id: '15278' volume: 2015 year: '2015' ... --- _id: '1768' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Peter J. full_name: Schreier, Peter J. last_name: Schreier citation: ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z' apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z' bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }' chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.' ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.' mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.' short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399. date_created: 2018-03-23T13:58:34Z date_updated: 2023-09-26T13:30:22Z department: - _id: '27' - _id: '518' - _id: '263' - _id: '78' doi: 10.1007/s00287-015-0911-z issue: '5' keyword: - approximate computing - survey language: - iso: eng page: 396-399 publication: Informatik Spektrum publisher: Springer quality_controlled: '1' status: public title: 'Aktuelles Schlagwort: Approximate Computing' type: journal_article user_id: '15278' year: '2015' ... --- _id: '1775' abstract: - lang: eng text: The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed. article_number: '082050' author: - first_name: J full_name: Anderson, J last_name: Anderson - first_name: A full_name: Borga, A last_name: Borga - first_name: H full_name: Boterenbrood, H last_name: Boterenbrood - first_name: H full_name: Chen, H last_name: Chen - first_name: K full_name: Chen, K last_name: Chen - first_name: G full_name: Drake, G last_name: Drake - first_name: D full_name: Francis, D last_name: Francis - first_name: B full_name: Gorini, B last_name: Gorini - first_name: F full_name: Lanni, F last_name: Lanni - first_name: G full_name: Lehmann Miotto, G last_name: Lehmann Miotto - first_name: L full_name: Levinson, L last_name: Levinson - first_name: J full_name: Narevicius, J last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A full_name: Roich, A last_name: Roich - first_name: S full_name: Ryu, S last_name: Ryu - first_name: F full_name: Schreuder, F last_name: Schreuder - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J full_name: Vermeulen, J last_name: Vermeulen - first_name: J full_name: Zhang, J last_name: Zhang citation: ama: 'Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050' apa: 'Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics: Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050' bibtex: '@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050}, number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann Miotto, G and et al.}, year={2015} }' chicago: 'Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis, et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series 664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.' ieee: 'J. Anderson et al., “FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics: Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.' mla: 'Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.' short: 'J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang, Journal of Physics: Conference Series 664 (2015).' date_created: 2018-03-23T14:19:27Z date_updated: 2023-09-26T13:31:23Z department: - _id: '27' - _id: '518' doi: 10.1088/1742-6596/664/8/082050 intvolume: ' 664' language: - iso: eng publication: 'Journal of Physics: Conference Series' publisher: IOP Publishing quality_controlled: '1' status: public title: 'FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades' type: journal_article user_id: '15278' volume: 664 year: '2015' ... --- _id: '363' abstract: - lang: eng text: Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Hendrik full_name: Hangmann, Hendrik last_name: Hangmann - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems. 2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001 apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001 bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }' chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.' ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.' mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001. short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919. date_created: 2017-10-17T12:42:02Z date_updated: 2023-09-26T13:33:06Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2013.12.001 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:20:31Z date_updated: 2018-03-20T07:20:31Z file_id: '1408' file_name: 363-plessl13_micpro.pdf file_size: 1499996 relation: main_file success: 1 file_date_updated: 2018-03-20T07:20:31Z has_accepted_license: '1' intvolume: ' 38' issue: 8, Part B language: - iso: eng page: 911-919 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Microprocessors and Microsystems publisher: Elsevier quality_controlled: '1' status: public title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators type: journal_article user_id: '15278' volume: 38 year: '2014' ... --- _id: '365' abstract: - lang: eng text: Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems. article_number: '13' author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596 apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13. https://doi.org/10.1145/2617596 bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }' chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no. 2 (2014). https://doi.org/10.1145/2617596. ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no. 13, 2014, doi: 10.1145/2617596.' mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596. short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014). date_created: 2017-10-17T12:42:03Z date_updated: 2023-09-26T13:33:31Z ddc: - '040' department: - _id: '27' - _id: '78' - _id: '518' doi: 10.1145/2617596 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:19:19Z date_updated: 2018-03-20T07:19:19Z file_id: '1406' file_name: 365-plessl14_trets_01.pdf file_size: 916052 relation: main_file success: 1 file_date_updated: 2018-03-20T07:19:19Z has_accepted_license: '1' intvolume: ' 7' issue: '2' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS) publisher: ACM quality_controlled: '1' status: public title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores type: journal_article user_id: '15278' volume: 7 year: '2014' ... --- _id: '328' abstract: - lang: eng text: The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Ariane full_name: Keller, Ariane last_name: Keller - first_name: Enno full_name: Lübbers, Enno last_name: Lübbers - first_name: Bernhard full_name: Plattner, Bernhard last_name: Plattner - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110 apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., & Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110 bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }' chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.' ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.' mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110. short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71. date_created: 2017-10-17T12:41:55Z date_updated: 2023-09-26T13:32:31Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MM.2013.110 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:31:40Z date_updated: 2018-03-20T07:31:40Z file_id: '1426' file_name: 328-plessl14_micro_01.pdf file_size: 1877185 relation: main_file success: 1 file_date_updated: 2018-03-20T07:31:40Z has_accepted_license: '1' intvolume: ' 34' issue: '1' language: - iso: eng page: 60-71 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: IEEE Micro publisher: IEEE quality_controlled: '1' status: public title: ReconOS - An Operating System Approach for Reconfigurable Computing type: journal_article user_id: '15278' volume: 34 year: '2014' ... --- _id: '1779' author: - first_name: Heiner full_name: Giefers, Heiner last_name: Giefers - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Jens full_name: Förstner, Jens id: '158' last_name: Förstner orcid: 0000-0001-7059-9862 citation: ama: Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News. 2014;41(5):65-70. doi:10.1145/2641361.2641372 apa: Giefers, H., Plessl, C., & Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. ACM SIGARCH Computer Architecture News, 41(5), 65–70. https://doi.org/10.1145/2641361.2641372 bibtex: '@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={10.1145/2641361.2641372}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }' chicago: 'Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News 41, no. 5 (2014): 65–70. https://doi.org/10.1145/2641361.2641372.' ieee: 'H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, pp. 65–70, 2014, doi: 10.1145/2641361.2641372.' mla: Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” ACM SIGARCH Computer Architecture News, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:10.1145/2641361.2641372. short: H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70. date_created: 2018-03-26T13:42:34Z date_updated: 2023-09-26T13:35:58Z department: - _id: '27' - _id: '518' - _id: '61' - _id: '78' doi: 10.1145/2641361.2641372 intvolume: ' 41' issue: '5' keyword: - funding-maxup - tet_topic_hpc language: - iso: eng page: 65-70 publication: ACM SIGARCH Computer Architecture News publication_identifier: issn: - 0163-5964 publisher: ACM quality_controlled: '1' status: public title: Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers type: journal_article user_id: '15278' volume: 41 year: '2014' ... --- _id: '1792' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Soydan full_name: Redif, Soydan last_name: Redif citation: ama: Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans on Very Large Scale Integration (VLSI) Systems. 2013;22(3):522-536. doi:10.1109/TVLSI.2013.2248069 apa: Kasap, S., & Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(3), 522–536. https://doi.org/10.1109/TVLSI.2013.2248069 bibtex: '@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={10.1109/TVLSI.2013.2248069}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }' chicago: 'Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22, no. 3 (2013): 522–36. https://doi.org/10.1109/TVLSI.2013.2248069.' ieee: S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, pp. 522–536, 2013. mla: Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:10.1109/TVLSI.2013.2248069. short: S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536. date_created: 2018-03-26T15:15:03Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' - _id: '78' doi: 10.1109/TVLSI.2013.2248069 intvolume: ' 22' issue: '3' page: 522-536 publication: IEEE Trans. on Very Large Scale Integration (VLSI) Systems publisher: IEEE status: public title: Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices type: journal_article user_id: '24135' volume: 22 year: '2013' ... --- _id: '1965' abstract: - lang: eng text: Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations. author: - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Jens full_name: Krüger, Jens last_name: Krüger citation: ama: Niehörster O, Simon J, Brinkmann A, Keller A, Krüger J. Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing. 2012;10(3):553-577. doi:10.1007/s10723-012-9230-7 apa: Niehörster, O., Simon, J., Brinkmann, A., Keller, A., & Krüger, J. (2012). Cost-aware and SLO Fulfilling Software as a Service. Journal of Grid Computing, 10(3), 553–577. https://doi.org/10.1007/s10723-012-9230-7 bibtex: '@article{Niehörster_Simon_Brinkmann_Keller_Krüger_2012, title={Cost-aware and SLO Fulfilling Software as a Service}, volume={10}, DOI={10.1007/s10723-012-9230-7}, number={3}, journal={Journal of Grid Computing}, author={Niehörster, Oliver and Simon, Jens and Brinkmann, André and Keller, Axel and Krüger, Jens}, year={2012}, pages={553–577} }' chicago: 'Niehörster, Oliver, Jens Simon, André Brinkmann, Axel Keller, and Jens Krüger. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing 10, no. 3 (2012): 553–77. https://doi.org/10.1007/s10723-012-9230-7.' ieee: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, and J. Krüger, “Cost-aware and SLO Fulfilling Software as a Service,” Journal of Grid Computing, vol. 10, no. 3, pp. 553–577, 2012. mla: Niehörster, Oliver, et al. “Cost-Aware and SLO Fulfilling Software as a Service.” Journal of Grid Computing, vol. 10, no. 3, 2012, pp. 553–77, doi:10.1007/s10723-012-9230-7. short: O. Niehörster, J. Simon, A. Brinkmann, A. Keller, J. Krüger, Journal of Grid Computing 10 (2012) 553–577. date_created: 2018-03-29T11:16:18Z date_updated: 2022-01-06T06:54:09Z department: - _id: '27' doi: 10.1007/s10723-012-9230-7 intvolume: ' 10' issue: '3' language: - iso: eng page: 553-577 publication: Journal of Grid Computing publication_status: published status: public title: Cost-aware and SLO Fulfilling Software as a Service type: journal_article user_id: '15274' volume: 10 year: '2012' ... --- _id: '2102' author: - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Martin full_name: Wewior, Martin last_name: Wewior - first_name: Patrick full_name: Schäfer, Patrick last_name: Schäfer - first_name: Bernd full_name: Schuller, Bernd last_name: Schuller - first_name: Johannes full_name: Schuster, Johannes last_name: Schuster - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Sebastian full_name: Breuers, Sebastian last_name: Breuers - first_name: Ákos full_name: Balaskó, Ákos last_name: Balaskó - first_name: Miklos full_name: Kozlovszky, Miklos last_name: Kozlovszky - first_name: Anna full_name: Szikszay Fabri, Anna last_name: Szikszay Fabri - first_name: Lars full_name: Packschies, Lars last_name: Packschies - first_name: Peter full_name: Kacsuk, Peter last_name: Kacsuk - first_name: Dirk full_name: Blunk, Dirk last_name: Blunk - first_name: Thomas full_name: Steinke, Thomas last_name: Steinke - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Gregor full_name: Fels, Gregor last_name: Fels - first_name: Ralph full_name: Müller-Pfefferkorn, Ralph last_name: Müller-Pfefferkorn - first_name: René full_name: Jäkel, René last_name: Jäkel - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher citation: ama: Gesing S, Grunzke R, Krüger J, et al. A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics. Journal of Grid Computing. 2012;10(4):769-790. doi:10.1007/s10723-012-9247-y apa: Gesing, S., Grunzke, R., Krüger, J., Birkenheuer, G., Wewior, M., Schäfer, P., … Kohlbacher, O. (2012). A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics. Journal of Grid Computing, 10(4), 769–790. https://doi.org/10.1007/s10723-012-9247-y bibtex: '@article{Gesing_Grunzke_Krüger_Birkenheuer_Wewior_Schäfer_Schuller_Schuster_Herres-Pawlis_Breuers_et al._2012, title={A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics}, volume={10}, DOI={10.1007/s10723-012-9247-y}, number={4}, journal={Journal of Grid Computing}, publisher={Springer}, author={Gesing, Sandra and Grunzke, Richard and Krüger, Jens and Birkenheuer, Georg and Wewior, Martin and Schäfer, Patrick and Schuller, Bernd and Schuster, Johannes and Herres-Pawlis, Sonja and Breuers, Sebastian and et al.}, year={2012}, pages={769–790} }' chicago: 'Gesing, Sandra, Richard Grunzke, Jens Krüger, Georg Birkenheuer, Martin Wewior, Patrick Schäfer, Bernd Schuller, et al. “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics.” Journal of Grid Computing 10, no. 4 (2012): 769–90. https://doi.org/10.1007/s10723-012-9247-y.' ieee: S. Gesing et al., “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics,” Journal of Grid Computing, vol. 10, no. 4, pp. 769–790, 2012. mla: Gesing, Sandra, et al. “A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics.” Journal of Grid Computing, vol. 10, no. 4, Springer, 2012, pp. 769–90, doi:10.1007/s10723-012-9247-y. short: S. Gesing, R. Grunzke, J. Krüger, G. Birkenheuer, M. Wewior, P. Schäfer, B. Schuller, J. Schuster, S. Herres-Pawlis, S. Breuers, Á. Balaskó, M. Kozlovszky, A. Szikszay Fabri, L. Packschies, P. Kacsuk, D. Blunk, T. Steinke, A. Brinkmann, G. Fels, R. Müller-Pfefferkorn, R. Jäkel, O. Kohlbacher, Journal of Grid Computing 10 (2012) 769–790. date_created: 2018-03-29T14:53:52Z date_updated: 2022-01-06T06:54:42Z department: - _id: '27' doi: 10.1007/s10723-012-9247-y intvolume: ' 10' issue: '4' page: 769-790 publication: Journal of Grid Computing publisher: Springer status: public title: A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics type: journal_article user_id: '24135' volume: 10 year: '2012' ... --- _id: '2172' author: - first_name: Kris full_name: Thielemans, Kris last_name: Thielemans - first_name: Charalampos full_name: Tsoumpas, Charalampos last_name: Tsoumpas - first_name: Sanida full_name: Mustafovic, Sanida last_name: Mustafovic - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Pablo full_name: Aguiar, Pablo last_name: Aguiar - first_name: Nikolaos full_name: Dikaios, Nikolaos last_name: Dikaios - first_name: Matthew full_name: W Jacobson, Matthew last_name: W Jacobson citation: ama: 'Thielemans K, Tsoumpas C, Mustafovic S, et al. STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology. 2012;57(4):867-883. doi:10.1088/0031-9155/57/4/867' apa: 'Thielemans, K., Tsoumpas, C., Mustafovic, S., Beisel, T., Aguiar, P., Dikaios, N., & W Jacobson, M. (2012). STIR: Software for Tomographic Image Reconstruction Release 2. Physics in Medicine and Biology, 57(4), 867–883. https://doi.org/10.1088/0031-9155/57/4/867' bibtex: '@article{Thielemans_Tsoumpas_Mustafovic_Beisel_Aguiar_Dikaios_W Jacobson_2012, title={STIR: Software for Tomographic Image Reconstruction Release 2}, volume={57}, DOI={10.1088/0031-9155/57/4/867}, number={4}, journal={Physics in Medicine and Biology}, publisher={IOP Publishing}, author={Thielemans, Kris and Tsoumpas, Charalampos and Mustafovic, Sanida and Beisel, Tobias and Aguiar, Pablo and Dikaios, Nikolaos and W Jacobson, Matthew}, year={2012}, pages={867–883} }' chicago: 'Thielemans, Kris, Charalampos Tsoumpas, Sanida Mustafovic, Tobias Beisel, Pablo Aguiar, Nikolaos Dikaios, and Matthew W Jacobson. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology 57, no. 4 (2012): 867–83. https://doi.org/10.1088/0031-9155/57/4/867.' ieee: 'K. Thielemans et al., “STIR: Software for Tomographic Image Reconstruction Release 2,” Physics in Medicine and Biology, vol. 57, no. 4, pp. 867–883, 2012.' mla: 'Thielemans, Kris, et al. “STIR: Software for Tomographic Image Reconstruction Release 2.” Physics in Medicine and Biology, vol. 57, no. 4, IOP Publishing, 2012, pp. 867–83, doi:10.1088/0031-9155/57/4/867.' short: K. Thielemans, C. Tsoumpas, S. Mustafovic, T. Beisel, P. Aguiar, N. Dikaios, M. W Jacobson, Physics in Medicine and Biology 57 (2012) 867–883. date_created: 2018-04-03T09:02:27Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1088/0031-9155/57/4/867 intvolume: ' 57' issue: '4' page: 867-883 publication: Physics in Medicine and Biology publisher: IOP Publishing status: public title: 'STIR: Software for Tomographic Image Reconstruction Release 2' type: journal_article user_id: '24135' volume: 57 year: '2012' ... --- _id: '2173' author: - first_name: Soydan full_name: Redif, Soydan last_name: Redif - first_name: Server full_name: Kasap, Server last_name: Kasap citation: ama: Redif S, Kasap S. Parallel algorithm for computation of second-order sequential best rotations. Int Journal of Electronics. 2012;100(12):1646-1651. doi:10.1080/00207217.2012.751343 apa: Redif, S., & Kasap, S. (2012). Parallel algorithm for computation of second-order sequential best rotations. Int. Journal of Electronics, 100(12), 1646–1651. https://doi.org/10.1080/00207217.2012.751343 bibtex: '@article{Redif_Kasap_2012, title={Parallel algorithm for computation of second-order sequential best rotations}, volume={100}, DOI={10.1080/00207217.2012.751343}, number={12}, journal={Int. Journal of Electronics}, publisher={Taylor & Francis}, author={Redif, Soydan and Kasap, Server}, year={2012}, pages={1646–1651} }' chicago: 'Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics 100, no. 12 (2012): 1646–51. https://doi.org/10.1080/00207217.2012.751343.' ieee: S. Redif and S. Kasap, “Parallel algorithm for computation of second-order sequential best rotations,” Int. Journal of Electronics, vol. 100, no. 12, pp. 1646–1651, 2012. mla: Redif, Soydan, and Server Kasap. “Parallel Algorithm for Computation of Second-Order Sequential Best Rotations.” Int. Journal of Electronics, vol. 100, no. 12, Taylor & Francis, 2012, pp. 1646–51, doi:10.1080/00207217.2012.751343. short: S. Redif, S. Kasap, Int. Journal of Electronics 100 (2012) 1646–1651. date_created: 2018-04-03T09:05:36Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' doi: 10.1080/00207217.2012.751343 intvolume: ' 100' issue: '12' page: 1646-1651 publication: Int. Journal of Electronics publisher: Taylor & Francis status: public title: Parallel algorithm for computation of second-order sequential best rotations type: journal_article user_id: '24135' volume: 100 year: '2012' ... --- _id: '2174' author: - first_name: Server full_name: Kasap, Server last_name: Kasap - first_name: Khaled full_name: Benkrid, Khaled last_name: Benkrid citation: ama: Kasap S, Benkrid K. Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers. 2012;7(6):1312-1328. apa: Kasap, S., & Benkrid, K. (2012). Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer. Journal of Computers, 7(6), 1312–1328. bibtex: '@article{Kasap_Benkrid_2012, title={Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer}, volume={7}, number={6}, journal={Journal of Computers}, publisher={Academy Publishers}, author={Kasap, Server and Benkrid, Khaled}, year={2012}, pages={1312–1328} }' chicago: 'Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers 7, no. 6 (2012): 1312–28.' ieee: S. Kasap and K. Benkrid, “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer,” Journal of Computers, vol. 7, no. 6, pp. 1312–1328, 2012. mla: Kasap, Server, and Khaled Benkrid. “Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer.” Journal of Computers, vol. 7, no. 6, Academy Publishers, 2012, pp. 1312–28. short: S. Kasap, K. Benkrid, Journal of Computers 7 (2012) 1312–1328. date_created: 2018-04-03T09:08:00Z date_updated: 2022-01-06T06:55:12Z department: - _id: '27' - _id: '78' intvolume: ' 7' issue: '6' page: 1312-1328 publication: Journal of Computers publisher: Academy Publishers status: public title: Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer type: journal_article user_id: '24135' volume: 7 year: '2012' ... --- _id: '2176' author: - first_name: Sonja full_name: Herres-Pawlis, Sonja last_name: Herres-Pawlis - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Sandra full_name: Gesing, Sandra last_name: Gesing - first_name: Richard full_name: Grunzke, Richard last_name: Grunzke - first_name: René full_name: Jäkel, René last_name: Jäkel - first_name: Oliver full_name: Kohlbacher, Oliver last_name: Kohlbacher - first_name: Jens full_name: Krüger, Jens last_name: Krüger - first_name: Ines full_name: Dos Santos Vieira, Ines last_name: Dos Santos Vieira citation: ama: Herres-Pawlis S, Birkenheuer G, Brinkmann A, et al. Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics. 2012;175:142-151. doi:10.3233/978-1-61499-054-3-142 apa: Herres-Pawlis, S., Birkenheuer, G., Brinkmann, A., Gesing, S., Grunzke, R., Jäkel, R., … Dos Santos Vieira, I. (2012). Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway. Studies in Health Technology and Informatics, 175, 142–151. https://doi.org/10.3233/978-1-61499-054-3-142 bibtex: '@article{Herres-Pawlis_Birkenheuer_Brinkmann_Gesing_Grunzke_Jäkel_Kohlbacher_Krüger_Dos Santos Vieira_2012, title={Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway}, volume={175}, DOI={10.3233/978-1-61499-054-3-142}, journal={Studies in Health Technology and Informatics}, publisher={IOP Publishing}, author={Herres-Pawlis, Sonja and Birkenheuer, Georg and Brinkmann, André and Gesing, Sandra and Grunzke, Richard and Jäkel, René and Kohlbacher, Oliver and Krüger, Jens and Dos Santos Vieira, Ines}, year={2012}, pages={142–151} }' chicago: 'Herres-Pawlis, Sonja, Georg Birkenheuer, André Brinkmann, Sandra Gesing, Richard Grunzke, René Jäkel, Oliver Kohlbacher, Jens Krüger, and Ines Dos Santos Vieira. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics 175 (2012): 142–51. https://doi.org/10.3233/978-1-61499-054-3-142.' ieee: S. Herres-Pawlis et al., “Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway,” Studies in Health Technology and Informatics, vol. 175, pp. 142–151, 2012. mla: Herres-Pawlis, Sonja, et al. “Workflow-Enhanced Conformational Analysis of Guanidine Zinc Complexes via a Science Gateway.” Studies in Health Technology and Informatics, vol. 175, IOP Publishing, 2012, pp. 142–51, doi:10.3233/978-1-61499-054-3-142. short: S. Herres-Pawlis, G. Birkenheuer, A. Brinkmann, S. Gesing, R. Grunzke, R. Jäkel, O. Kohlbacher, J. Krüger, I. Dos Santos Vieira, Studies in Health Technology and Informatics 175 (2012) 142–151. date_created: 2018-04-03T09:12:01Z date_updated: 2022-01-06T06:55:13Z department: - _id: '27' doi: 10.3233/978-1-61499-054-3-142 intvolume: ' 175' page: 142-151 publication: Studies in Health Technology and Informatics publisher: IOP Publishing status: public title: Workflow-enhanced conformational analysis of guanidine zinc complexes via a science gateway type: journal_article user_id: '24135' volume: 175 year: '2012' ... --- _id: '2108' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems. 2012;36(2):110-126. doi:10.1016/j.micpro.2011.04.002' apa: 'Schumacher, T., Plessl, C., & Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. Microprocessors and Microsystems, 36(2), 110–126. https://doi.org/10.1016/j.micpro.2011.04.002' bibtex: '@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={10.1016/j.micpro.2011.04.002}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }' chicago: 'Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems 36, no. 2 (2012): 110–26. https://doi.org/10.1016/j.micpro.2011.04.002.' ieee: 'T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” Microprocessors and Microsystems, vol. 36, no. 2, pp. 110–126, 2012, doi: 10.1016/j.micpro.2011.04.002.' mla: 'Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” Microprocessors and Microsystems, vol. 36, no. 2, 2012, pp. 110–26, doi:10.1016/j.micpro.2011.04.002.' short: T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126. date_created: 2018-03-29T15:12:38Z date_updated: 2023-09-26T13:39:30Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1016/j.micpro.2011.04.002 intvolume: ' 36' issue: '2' keyword: - funding-altera language: - iso: eng page: 110-126 publication: Microprocessors and Microsystems publication_identifier: issn: - 0141-9331 quality_controlled: '1' status: public title: 'IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators' type: journal_article user_id: '15278' volume: 36 year: '2012' ... --- _id: '2177' author: - first_name: Mariusz full_name: Grad, Mariusz last_name: Grad - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int Journal of Reconfigurable Computing (IJRC). Published online 2012. doi:10.1155/2012/418315 apa: Grad, M., & Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. Int. Journal of Reconfigurable Computing (IJRC). https://doi.org/10.1155/2012/418315 bibtex: '@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={10.1155/2012/418315}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }' chicago: Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), 2012. https://doi.org/10.1155/2012/418315. ieee: 'M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” Int. Journal of Reconfigurable Computing (IJRC), 2012, doi: 10.1155/2012/418315.' mla: Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” Int. Journal of Reconfigurable Computing (IJRC), Hindawi Publishing Corp., 2012, doi:10.1155/2012/418315. short: M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012). date_created: 2018-04-03T09:13:22Z date_updated: 2023-09-26T13:39:48Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2012/418315 language: - iso: eng publication: Int. Journal of Reconfigurable Computing (IJRC) publisher: Hindawi Publishing Corp. quality_controlled: '1' status: public title: On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors type: journal_article user_id: '15278' year: '2012' ... --- _id: '1971' abstract: - lang: eng text: 'System virtualization has become the enabling technology to manage the increasing number of different applications inside data centers. The abstraction from the underlying hardware and the provision of multiple virtual machines (VM) on a single physical server have led to a consolidation and more efficient usage of physical servers. The abstraction from the hardware also eases the provision of applications on different data centers, as applied in several cloud computing environments. In this case, the application need not adapt to the environment of the cloud computing provider, but can travel around with its own VM image, including its own operating system and libraries. System virtualization and cloud computing could also be very attractive in the context of high‐performance computing (HPC). Today, HPC centers have to cope with both, the management of the infrastructure and also the applications. Virtualization technology would enable these centers to focus on the infrastructure, while the users, collaborating inside their virtual organizations (VOs), would be able to provide the software. Nevertheless, there seems to be a contradiction between HPC and cloud computing, as there are very few successful approaches to virtualize HPC centers. This work discusses the underlying reasons, including the management and performance, and presents solutions to overcome the contradiction, including a set of new libraries. The viability of the presented approach is shown based on evaluating a selected parallel, scientific application in a virtualized HPC environment. ' author: - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Jürgen full_name: Kaiser, Jürgen last_name: Kaiser - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Matthias full_name: Keller, Matthias last_name: Keller - first_name: Christoph full_name: Kleineweber, Christoph last_name: Kleineweber - first_name: Christoph full_name: Konersmann, Christoph last_name: Konersmann - first_name: Oliver full_name: Niehörster, Oliver last_name: Niehörster - first_name: Thorsten full_name: Schäfer, Thorsten last_name: Schäfer - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon - first_name: Maximilan full_name: Wilhelm, Maximilan last_name: Wilhelm citation: ama: 'Birkenheuer G, Brinkmann A, Kaiser J, et al. Virtualized HPC: a contradiction in terms? Software: Practice and Experience. 2011. doi:10.1002/spe.1055' apa: 'Birkenheuer, G., Brinkmann, A., Kaiser, J., Keller, A., Keller, M., Kleineweber, C., … Wilhelm, M. (2011). Virtualized HPC: a contradiction in terms? Software: Practice and Experience. https://doi.org/10.1002/spe.1055' bibtex: '@article{Birkenheuer_Brinkmann_Kaiser_Keller_Keller_Kleineweber_Konersmann_Niehörster_Schäfer_Simon_et al._2011, title={Virtualized HPC: a contradiction in terms?}, DOI={10.1002/spe.1055}, journal={Software: Practice and Experience}, publisher={John Wiley & Sons}, author={Birkenheuer, Georg and Brinkmann, André and Kaiser, Jürgen and Keller, Axel and Keller, Matthias and Kleineweber, Christoph and Konersmann, Christoph and Niehörster, Oliver and Schäfer, Thorsten and Simon, Jens and et al.}, year={2011} }' chicago: 'Birkenheuer, Georg, André Brinkmann, Jürgen Kaiser, Axel Keller, Matthias Keller, Christoph Kleineweber, Christoph Konersmann, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, 2011. https://doi.org/10.1002/spe.1055.' ieee: 'G. Birkenheuer et al., “Virtualized HPC: a contradiction in terms?,” Software: Practice and Experience, 2011.' mla: 'Birkenheuer, Georg, et al. “Virtualized HPC: A Contradiction in Terms?” Software: Practice and Experience, John Wiley & Sons, 2011, doi:10.1002/spe.1055.' short: 'G. Birkenheuer, A. Brinkmann, J. Kaiser, A. Keller, M. Keller, C. Kleineweber, C. Konersmann, O. Niehörster, T. Schäfer, J. Simon, M. Wilhelm, Software: Practice and Experience (2011).' date_created: 2018-03-29T11:22:26Z date_updated: 2022-01-06T06:54:10Z department: - _id: '27' doi: 10.1002/spe.1055 language: - iso: eng publication: 'Software: Practice and Experience' publication_status: published publisher: John Wiley & Sons status: public title: 'Virtualized HPC: a contradiction in terms?' type: journal_article user_id: '15274' year: '2011' ... --- _id: '2192' author: - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Mikael full_name: Högqvist, Mikael last_name: Högqvist - first_name: Alexander full_name: Papaspyrou, Alexander last_name: Papaspyrou - first_name: Bernhard full_name: Schott, Bernhard last_name: Schott - first_name: Dietmar full_name: Sommerfeld, Dietmar last_name: Sommerfeld - first_name: Wolfgang full_name: Ziegler, Wolfgang last_name: Ziegler citation: ama: Birkenheuer G, Brinkmann A, Högqvist M, et al. Infrastructure Federation Through Virtualized Delegation of Resources and Services. Journal of Grid Computing. 2011;9(3):355-377. doi:10.1007/s10723-011-9192-1 apa: Birkenheuer, G., Brinkmann, A., Högqvist, M., Papaspyrou, A., Schott, B., Sommerfeld, D., & Ziegler, W. (2011). Infrastructure Federation Through Virtualized Delegation of Resources and Services. Journal of Grid Computing, 9(3), 355–377. https://doi.org/10.1007/s10723-011-9192-1 bibtex: '@article{Birkenheuer_Brinkmann_Högqvist_Papaspyrou_Schott_Sommerfeld_Ziegler_2011, title={Infrastructure Federation Through Virtualized Delegation of Resources and Services}, volume={9}, DOI={10.1007/s10723-011-9192-1}, number={3}, journal={Journal of Grid Computing}, publisher={Springer}, author={Birkenheuer, Georg and Brinkmann, André and Högqvist, Mikael and Papaspyrou, Alexander and Schott, Bernhard and Sommerfeld, Dietmar and Ziegler, Wolfgang}, year={2011}, pages={355–377} }' chicago: 'Birkenheuer, Georg, André Brinkmann, Mikael Högqvist, Alexander Papaspyrou, Bernhard Schott, Dietmar Sommerfeld, and Wolfgang Ziegler. “Infrastructure Federation Through Virtualized Delegation of Resources and Services.” Journal of Grid Computing 9, no. 3 (2011): 355–77. https://doi.org/10.1007/s10723-011-9192-1.' ieee: G. Birkenheuer et al., “Infrastructure Federation Through Virtualized Delegation of Resources and Services,” Journal of Grid Computing, vol. 9, no. 3, pp. 355–377, 2011. mla: Birkenheuer, Georg, et al. “Infrastructure Federation Through Virtualized Delegation of Resources and Services.” Journal of Grid Computing, vol. 9, no. 3, Springer, 2011, pp. 355–77, doi:10.1007/s10723-011-9192-1. short: G. Birkenheuer, A. Brinkmann, M. Högqvist, A. Papaspyrou, B. Schott, D. Sommerfeld, W. Ziegler, Journal of Grid Computing 9 (2011) 355–377. date_created: 2018-04-03T14:36:06Z date_updated: 2022-01-06T06:55:19Z department: - _id: '27' doi: 10.1007/s10723-011-9192-1 intvolume: ' 9' issue: '3' page: 355-377 publication: Journal of Grid Computing publisher: Springer status: public title: Infrastructure Federation Through Virtualized Delegation of Resources and Services type: journal_article user_id: '24135' volume: 9 year: '2011' ... --- _id: '2201' author: - first_name: Tobias full_name: Schumacher, Tobias last_name: Schumacher - first_name: Tim full_name: Süß, Tim last_name: Süß - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int Journal of Recon- figurable Computing (IJRC). Published online 2011. doi:10.1155/2011/760954' apa: 'Schumacher, T., Süß, T., Plessl, C., & Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. Int. Journal of Recon- Figurable Computing (IJRC). https://doi.org/10.1155/2011/760954' bibtex: '@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={10.1155/2011/760954}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }' chicago: 'Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), 2011. https://doi.org/10.1155/2011/760954.' ieee: 'T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” Int. Journal of Recon- figurable Computing (IJRC), 2011, doi: 10.1155/2011/760954.' mla: 'Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” Int. Journal of Recon- Figurable Computing (IJRC), Hindawi Publishing Corp., 2011, doi:10.1155/2011/760954.' short: T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011). date_created: 2018-04-03T15:09:49Z date_updated: 2023-09-26T13:45:46Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2011/760954 keyword: - funding-altera language: - iso: eng publication: Int. Journal of Recon- figurable Computing (IJRC) publisher: Hindawi Publishing Corp. quality_controlled: '1' status: public title: 'FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study' type: journal_article user_id: '15278' year: '2011' ... --- _id: '2235' author: - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Dominic full_name: Battré, Dominic last_name: Battré - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: Odej full_name: Kao, Odej last_name: Kao - first_name: Kerstin full_name: Voß, Kerstin last_name: Voß citation: ama: Brinkmann A, Battré D, Birkenheuer G, Kao O, Voß K. Risikomanagement für verteilte Umgebungen. ForschungsForum Paderborn. 2010;13(13). apa: Brinkmann, A., Battré, D., Birkenheuer, G., Kao, O., & Voß, K. (2010). Risikomanagement für verteilte Umgebungen. ForschungsForum Paderborn, 13(13). bibtex: '@article{Brinkmann_Battré_Birkenheuer_Kao_Voß_2010, title={Risikomanagement für verteilte Umgebungen}, volume={13}, number={13}, journal={ForschungsForum Paderborn}, publisher={Universität Paderborn}, author={Brinkmann, André and Battré, Dominic and Birkenheuer, Georg and Kao, Odej and Voß, Kerstin}, year={2010} }' chicago: Brinkmann, André, Dominic Battré, Georg Birkenheuer, Odej Kao, and Kerstin Voß. “Risikomanagement Für Verteilte Umgebungen.” ForschungsForum Paderborn 13, no. 13 (2010). ieee: A. Brinkmann, D. Battré, G. Birkenheuer, O. Kao, and K. Voß, “Risikomanagement für verteilte Umgebungen,” ForschungsForum Paderborn, vol. 13, no. 13, 2010. mla: Brinkmann, André, et al. “Risikomanagement Für Verteilte Umgebungen.” ForschungsForum Paderborn, vol. 13, no. 13, Universität Paderborn, 2010. short: A. Brinkmann, D. Battré, G. Birkenheuer, O. Kao, K. Voß, ForschungsForum Paderborn 13 (2010). date_created: 2018-04-05T16:53:36Z date_updated: 2022-01-06T06:55:31Z department: - _id: '27' intvolume: ' 13' issue: '13' publication: ForschungsForum Paderborn publisher: Universität Paderborn status: public title: Risikomanagement für verteilte Umgebungen type: journal_article user_id: '24135' volume: 13 year: '2010' ... --- _id: '2354' author: - first_name: André full_name: Brinkmann, André last_name: Brinkmann - first_name: Dominic full_name: Eschweiler, Dominic last_name: Eschweiler citation: ama: Brinkmann A, Eschweiler D. A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel. Journal of Supercomputing. 2009:35:1-35:10. doi:10.1145/1654059.1654095 apa: Brinkmann, A., & Eschweiler, D. (2009). A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel. Journal of Supercomputing, 35:1-35:10. https://doi.org/10.1145/1654059.1654095 bibtex: '@article{Brinkmann_Eschweiler_2009, title={A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel}, DOI={10.1145/1654059.1654095}, journal={Journal of Supercomputing}, publisher={ACM}, author={Brinkmann, André and Eschweiler, Dominic}, year={2009}, pages={35:1-35:10} }' chicago: Brinkmann, André, and Dominic Eschweiler. “A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel.” Journal of Supercomputing, 2009, 35:1-35:10. https://doi.org/10.1145/1654059.1654095. ieee: A. Brinkmann and D. Eschweiler, “A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel,” Journal of Supercomputing, pp. 35:1-35:10, 2009. mla: Brinkmann, André, and Dominic Eschweiler. “A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel.” Journal of Supercomputing, ACM, 2009, pp. 35:1-35:10, doi:10.1145/1654059.1654095. short: A. Brinkmann, D. Eschweiler, Journal of Supercomputing (2009) 35:1-35:10. date_created: 2018-04-16T15:11:07Z date_updated: 2022-01-06T06:55:56Z department: - _id: '27' doi: 10.1145/1654059.1654095 page: 35:1-35:10 publication: Journal of Supercomputing publisher: ACM status: public title: A Microdriver Architecture for Error Correcting Codes inside the Linux Kernel type: journal_article user_id: '24135' year: '2009' ... --- _id: '2405' author: - first_name: Sven full_name: Groppe, Sven last_name: Groppe - first_name: Stefan full_name: Böttcher, Stefan last_name: Böttcher - first_name: Georg full_name: Birkenheuer, Georg last_name: Birkenheuer - first_name: André full_name: Höing, André last_name: Höing citation: ama: Groppe S, Böttcher S, Birkenheuer G, Höing A. Reformulating XPath queries and XSLT queries on XSLT views. Data & Knowledge Engineering. 2006;57(1):64-110. doi:10.1016/j.datak.2005.04.002 apa: Groppe, S., Böttcher, S., Birkenheuer, G., & Höing, A. (2006). Reformulating XPath queries and XSLT queries on XSLT views. Data & Knowledge Engineering, 57(1), 64–110. https://doi.org/10.1016/j.datak.2005.04.002 bibtex: '@article{Groppe_Böttcher_Birkenheuer_Höing_2006, title={Reformulating XPath queries and XSLT queries on XSLT views}, volume={57}, DOI={10.1016/j.datak.2005.04.002}, number={1}, journal={Data & Knowledge Engineering}, publisher={Elsevier}, author={Groppe, Sven and Böttcher, Stefan and Birkenheuer, Georg and Höing, André}, year={2006}, pages={64–110} }' chicago: 'Groppe, Sven, Stefan Böttcher, Georg Birkenheuer, and André Höing. “Reformulating XPath Queries and XSLT Queries on XSLT Views.” Data & Knowledge Engineering 57, no. 1 (2006): 64–110. https://doi.org/10.1016/j.datak.2005.04.002.' ieee: S. Groppe, S. Böttcher, G. Birkenheuer, and A. Höing, “Reformulating XPath queries and XSLT queries on XSLT views,” Data & Knowledge Engineering, vol. 57, no. 1, pp. 64–110, 2006. mla: Groppe, Sven, et al. “Reformulating XPath Queries and XSLT Queries on XSLT Views.” Data & Knowledge Engineering, vol. 57, no. 1, Elsevier, 2006, pp. 64–110, doi:10.1016/j.datak.2005.04.002. short: S. Groppe, S. Böttcher, G. Birkenheuer, A. Höing, Data & Knowledge Engineering 57 (2006) 64–110. date_created: 2018-04-17T13:47:44Z date_updated: 2022-01-06T06:56:06Z department: - _id: '27' - _id: '69' doi: 10.1016/j.datak.2005.04.002 intvolume: ' 57' issue: '1' page: 64-110 publication: Data & Knowledge Engineering publisher: Elsevier status: public title: Reformulating XPath queries and XSLT queries on XSLT views type: journal_article user_id: '24135' volume: 57 year: '2006' ... --- _id: '1999' abstract: - lang: eng text: "Workstation clusters are often not only used for high-throughput computing in time-sharing mode but also for running complex parallel jobs in space-sharing mode. This poses several difficulties to the resource management system, which must be able to reserve computing resources for exclusive use and also to determine an optimal process mapping for a given system topology.\r\nOn the basis of our CCS software, we describe the anatomy of a modern resource management system. Like Codine, Condor, and LSF, CCS provides mechanisms for the user-friendly system access and management of clusters. But unlike them, CCS is targeted at the effective support of space-sharing parallel computers and even metacomputers. Among other features, CCS provides a versatile resource description facility, topology-based process mapping, pluggable schedulers, and hooks to metacomputer management." author: - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Alexander full_name: Reinefeld, Alexander last_name: Reinefeld citation: ama: Keller A, Reinefeld A. Anatomy of a Resource Management System for HPC Clusters. Annual Review of Scalable Computing. 2001;3:1-31. doi:10.1142/9789812810182_0001 apa: Keller, A., & Reinefeld, A. (2001). Anatomy of a Resource Management System for HPC Clusters. Annual Review of Scalable Computing, 3, 1–31. https://doi.org/10.1142/9789812810182_0001 bibtex: '@article{Keller_Reinefeld_2001, title={Anatomy of a Resource Management System for HPC Clusters}, volume={3}, DOI={10.1142/9789812810182_0001}, journal={Annual Review of Scalable Computing}, author={Keller, Axel and Reinefeld, Alexander}, year={2001}, pages={1–31} }' chicago: 'Keller, Axel, and Alexander Reinefeld. “Anatomy of a Resource Management System for HPC Clusters.” Annual Review of Scalable Computing 3 (2001): 1–31. https://doi.org/10.1142/9789812810182_0001.' ieee: A. Keller and A. Reinefeld, “Anatomy of a Resource Management System for HPC Clusters,” Annual Review of Scalable Computing, vol. 3, pp. 1–31, 2001. mla: Keller, Axel, and Alexander Reinefeld. “Anatomy of a Resource Management System for HPC Clusters.” Annual Review of Scalable Computing, vol. 3, 2001, pp. 1–31, doi:10.1142/9789812810182_0001. short: A. Keller, A. Reinefeld, Annual Review of Scalable Computing 3 (2001) 1–31. date_created: 2018-03-29T11:37:53Z date_updated: 2022-01-06T06:54:17Z department: - _id: '27' doi: 10.1142/9789812810182_0001 intvolume: ' 3' language: - iso: eng page: 1-31 publication: Annual Review of Scalable Computing publication_status: published status: public title: Anatomy of a Resource Management System for HPC Clusters type: journal_article user_id: '15274' volume: 3 year: '2001' ... --- _id: '2007' abstract: - lang: eng text: "We present a software system for the management of geographically distributed high‐performance computers. It consists of three components: \r\n\r\n1. The Computing Center Software (CCS) is a vendor‐independent resource management software for local HPC systems. It controls the mapping and scheduling of interactive and batch jobs on massively parallel systems; \r\n\r\n2. The Resource and Service Description (RSD) is used by CCS for specifying and mapping hardware and software components of (meta‐)computing environments. It has a graphical user interface, a textual representation and an object‐oriented API; \r\n\r\n3. The Service Coordination Layer (SCL) co‐ordinates the co‐operative use of resources in autonomous computing sites. It negotiates between the applications' requirements and the available system services. " author: - first_name: Matthias full_name: Brune, Matthias last_name: Brune - first_name: Jörn full_name: Gehring, Jörn last_name: Gehring - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Alexander full_name: Reinefeld, Alexander last_name: Reinefeld citation: ama: Brune M, Gehring J, Keller A, Reinefeld A. Managing Clusters of Geographically Distributed High-Performance Computers. Concurrency, Practice, and Experience. 1999;II(15):887-911. doi:10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J apa: Brune, M., Gehring, J., Keller, A., & Reinefeld, A. (1999). Managing Clusters of Geographically Distributed High-Performance Computers. Concurrency, Practice, and Experience, II(15), 887–911. https://doi.org/10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J bibtex: '@article{Brune_Gehring_Keller_Reinefeld_1999, title={Managing Clusters of Geographically Distributed High-Performance Computers}, volume={II(15)}, DOI={10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J}, journal={Concurrency, Practice, and Experience}, author={Brune, Matthias and Gehring, Jörn and Keller, Axel and Reinefeld, Alexander}, year={1999}, pages={887–911} }' chicago: 'Brune, Matthias, Jörn Gehring, Axel Keller, and Alexander Reinefeld. “Managing Clusters of Geographically Distributed High-Performance Computers.” Concurrency, Practice, and Experience II(15) (1999): 887–911. https://doi.org/10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J.' ieee: M. Brune, J. Gehring, A. Keller, and A. Reinefeld, “Managing Clusters of Geographically Distributed High-Performance Computers,” Concurrency, Practice, and Experience, vol. II(15), pp. 887–911, 1999. mla: Brune, Matthias, et al. “Managing Clusters of Geographically Distributed High-Performance Computers.” Concurrency, Practice, and Experience, vol. II(15), 1999, pp. 887–911, doi:10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J. short: M. Brune, J. Gehring, A. Keller, A. Reinefeld, Concurrency, Practice, and Experience II(15) (1999) 887–911. date_created: 2018-03-29T11:42:17Z date_updated: 2022-01-06T06:54:18Z department: - _id: '27' doi: 10.1002/(SICI)1096-9128(19991225)11:15<887::AID-CPE459>3.0.CO;2-J language: - iso: eng page: 887-911 publication: Concurrency, Practice, and Experience publication_status: published status: public title: Managing Clusters of Geographically Distributed High-Performance Computers type: journal_article user_id: '15274' volume: II(15) year: '1999' ... --- _id: '2012' abstract: - lang: eng text: With a steadily increasing number of services, metacomputing is now gaining importance in science and industry. Virtual organizations, autonomous agents, mobile computing services, and high-performance client–server applications are among the many examples of metacomputing services. For all of them, resource description plays a major role in organizing access, use, and administration of the computing components and software services. We present a generic Resource and Service Description (RSD) for specifying the hardware and software components of (meta-) computing environments. Its graphical interface allows metacomputer users to specify their resource requests. Its textual counterpart gives service providers the necessary flexibility to specify topology and properties of the available system and software resources. Finally, its internal object-oriented representation is used to link different resource management systems and service tools. With these three representations, our generic RSD approach is a key component for building metacomputer environments. author: - first_name: Matthias full_name: Brune, Matthias last_name: Brune - first_name: Jörn full_name: Gehring, Jörn last_name: Gehring - first_name: Axel full_name: Keller, Axel id: '15274' last_name: Keller - first_name: Burkhard full_name: Monien, Burkhard last_name: Monien citation: ama: Brune M, Gehring J, Keller A, Monien B. Specifying Resources and Services in Metacomputing Environments. Parallel Computing. 1998;24:1751-1776. doi:10.1016/S0167-8191(98)00076-3 apa: Brune, M., Gehring, J., Keller, A., & Monien, B. (1998). Specifying Resources and Services in Metacomputing Environments. Parallel Computing, 24, 1751–1776. https://doi.org/10.1016/S0167-8191(98)00076-3 bibtex: '@article{Brune_Gehring_Keller_Monien_1998, title={Specifying Resources and Services in Metacomputing Environments}, volume={24}, DOI={10.1016/S0167-8191(98)00076-3}, journal={Parallel Computing}, publisher={Elsevier}, author={Brune, Matthias and Gehring, Jörn and Keller, Axel and Monien, Burkhard}, year={1998}, pages={1751–1776} }' chicago: 'Brune, Matthias, Jörn Gehring, Axel Keller, and Burkhard Monien. “Specifying Resources and Services in Metacomputing Environments.” Parallel Computing 24 (1998): 1751–76. https://doi.org/10.1016/S0167-8191(98)00076-3.' ieee: M. Brune, J. Gehring, A. Keller, and B. Monien, “Specifying Resources and Services in Metacomputing Environments,” Parallel Computing, vol. 24, pp. 1751–1776, 1998. mla: Brune, Matthias, et al. “Specifying Resources and Services in Metacomputing Environments.” Parallel Computing, vol. 24, Elsevier, 1998, pp. 1751–76, doi:10.1016/S0167-8191(98)00076-3. short: M. Brune, J. Gehring, A. Keller, B. Monien, Parallel Computing 24 (1998) 1751–1776. date_created: 2018-03-29T11:44:00Z date_updated: 2022-01-06T06:54:20Z department: - _id: '27' doi: 10.1016/S0167-8191(98)00076-3 intvolume: ' 24' language: - iso: eng page: 1751-1776 publication: Parallel Computing publication_status: published publisher: Elsevier quality_controlled: '1' status: public title: Specifying Resources and Services in Metacomputing Environments type: journal_article user_id: '15274' volume: 24 year: '1998' ... --- _id: '2437' author: - first_name: Jens full_name: Simon, Jens id: '15273' last_name: Simon - first_name: Jens-Michael full_name: Wierum, Jens-Michael last_name: Wierum citation: ama: Simon J, Wierum J-M. The Latency-of-Data-Access model for Analyzing Parallel Computation. Information Processing Letters - Special Issue on Models of Computation. 1998;66(5):255-261. doi:10.1016/S0020-0190(98)00062-3 apa: Simon, J., & Wierum, J.-M. (1998). The Latency-of-Data-Access model for Analyzing Parallel Computation. Information Processing Letters - Special Issue on Models of Computation, 66(5), 255–261. https://doi.org/10.1016/S0020-0190(98)00062-3 bibtex: '@article{Simon_Wierum_1998, title={The Latency-of-Data-Access model for Analyzing Parallel Computation}, volume={66}, DOI={10.1016/S0020-0190(98)00062-3}, number={5}, journal={Information Processing Letters - Special Issue on Models of Computation}, publisher={Elsevier}, author={Simon, Jens and Wierum, Jens-Michael}, year={1998}, pages={255–261} }' chicago: 'Simon, Jens, and Jens-Michael Wierum. “The Latency-of-Data-Access Model for Analyzing Parallel Computation.” Information Processing Letters - Special Issue on Models of Computation 66, no. 5 (1998): 255–61. https://doi.org/10.1016/S0020-0190(98)00062-3.' ieee: J. Simon and J.-M. Wierum, “The Latency-of-Data-Access model for Analyzing Parallel Computation,” Information Processing Letters - Special Issue on Models of Computation, vol. 66, no. 5, pp. 255–261, 1998. mla: Simon, Jens, and Jens-Michael Wierum. “The Latency-of-Data-Access Model for Analyzing Parallel Computation.” Information Processing Letters - Special Issue on Models of Computation, vol. 66, no. 5, Elsevier, 1998, pp. 255–61, doi:10.1016/S0020-0190(98)00062-3. short: J. Simon, J.-M. Wierum, Information Processing Letters - Special Issue on Models of Computation 66 (1998) 255–261. date_created: 2018-04-17T16:09:51Z date_updated: 2022-01-06T06:56:19Z department: - _id: '27' doi: 10.1016/S0020-0190(98)00062-3 intvolume: ' 66' issue: '5' page: 255-261 publication: Information Processing Letters - Special Issue on Models of Computation publication_identifier: issn: - 0020-0190 publisher: Elsevier status: public title: The Latency-of-Data-Access model for Analyzing Parallel Computation type: journal_article user_id: '24135' volume: 66 year: '1998' ...