Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations - Walder, Herbert; Platzner, Marco (Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices - Steiger, Christoph; Walder, Herbert; Platzner, Marco (Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL))

Online scheduling and placement of real-time tasks to partially reconfigurable devices - Steiger, Christoph; Walder, Herbert; Platzner, Marco; Thiele, Lothar (Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS))

Reconfigurable Hardware in Wearable Computing Nodes - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar (Proc. Int. Symp. on Wearable Computers (ISWC))
Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.
Keywords: wearable computing

Partially Reconfigurable Cores for Xilinx Virtex - Dyer, Matthias; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.
Keywords: partial reconfiguration

Custom Computing Machines for the Set Covering Problem - Plessl, Christian; Platzner, Marco (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch & bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software.

Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform - Walder, Herbert; Platzner, Marco (Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups.
Keywords: minimum covering; accelerator; funding-sundance

Reconfigurable Processors for Handhelds and Wearables: Application Analysis - Enzler, Rolf; Platzner, Marco; Plessl, Christian; Thiele, Lothar; Tröster, Gerhard (Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III)
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.
Keywords: benchmark

An Implementation Framework for Run-time Reconfigurable Systems - Eisenring, Michael H.; Platzner, Marco (Proceedings of the 2nd International Workshop on Engineering of Reconfigurable Hardware/Software Objects (ENREGLE))

Optimization of Run-time Reconfigurable Embedded Systems - Eisenring, Michael; Platzner, Marco (Proceedings of the 10th International Workshop on Field Programmable Logic and Applications (FPL))

Dynamic circuit generation for Boolean satisfiability in an object-oriented design environment - Mencer, Oskar; Platzner, Marco (Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences (HICSS-32))

Communication Synthesis for Reconfigurable Embedded Systems - Eisenring, Michael; Platzner, Marco; Thiele, Lothar (Proceedings of the 9th International Workshop on Field Programmable Logic and Applications (FPL))

Acceleration of satisfiability algorithms by reconfigurable hardware - Platzner, Marco; De Micheli, Giovanni (Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL))

Fast Signature Segmentation on a Multi-DSP Architecture - Platzner, Marco; Peters, Liliane (Proceedings of the SPIE: Conference on Parallel and Distributed Methods for Image Processing)

Specialized Architectures for Optical Flow Computation: A Performance Comparison of ASIC, DSP, and Multi-DSP - Röwekamp, Thomas; Platzner, Marco; Peters, Liliane (Proceedings of the 8th International Conference on Signal Processing Applications & Technology (ICSPAT))

A Multi-DSP System with Dynamically Reconfigurable Processors - Lind, Erich; Platzner, Marco; Rinner, Bernhard (Proceedings of the 7th International Conference on Signal Processing Applications & Technology (ICSPAT))

A Distributed Computer Architecture for Qualitative Simulation based on a Multi-DSP and FPGAs - Platzner, Marco; Rinner, Bernhard; Weiss, Reinhold (Proceedings of the 3rd Euromicro Workshop on Parallel and Distributed Processing)

High-Performance Simulators Based on Multi-TMS320C40 - Brenner, Eugen; Ginthör-Kalcsics, Robert; Hranitzky, Robert; Platzner, Marco; Rinner, Bernhard; Steger, Christian; Weiss, Reinhold (Proceedings of the 5th Annual Texas Instruments TMS320 Educators Conference)

A Special-Purpose Coprocessor for Qualitative Simulation - Friedl, Gerald; Platzner, Marco; Rinner, Bernhard (Proceedings of the EURO-PAR'95 International Conference on Parallel Processing)

Parallel Qualitative Simulation - Platzner, Marco; Rinner, Bernhard; Weiss, Reinhold (Proceedings of the EUROSIM Congress)

Improving Performance of the Qualitative Simulator QSIM - Design and Implementation of a Specialized Computer Architecture - Platzner, Marco; Rinner, Bernhard (Proceedings of the PDCS International Conference on Parallel and Distributed Computing Systems)

High-Performance Qualitative Simulation on a Multi-DSP Architecture - Platzner, Marco; Rinner, Bernhard (Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT))

Design and Implementation of Adaptive Digital Filters on a Multi-TMS320C40 System - Hranitzky, Robert; Platzner, Marco (Proceedings of the 6th International Conference on Signal Processing Applications & Technology (ICSPAT))

Experimental Evaluation of Multi-DSP Architectures in High Performance Applications - Platzner, Marco; Steger, Christian; Weiss, Reinhold (Proceedings of the 7th Mediterranean Electrotechnical Conference)

Performance Measurements on a Multi-DSP Architecture with TMS320C40 - Platzner, Marco; Steger, Christian; Weiss, Reinhold (Proceedings of the 4th International Conference on Signal Processing Applications & Technology (ICSPAT))

Experimental Results to Interprocessor Communication in Distributed Transputer-Systems - Ginthör, Robert; Platzner, Marco; Weiss, Reinhold (Proceedings of the 1st Austrian-Hungarian Workshop on Transputer Applications)