TY - CONF AU - Clausing, Lennart AU - Guetattfi, Zakarya AU - Kaufmann, Paul AU - Lienen, Christian AU - Platzner, Marco ID - 45913 T2 - Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC) TI - On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64 ER - TY - GEN AU - Lienen, Christian AU - Nowosad, Alexander Philipp AU - Platzner, Marco ID - 46229 TI - Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms ER - TY - CONF AU - Ahmed, Qazi Arbab AU - Awais, Muhammad AU - Platzner, Marco ID - 44194 T2 - The 24th International Symposium on Quality Electronic Design (ISQED'23), San Francisco, Califorina USA TI - MAAS: Hiding Trojans in Approximate Circuits ER - TY - GEN AU - Lienen, Christian AU - Middeke, Sorel Horst AU - Platzner, Marco ID - 43048 TI - fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications ER - TY - CONF AU - Ahmed, Qazi Arbab AU - Platzner, Marco ID - 32342 TI - On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs ER - TY - CONF AU - Lienen, Christian AU - Platzner, Marco ID - 34005 T2 - 2022 25th Euromicro Conference on Digital System Design (DSD) TI - Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications ER - TY - CONF AU - Hansmeier, Tim AU - Brede, Mathis AU - Platzner, Marco ID - 33253 T2 - GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion ER - TY - CONF AU - Clausing, Lennart AU - Platzner, Marco ID - 32855 T2 - 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support ER - TY - CONF AU - Lienen, Christian AU - Platzner, Marco ID - 34007 TI - Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS ER - TY - CONF AU - Hansmeier, Tim AU - Platzner, Marco ID - 30971 SN - 0302-9743 T2 - Applications of Evolutionary Computation, EvoApplications 2022, Proceedings TI - Integrating Safety Guarantees into the Learning Classifier System XCS VL - 13224 ER - TY - CONF AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Artmann, Matthias AU - Platzner, Marco ID - 29865 T2 - Design, Automation and Test in Europe (DATE) TI - MUSCAT: MUS-based Circuit Approximation Technique ER - TY - CONF AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Reuter, Lucas David AU - Platzner, Marco ID - 29945 T2 - 2022 59th ACM/IEEE Design Automation Conference (DAC) TI - Search Space Characterization for Approximate Logic Synthesis ER - TY - GEN AU - Lienen, Christian AU - Platzner, Marco ID - 29541 TI - ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications ER - TY - CONF AU - Ghasemzadeh Mohammadi, Hassan AU - Jentzsch, Felix AU - Kuschel, Maurice AU - Arshad, Rahil AU - Rautmare, Sneha AU - Manjunatha, Suraj AU - Platzner, Marco AU - Boschmann, Alexander AU - Schollbach, Dirk ID - 30908 T2 - Machine Learning and Principles and Practice of Knowledge Discovery in Databases TI - FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics ER - TY - CONF AU - Clausing, Lennart ID - 30909 T2 - Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip ER - TY - CONF AB - The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ID - 20681 T2 - 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) TI - Malicious Routing: Circumventing Bitstream-level Verification for FPGAs ER - TY - CONF AU - Ahmed, Qazi Arbab ID - 29138 T2 - 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC) TI - Hardware Trojans in Reconfigurable Computing ER - TY - CONF AU - Hansmeier, Tim ID - 29137 T2 - HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS ER - TY - CONF AU - Hansmeier, Tim AU - Platzner, Marco ID - 21813 SN - 978-1-4503-8351-6 T2 - GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS ER - TY - CONF AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Raeisi Nafchi, Masood AU - Bockhorn, Arne AU - Platzner, Marco ED - Hannig, Frank ED - Derrien, Steven ED - Diniz, Pedro ED - Chillet, Daniel ID - 21953 T2 - Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21) TI - Timing Optimization for Virtual FPGA Configurations ER - TY - GEN AB - Robotics applications process large amounts of data in real-time and require compute platforms that provide high performance and energy-efficiency. FPGAs are well-suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this paper we present ReconROS, a framework that integrates the widely-used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach. AU - Lienen, Christian AU - Platzner, Marco ID - 22764 T2 - arXiv:2107.07208 TI - Design of Distributed Reconfigurable Robotics Systems with ReconROS ER - TY - CONF AB - Approximate computing (AC) has acquired significant maturity in recent years as a promising approach to obtain energy and area-efficient hardware. Automated approximate accelerator synthesis involves a great deal of complexity on the size of design space which exponentially grows with the number of possible approximations. Design space exploration of approximate accelerator synthesis is usually targeted via heuristic-based search methods. The majority of existing frameworks prune a large part of the design space using a greedy-based approach to keep the problem tractable. Therefore, they result in inferior solutions since many potential solutions are neglected in the pruning process without the possibility of backtracking of removed approximate instances. In this paper, we address the aforementioned issue by adopting Monte Carlo Tree Search (MCTS), as an efficient stochastic learning-based search algorithm, in the context of automated synthesis of approximate accelerators. This enables the synthesis frameworks to deeply subsamples the design space of approximate accelerator synthesis toward most promising approximate instances based on the required performance goals, i.e., power consumption, area, or/and delay. We investigated the challenges of providing an efficient open-source framework that benefits analytical and search-based approximation techniques simultaneously to both speed up the synthesis runtime and improve the quality of obtained results. Besides, we studied the utilization of machine learning algorithms to improve the performance of several critical steps, i.e., accelerator quality testing, in the synthesis framework. The proposed framework can help the community to rapidly generate efficient approximate accelerators in a reasonable runtime. AU - Awais, Muhammad AU - Platzner, Marco ID - 22309 KW - Approximate computing KW - Design space exploration KW - Accelerator synthesis T2 - Proceedings of IEEE Computer Society Annual Symposium on VLSI TI - MCTS-Based Synthesis Towards Efficient Approximate Accelerators ER - TY - CONF AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 21610 T2 - Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 TI - LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 20838 SN - 9781728174457 T2 - 2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - MigHEFT: DAG-based Scheduling of Migratable Tasks on Heterogeneous Compute Nodes ER - TY - CONF AU - Guetttatfi, Zakarya AU - Kaufmann, Paul AU - Platzner, Marco ID - 3583 T2 - Proceedings of the International Workshop on Applied Reconfigurable Computing (ARC) TI - Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices ER - TY - CONF AU - Gatica, Carlos Paiz AU - Platzner, Marco ID - 21584 SN - 2522-8579 T2 - Machine Learning for Cyber Physical Systems (ML4CPS 2017) TI - Adaptable Realization of Industrial Analytics Functions on Edge-Devices using Reconfigurable Architectures ER - TY - GEN AB - On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 20748 T2 - Fifth Workshop on Approximate Computing (AxC 2020) TI - Search Space Characterization for AxC Synthesis ER - TY - CONF AU - Lienen, Christian AU - Platzner, Marco AU - Rinner, Bernhard ID - 20750 T2 - Proceedings of the 2020 International Conference on Field-Programmable Technology (FPT) TI - ReconROS: Flexible Hardware Acceleration for ROS2 Applications ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 17063 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Adaption Mechanism for the Error Threshold of XCSF ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 16363 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold ER - TY - CONF AB - Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 16213 T2 - Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 TI - A Hybrid Synthesis Methodology for Approximate Circuits ER - TY - CONF AB - Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. AU - Ahmed, Qazi Arbab AU - Wiersema, Tobias AU - Platzner, Marco ED - Hochberger, Christian ED - Nelson, Brent ED - Koch, Andreas ED - Woods, Roger ED - Diniz, Pedro ID - 9913 SN - 978-3-030-17227-5 T2 - Applied Reconfigurable Computing TI - Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan VL - 11444 ER - TY - CONF AU - Guettatfi, Zakarya AU - Platzner, Marco AU - Kermia, Omar AU - Khouas, Abdelhakim ID - 31067 T2 - 2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) TI - An Approach for Mapping Periodic Real-Time Tasks to Reconfigurable Hardware ER - TY - GEN AB - State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing. AU - Witschen, Linus Matthias AU - Ghasemzadeh Mohammadi, Hassan AU - Artmann, Matthias AU - Platzner, Marco ID - 16853 KW - Approximate computing KW - parameter selection KW - search space exploration KW - verification KW - circuit synthesis T2 - Fourth Workshop on Approximate Computing (AxC 2019) TI - Jump Search: A Fast Technique for the Synthesis of Approximate Circuits ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 15422 T2 - World Congress on Nature and Biologically Inspired Computing (NaBIC) TI - Optimization of Application-specific L1 Cache Translation Functions of the LEON3 Processor ER - TY - CONF AB - State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing. AU - Witschen, Linus Matthias AU - Ghasemzadeh Mohammadi, Hassan AU - Artmann, Matthias AU - Platzner, Marco ID - 10577 KW - Approximate computing KW - design automation KW - parameter selection KW - circuit synthesis SN - 9781450362528 T2 - Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19 TI - Jump Search: A Fast Technique for the Synthesis of Approximate Circuits ER - TY - CONF AU - Lösch, Achim AU - Platzner, Marco ID - 5547 SN - 9781538674796 T2 - 2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - A Highly Accurate Energy Model for Task Execution on Heterogeneous Compute Nodes ER - TY - GEN AB - Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Ghasemzadeh Mohammadi, Hassan AU - Awais, Muhammad AU - Platzner, Marco ID - 3586 KW - Approximate Computing KW - Framework KW - Pareto Front KW - Accuracy T2 - Third Workshop on Approximate Computing (AxC 2018) TI - CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation ER - TY - CONF AB - Profiling applications on a heterogeneous compute node is challenging since the way to retrieve data from the resources and interpret them varies between resource types and manufacturers. This holds especially true for measuring the energy consumption. In this paper we present Ampehre, a novel open source measurement framework that allows developers to gather comparable measurements from heterogeneous compute nodes, e.g., nodes comprising CPU, GPU, and FPGA. We explain the architecture of Ampehre and detail the measurement process on the example of energy measurements on CPU and GPU. To characterize the probing effect, we quantitatively analyze the trade-off between the accuracy of measurements and the CPU load imposed by Ampehre. Based on this analysis, we are able to specify reasonable combinations of sampling periods for the different resource types of a compute node. AU - Lösch, Achim AU - Wiens, Alex AU - Platzner, Marco ID - 3362 SN - 0302-9743 T2 - Proceedings of the International Conference on Architecture of Computing Systems (ARCS) TI - Ampehre: An Open Source Measurement Framework for Heterogeneous Compute Nodes VL - 10793 ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AU - Witschen, Linus Matthias AU - Wiersema, Tobias AU - Platzner, Marco ID - 1165 T2 - 4th Workshop On Approximate Computing (WAPCO 2018) TI - Making the Case for Proof-carrying Approximate Circuits ER - TY - CONF AB - Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints. AU - Awais, Muhammad AU - Ghasemzadeh Mohammadi, Hassan AU - Platzner, Marco ID - 10598 KW - Approximate computing KW - High-level synthesis KW - Accuracy KW - Monte-Carlo tree search KW - Circuit simulation T2 - 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC) TI - An MCTS-based Framework for Synthesis of Approximate Circuits ER - TY - CONF AB - Heterogeneous compute nodes in form of CPUs with attached GPU and FPGA accelerators have strongly gained interested in the last years. Applications differ in their execution characteristics and can therefore benefit from such heterogeneous resources in terms of performance or energy consumption. While performance optimization has been the only goal for a long time, nowadays research is more and more focusing on techniques to minimize energy consumption due to rising electricity costs.This paper presents reMinMin, a novel static list scheduling approach for optimizing the total energy consumption for a set of tasks executed on a heterogeneous compute node. reMinMin bases on a new energy model that differentiates between static and dynamic energy components and covers effects of accelerator tasks on the host CPU. The required energy values are retrieved by measurements on the real computing system. In order to evaluate reMinMin, we compare it with two reference implementations on three task sets with different degrees of heterogeneity. In our experiments, MinMin is consistently better than a scheduler optimizing for dynamic energy only, which requires up to 19.43% more energy, and very close to optimal schedules. AU - Lösch, Achim AU - Platzner, Marco ID - 65 T2 - Proceedings of the 28th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP) TI - reMinMin: A Novel Static Energy-Centric List Scheduling Approach Based on Real Measurements ER - TY - CONF AU - Ghribi, Ines AU - Abdallah, Riadh Ben AU - Khalgui, Mohamed AU - Platzner, Marco ID - 14893 SN - 1865-0929 T2 - Communications in Computer and Information Science TI - I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10760 T2 - KI 2017: Advances in Artificial Intelligence: 40th Annual German Conference on AI TI - Parametrizing Cartesian Genetic Programming: An Empirical Study ER - TY - CONF AU - Kaufmann, Paul AU - Ho, Nam AU - Platzner, Marco ID - 10761 T2 - Adaptive Hardware and Systems (AHS) TI - Evaluation Methodology for Complex Non-deterministic Functions: A Case Study in Metaheuristic Optimization of Caches ER - TY - CONF AU - Kaufmann, Paul AU - Kalkreuth, Roman ID - 10762 T2 - Genetic and Evolutionary Computation (GECCO), Compendium TI - An Empirical Study on the Parametrization of Cartesian Genetic Programming ER - TY - CONF AU - Guettatfi, Zakarya AU - Hübner, Philipp AU - Platzner, Marco AU - Rinner, Bernhard ID - 10780 KW - embedded systems KW - image sensors KW - power aware computing KW - wireless sensor networks KW - Zynq-based VSN node prototype KW - computational self-awareness KW - design approach KW - platform levels KW - power consumption KW - visual sensor networks KW - visual sensor nodes KW - Cameras KW - Hardware KW - Middleware KW - Multicore processing KW - Operating systems KW - Runtime KW - Reconfigurable platforms KW - distributed embedded systems KW - performance-resource trade-off KW - self-awareness KW - visual sensor nodes T2 - 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) TI - Computational self-awareness as design approach for visual sensor nodes ER - TY - CONF AU - Boschmann, Alexander AU - Thombansen, Georg AU - Witschen, Linus Matthias AU - Wiens, Alex AU - Platzner, Marco ID - 10630 T2 - Design, Automation and Test in Europe (DATE) TI - A Zynq-based dynamically reconfigurable high density myoelectric prosthesis controller ER - TY - CONF AU - Ho, Nam AU - Ashraf, Ishraq Ibne AU - Kaufmann, Paul AU - Platzner, Marco ID - 10672 T2 - Proc. Design, Automation and Test in Europe Conf. (DATE) TI - Accurate Private/Shared Classification of Memory Accesses: a Run-time Analysis System for the LEON3 Multi-core Processor ER -