Hardware-Aware AutoML for Exploration of Custom FPGA Accelerators for RadioML - Jentzsch, Felix (2023 33rd International Conference on Field-Programmable Logic and Applications (FPL))

AutonomROS: A ReconROS-based Autonomous Driving Unit - Lienen, Christian; Brede, Mathis; Karger, Daniel; Koch, Kevin; Logan, Dalisha; Mazur, Janet; Nowosad, Alexander Philipp; Schnelle, Alexander; Waizy, Mohness; Platzner, Marco (2023 Seventh IEEE International Conference on Robotic Computing (IRC))

Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms - Lienen, Christian; Nowosad, Alexander Philipp; Platzner, Marco (Proceedings of the 2023 9th International Conference on Robotics and Artificial Intelligence (ICRAI))

fpgaDDS: An Intra-FPGA Data Distribution Service for ROS 2 Robotics Applications - Lienen, Christian; Middeke, Sorel Horst; Platzner, Marco (Proceedings of the 2023 IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS))

On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64 - Clausing, Lennart; Guetattfi, Zakarya; Kaufmann, Paul; Lienen, Christian; Platzner, Marco (Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC))

MAAS: Hiding Trojans in Approximate Circuits - Ahmed, Qazi Arbab; Awais, Muhammad; Platzner, Marco (The 24th International Symposium on Quality Electronic Design (ISQED'23), San Francisco, Califorina USA)

On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs - Ahmed, Qazi Arbab; Platzner, Marco

Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications - Lienen, Christian; Platzner, Marco (2022 25th Euromicro Conference on Digital System Design (DSD))

XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion - Hansmeier, Tim; Brede, Mathis; Platzner, Marco (GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion)

ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support - Clausing, Lennart; Platzner, Marco (2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW))

Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS - Lienen, Christian; Platzner, Marco

Integrating Safety Guarantees into the Learning Classifier System XCS - Hansmeier, Tim; Platzner, Marco (Applications of Evolutionary Computation, EvoApplications 2022, Proceedings)

MUSCAT: MUS-based Circuit Approximation Technique - Witschen, Linus Matthias; Wiersema, Tobias; Artmann, Matthias; Platzner, Marco (Design, Automation and Test in Europe (DATE))

Search Space Characterization for Approximate Logic Synthesis - Witschen, Linus Matthias; Wiersema, Tobias; Reuter, Lucas David; Platzner, Marco (2022 59th ACM/IEEE Design Automation Conference (DAC))

ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications - Lienen, Christian; Platzner, Marco

FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics - Ghasemzadeh Mohammadi, Hassan; Jentzsch, Felix; Kuschel, Maurice; Arshad, Rahil; Rautmare, Sneha; Manjunatha, Suraj; Platzner, Marco; Boschmann, Alexander; Schollbach, Dirk (Machine Learning and Principles and Practice of Knowledge Discovery in Databases)

ReconOS64: High-Performance Embedded Computing for Industrial Analytics on a Reconfigurable System-on-Chip - Clausing, Lennart (Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies)

Malicious Routing: Circumventing Bitstream-level Verification for FPGAs - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (2021 Design, Automation & Test in Europe Conference & Exhibition (DATE))
The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.

Hardware Trojans in Reconfigurable Computing - Ahmed, Qazi Arbab (2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC))

Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS - Hansmeier, Tim (HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies)