[{"citation":{"bibtex":"@book{Hansmeier_2023, title={XCS for Self-awareness in Autonomous Computing Systems}, author={Hansmeier, Tim}, year={2023} }","mla":"Hansmeier, Tim. XCS for Self-Awareness in Autonomous Computing Systems. 2023.","chicago":"Hansmeier, Tim. XCS for Self-Awareness in Autonomous Computing Systems, 2023.","ama":"Hansmeier T. XCS for Self-Awareness in Autonomous Computing Systems.; 2023.","apa":"Hansmeier, T. (2023). XCS for Self-awareness in Autonomous Computing Systems.","ieee":"T. Hansmeier, XCS for Self-awareness in Autonomous Computing Systems. 2023.","short":"T. Hansmeier, XCS for Self-Awareness in Autonomous Computing Systems, 2023."},"year":"2023","type":"dissertation","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"eng"}],"_id":"47837","date_updated":"2023-10-06T12:46:08Z","author":[{"full_name":"Hansmeier, Tim","first_name":"Tim","last_name":"Hansmeier"}],"department":[{"_id":"78"}],"status":"public","date_created":"2023-10-06T12:45:58Z","project":[{"name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","grant_number":"160364472","_id":"1"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)"}],"title":"XCS for Self-awareness in Autonomous Computing Systems","user_id":"15504"},{"doi":"10.17619/UNIPB/1-1649","date_updated":"2023-01-19T06:41:22Z","_id":"34041","citation":{"chicago":"Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based Approximate Logic Synthesis, 2022. https://doi.org/10.17619/UNIPB/1-1649.","ama":"Witschen LM. Frameworks and Methodologies for Search-Based Approximate Logic Synthesis.; 2022. doi:10.17619/UNIPB/1-1649","apa":"Witschen, L. M. (2022). Frameworks and Methodologies for Search-based Approximate Logic Synthesis. https://doi.org/10.17619/UNIPB/1-1649","mla":"Witschen, Linus Matthias. Frameworks and Methodologies for Search-Based Approximate Logic Synthesis. 2022, doi:10.17619/UNIPB/1-1649.","bibtex":"@book{Witschen_2022, title={Frameworks and Methodologies for Search-based Approximate Logic Synthesis}, DOI={10.17619/UNIPB/1-1649}, author={Witschen, Linus Matthias}, year={2022} }","short":"L.M. Witschen, Frameworks and Methodologies for Search-Based Approximate Logic Synthesis, 2022.","ieee":"L. M. Witschen, Frameworks and Methodologies for Search-based Approximate Logic Synthesis. 2022."},"type":"dissertation","year":"2022","supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}],"title":"Frameworks and Methodologies for Search-based Approximate Logic Synthesis","user_id":"15504","date_created":"2022-11-09T06:26:22Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - B: SFB 901 - Project Area B","_id":"3"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"}],"status":"public","department":[{"_id":"78"}],"author":[{"id":"49051","last_name":"Witschen","full_name":"Witschen, Linus Matthias","first_name":"Linus Matthias"}]},{"_id":"29769","year":"2022","citation":{"apa":"Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271","ama":"Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271","chicago":"Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.","mla":"Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.","bibtex":"@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable Computing}, DOI={10.17619/UNIPB/1-1271}, publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab}, year={2022} }","short":"Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University, Paderborn, Germany, Paderborn, 2022.","ieee":"Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn University, Paderborn, Germany, 2022."},"type":"dissertation","supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"main_file_link":[{"open_access":"1","url":"\turn:nbn:de:hbz:466:2-40303"}],"ddc":["004"],"user_id":"477","abstract":[{"lang":"eng","text":"Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen den Trojaner ``Heimtückische LUT'' stellen wir die allererste erfolgreiche Gegenmaßnahme vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden."},{"text":"The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable systems, the defenders perspective which corresponds to the bitstream-level Trojan detection technique, and the attackers perspective which corresponds to a novel FPGA Trojan attack. From the defender's perspective, we introduce a first-ever successful pre-configuration countermeasure against the ``Malicious LUT''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers perspective, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by bitstream-level verification techniques.","lang":"eng"}],"date_created":"2022-02-07T14:02:36Z","status":"public","has_accepted_license":"1","keyword":["FPGA Security","Hardware Trojans","Bitstream-level Trojans","Bitstream Verification"],"publisher":" Paderborn University, Paderborn, Germany","author":[{"id":"72764","last_name":"Ahmed","orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","first_name":"Qazi Arbab"}],"doi":"10.17619/UNIPB/1-1271","oa":"1","date_updated":"2022-11-30T13:39:01Z","language":[{"iso":"eng"}],"title":"Hardware Trojans in Reconfigurable Computing","place":"Paderborn","publication_status":"published","project":[{"name":"SFB 901: SFB 901","_id":"1"},{"name":"SFB 901 - C: SFB 901 - Project Area C","_id":"4"},{"name":"SFB 901 - C2: SFB 901 - Subproject C2","_id":"14"}],"department":[{"_id":"78"}]},{"oa":"1","date_updated":"2022-01-06T06:57:26Z","language":[{"iso":"eng"}],"title":"Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware","place":"Paderborn","project":[{"_id":"1","name":"SFB 901"},{"_id":"3","name":"SFB 901 - Project Area B"},{"name":"SFB 901 - Subproject B4","_id":"12"}],"publication_status":"published","department":[{"_id":"78"}],"_id":"26746","supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"year":"2021","citation":{"ama":"Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University; 2021.","apa":"Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University.","chicago":"Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.","mla":"Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University, 2021.","bibtex":"@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2021} }","short":"T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.","ieee":"T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021."},"type":"dissertation","page":"293","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800"}],"user_id":"3118","ddc":["006"],"abstract":[{"lang":"eng","text":"Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques."},{"text":"Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen, Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale. Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt werden können.","lang":"ger"}],"status":"public","date_created":"2021-10-25T06:35:41Z","publisher":"Paderborn University","author":[{"first_name":"Tobias","full_name":"Wiersema, Tobias","last_name":"Wiersema","id":"3118"}],"keyword":["Proof-Carrying Hardware","Formal Verification","Sequential Circuits","Non-Functional Properties","Functional Properties"]},{"abstract":[{"lang":"eng","text":"Traditional cache design uses a consolidated block of memory address bits to index a cache set, equivalent to the use of modulo functions. While this module-based mapping scheme is widely used in contemporary cache structures due to the simplicity of its hardware design and its good performance for sequences of consecutive addresses, its use may not be satisfactory for a variety of application domains having different characteristics.This thesis presents a new type of cache mapping scheme, motivated by programmable capabilities combined with Nature-inspired optimization of reconfigurable hardware. This research has focussed on an FPGA-based evolvable cache structure of the first level cache in a multi-core processor architecture, able to dynamically change cache indexing. To solve the challenge of reconfigurable cache mappings, a programmable Boolean circuit based on a combination of Look-up Table (LUT) memory elements is proposed. Focusing on optimization aspects at the system level, a Performance Measurement Infrastructure is introduced that is able to monitor the underlying microarchitectural metrics, and an adaptive evaluation strategy is presented that leverages on Evolutionary Algorithms, that is not only capable of evolving application-specific address-to-cache-index mappings for level one split caches but also of reducing optimization times. Putting this all together and prototyping in an FPGA for a LEON3/Linux-based multi-core processor, the creation of a system architecture reduces cache misses and improves performance over the use of conventional caches."},{"lang":"ger","text":"Traditionelle Cachedesigns verwenden konsolidierte Blöcke von Speicheradressbits um einen Cachesatz zu indizieren, vergleichbar mit der Anwendung einer Modulofunktion. Obwohl dieses modulobasierte Abbildungsschema in heutigen Cachestrukturen weit verbreitet ist, vor allem wegen seiner einfachen Anforderungen an das Hardwaredesign und seiner Effizienz für die Indizierung eufeinanderfolgender Speicheradressen, kann seine Verwendung für eine Vielzahl von Anwendungsdomänen mit unterschiedlichen Charakteristiken zu suboptimalen Ergebnissen führen. Diese Dissertation präsentiert einen neuen Typ von Cacheabbildungsschema, motiviert durch die Kombination programmierbarer Ressourcen mit der naturinspirierten Optimierung rekonfigurierbarer Hardware. Im Fokus dieser Forschung steht eine FPGA-basierte Cachestruktur für den first level Cache einer Mehrkernprozessorarchitektur, welche die Cacheindizierung dynamisch ändern kann. Um die Herausforderung rekonfigurierbarer Cacheabbildungen zu lösen, wird eine reprogrammierbare Boolesche Schaltung eingeführt, die auf Look-up Table (LUT) Speicherelementen basiert. Weiterhin wird eine Infrastruktur zur Effizienzmessung eingeführt, welche die zugrundeliege Mikroarchitektur überwachen kann, sowie eine adaptive Evaluationsstrategie präsentiert, die evolutionäre Algorithmen wirksam einsetzt, und die nicht nur anwendungsspezifische Abbildungen von Speicheradressen zu Cacheindizes für level one Caches evolvieren sondern dabei auch die Optimierungszeiten reduzieren kann. All diese Aspekte zusammen in einer prototypischen Implementierung auf einem FPGA für einen LEON3/Linux-basierten Mehrkernprozessor zeigen, dass evolvierbare Cacheabbildungsfunktionen Cache Misses reduzieren, sowie die Effizienz im Vergleich zu konventionellen Caches erhöhen können."}],"title":"FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization","user_id":"477","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"}],"publisher":"Universität Paderborn","department":[{"_id":"78"}],"publication_status":"published","status":"public","project":[{"name":"SFB 901 - Subproject B4","_id":"12"},{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"}],"date_created":"2018-07-27T06:41:13Z","date_updated":"2022-01-06T06:59:31Z","_id":"3720","doi":"10.17619/UNIPB/1-376","year":"2018","type":"dissertation","citation":{"chicago":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018. https://doi.org/10.17619/UNIPB/1-376.","apa":"Ho, N. (2018). FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn. https://doi.org/10.17619/UNIPB/1-376","ama":"Ho N. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn; 2018. doi:10.17619/UNIPB/1-376","mla":"Ho, Nam. FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018, doi:10.17619/UNIPB/1-376.","bibtex":"@book{Ho_2018, title={FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization}, DOI={10.17619/UNIPB/1-376}, publisher={Universität Paderborn}, author={Ho, Nam}, year={2018} }","short":"N. Ho, FPGA-Based Reconfigurable Cache Mapping Schemes: Design and Optimization, Universität Paderborn, 2018.","ieee":"N. Ho, FPGA-based Reconfigurable Cache Mapping Schemes: Design and Optimization. Universität Paderborn, 2018."},"page":"139","supervisor":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"language":[{"iso":"eng"}]},{"author":[{"full_name":"Beisel, Tobias","first_name":"Tobias","last_name":"Beisel"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"},{"_id":"27"},{"_id":"518"}],"publication_identifier":{"isbn":["978-3-8325-4155-2"]},"status":"public","date_created":"2019-07-10T09:36:58Z","project":[{"grant_number":"01|H11004","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","_id":"30"}],"place":"Berlin","abstract":[{"text":"The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.","lang":"eng"}],"title":"Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing","user_id":"3118","type":"dissertation","citation":{"short":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015.","ieee":"T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","chicago":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.","ama":"Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.","apa":"Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.","mla":"Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015.","bibtex":"@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }"},"year":"2015","page":"183","supervisor":[{"last_name":"Plessl","id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian"}],"language":[{"iso":"eng"}],"_id":"10624","date_updated":"2022-01-06T06:50:48Z"},{"language":[{"iso":"eng"}],"supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"citation":{"short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014.","ieee":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","chicago":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","ama":"Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.","apa":"Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","mla":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Logos Verlag Berlin GmbH, 2014."},"type":"dissertation","year":"2014","page":"133","date_updated":"2022-01-06T06:50:50Z","_id":"10733","author":[{"last_name":"Schäfers","full_name":"Schäfers, Lars","first_name":"Lars"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"}],"status":"public","date_created":"2019-07-10T11:58:06Z","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"publication_status":"published","place":"Berlin","abstract":[{"text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.","lang":"eng"}],"user_id":"3118","title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:01:34Z","department":[{"_id":"78"}],"publication_identifier":{"isbn":["978-3-8325-3425-7"]},"publication_status":"published","project":[{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901","_id":"1"},{"name":"SFB 901 - Project Area C","_id":"4"}],"place":"Berlin","title":"Performance and thermal management on self-adaptive hybrid multi-cores","related_material":{"link":[{"url":"https://www.logos-verlag.de/cgi-bin/engbuchmid?isbn=3425&lng=deu&id=","relation":"confirmation"}]},"page":"220","type":"dissertation","year":"2013","citation":{"ieee":"M. Happe, Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH, 2013.","short":"M. Happe, Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores, Logos Verlag Berlin GmbH, Berlin, 2013.","mla":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Happe_2013, place={Berlin}, title={Performance and thermal management on self-adaptive hybrid multi-cores}, publisher={Logos Verlag Berlin GmbH}, author={Happe, Markus}, year={2013} }","ama":"Happe M. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Happe, M. (2013). Performance and thermal management on self-adaptive hybrid multi-cores. Berlin: Logos Verlag Berlin GmbH.","chicago":"Happe, Markus. Performance and Thermal Management on Self-Adaptive Hybrid Multi-Cores. Berlin: Logos Verlag Berlin GmbH, 2013."},"supervisor":[{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"_id":"501","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"}],"publisher":"Logos Verlag Berlin GmbH","date_created":"2017-10-17T12:42:30Z","status":"public","abstract":[{"lang":"eng","text":"Handling run-time dynamics on embedded system-on-chip architectures has become more challenging over the years. On the one hand, the impact of workload and physical dynamics on the system behavior has dramatically increased. On the other hand, embedded architectures have become more complex as they have evolved from single-processor systems over multi-processor systems to hybrid multi-core platforms.Static design-time techniques no longer provide suitable solutions to deal with the run-time dynamics of today's embedded systems. Therefore, system designers have to apply run-time solutions, which have hardly been investigated for hybrid multi-core platforms.In this thesis, we present fundamental work in the new area of run-time management on hybrid multi-core platforms. We propose a novel architecture, a self-adaptive hybrid multi-core system, that combines heterogeneous processors, reconfigurable hardware cores, and monitoring cores on a single chip. Using self-adaptation on thread-level, our hybrid multi-core systems can effectively perform performance and thermal management autonomously at run-time. "}],"user_id":"477"},{"department":[{"_id":"78"}],"publisher":"Logos Verlag Berlin GmbH","author":[{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"}],"publication_identifier":{"isbn":["978-3-8325-3530-8"]},"publication_status":"published","date_created":"2019-07-11T11:51:51Z","status":"public","abstract":[{"text":"Reconfigurable circuit devices have opened up a fundamentally new way of creating adaptable systems. Combined with artificial evolution, reconfigurable circuits allow an elegant adaptation approach to compensating for changes in the distribution of input data, computational resource errors, and variations in resource requirements. Referred to as ``Evolvable Hardware'' (EHW), this paradigm has yielded astonishing results for traditional engineering challenges and has discovered intriguing design principles, which have not yet been seen in conventional engineering.\r\n\r\nIn this thesis, we present new and fundamental work on Evolvable Hardware motivated by the insight that Evolvable Hardware needs to compensate for events with different change rates. To solve the challenge of different adaptation speeds, we propose a unified adaptation approach based on multi-objective evolution, evolving and propagating candidate solutions that are diverse in objectives that may experience radical changes.\r\n\r\nFocusing on algorithmic aspects, we enable Cartesian Genetic Programming (CGP) model, which we are using to encode Boolean circuits, for multi-objective optimization by introducing a meaningful recombination operator. We improve the scalability of CGP by objectives scaling, periodization of local- and global-search algorithms, and the automatic acquisition and reuse of subfunctions using age- and cone-based techniques. We validate our methods on the applications of adaptation of hardware classifiers to resource changes, recognition of muscular signals for prosthesis control and optimization of processor caches.","lang":"eng"}],"place":"Berlin","title":"Adapting Hardware Systems by Means of Multi-Objective Evolution","user_id":"3118","page":"249","year":"2013","type":"dissertation","citation":{"short":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution, Logos Verlag Berlin GmbH, Berlin, 2013.","ieee":"P. Kaufmann, Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","ama":"Kaufmann P. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH; 2013.","apa":"Kaufmann, P. (2013). Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH.","chicago":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Berlin: Logos Verlag Berlin GmbH, 2013.","mla":"Kaufmann, Paul. Adapting Hardware Systems by Means of Multi-Objective Evolution. Logos Verlag Berlin GmbH, 2013.","bibtex":"@book{Kaufmann_2013, place={Berlin}, title={Adapting Hardware Systems by Means of Multi-Objective Evolution}, publisher={Logos Verlag Berlin GmbH}, author={Kaufmann, Paul}, year={2013} }"},"language":[{"iso":"eng"}],"supervisor":[{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"_id":"11619","date_updated":"2022-01-06T06:51:04Z"},{"language":[{"iso":"eng"}],"date_updated":"2022-01-06T07:02:44Z","oa":"1","department":[{"_id":"78"}],"publication_status":"published","project":[{"name":"SFB 901 - Subprojekt B4","_id":"12"},{"name":"SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - Project Area B"}],"title":"Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.de/urn:nbn:de:hbz:466:2-10423"}],"page":"114","citation":{"mla":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","bibtex":"@book{Drzevitzky_2012, title={Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security}, publisher={Universität Paderborn}, author={Drzevitzky, Stephanie}, year={2012} }","chicago":"Drzevitzky, Stephanie. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","apa":"Drzevitzky, S. (2012). Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn.","ama":"Drzevitzky S. Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn; 2012.","ieee":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security. Universität Paderborn, 2012.","short":"S. Drzevitzky, Proof-Carrying Hardware: A Novel Approach to Reconfigurable Hardware Security, Universität Paderborn, 2012."},"year":"2012","type":"dissertation","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"_id":"586","file_date_updated":"2018-03-15T08:38:19Z","publisher":"Universität Paderborn","author":[{"first_name":"Stephanie","full_name":"Drzevitzky, Stephanie","last_name":"Drzevitzky"}],"file":[{"file_name":"586-Drzevitzky-PhD_01.pdf","date_created":"2018-03-15T08:38:19Z","access_level":"closed","creator":"florida","file_id":"1261","file_size":1438436,"success":1,"relation":"main_file","content_type":"application/pdf","date_updated":"2018-03-15T08:38:19Z"}],"date_created":"2017-10-17T12:42:46Z","status":"public","has_accepted_license":"1","abstract":[{"text":"FPGAs, systems on chip and embedded systems are nowadays irreplaceable. They combine the computational power of application specific hardware with software-like flexibility. At runtime, they can adjust their functionality by downloading new hardware modules and integrating their functionality. Due to their growing capabilities, the demands made to reconfigurable hardware grow. Their deployment in increasingly security critical scenarios requires new ways of enforcing security since a failure in security has severe consequences. Aside from financial losses, a loss of human life and risks to national security are possible. With this work I present the novel and groundbreaking concept of proof-carrying hardware. It is a method for the verification of properties of hardware modules to guarantee security for a target platform at runtime. The producer of a hardware module delivers based on the consumer's safety policy a safety proof in combination with the reconfiguration bitstream. The extensive computation of a proof is a contrast to the comparatively undemanding checking of the proof. I present a prototype based on open-source tools and an abstract FPGA architecture and bitstream format. The proof of the usability of proof-carrying hardware provides the evaluation of the prototype with the exemplary application of securing combinational and bounded sequential equivalence of reference monitor modules for memory safety.","lang":"eng"},{"text":"FPGAs, System on Chips und eingebettete Systeme sind heutzutage kaum mehr wegzudenken. Sie kombinieren die Rechenleistung von spezialisierter Hardware mit einer Software-ähnlichen Flexibilität. Zur Laufzeit können sie ihre Funktionalität anpassen, indem sie online neue Hardware Module beziehen und deren Funktionalität integrieren. Mit der Leistung wachsen auch die Anforderungen an rekonfigurierbare Hardware. Ihr Einsatz in immer sicherheitskritischeren Szenarien erfordert neue Wege um Sicherheit zu gewährleisten, da ein Versagen der Sicherheit gravierende Folgen mit sich bringt. Neben finanziellen Verlusten sind auch der Verlust von Menschenleben oder Einbußen in der nationalen Sicherheit denkbar. In dieser Arbeit stelle ich das neue und wegweisende Konzept der beweistragenden Hardware vor. Es ist eine Methode zur Verifizierung von Eigenschaften von Hardware Modulen um die Sicherheit der Zielplatformen zur Laufzeit zu garantieren. Der Produzent eines Hardware Moduls liefert, basierend auf den Sicherheitsbestimmungen des Konsumenten, einen Beweis der Sicherheit mit dem Rekonfigurierungsbitstrom. Die aufwendige Berechnung des Beweises steht im Kontrast zu der vergleichsweise unaufwendigen Überprüfung durch den Konsumenten. Ich präsentiere einen Prototypen basierend auf Open Source Werkzeugen und einer eigenen abstrakten FPGA Architektur samt Bitstromformat. Den Nachweis über die Nutzbarkeit von beweistragender Hardware erbringt die Evaluierung des Prototypen zur beispielhaften Anwendung der Sicherung von kombinatorischer und begrenzt sequenzieller Äquivalenz von Referenzmonitor-Modulen zur Speichersicherheit.","lang":"ger"}],"ddc":["040"],"user_id":"477"},{"_id":"10652","date_updated":"2022-01-06T06:50:49Z","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"page":"159","year":"2012","citation":{"bibtex":"@book{Giefers_2012, place={Berlin}, title={Design and Programming of Reconfigurable Mesh based Many-Cores}, publisher={Logos Verlag Berlin GmbH}, author={Giefers, Heiner}, year={2012} }","mla":"Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Logos Verlag Berlin GmbH, 2012.","ama":"Giefers H. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH; 2012.","apa":"Giefers, H. (2012). Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH.","chicago":"Giefers, Heiner. Design and Programming of Reconfigurable Mesh Based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.","ieee":"H. Giefers, Design and Programming of Reconfigurable Mesh based Many-Cores. Berlin: Logos Verlag Berlin GmbH, 2012.","short":"H. Giefers, Design and Programming of Reconfigurable Mesh Based Many-Cores, Logos Verlag Berlin GmbH, Berlin, 2012."},"type":"dissertation","abstract":[{"text":"The paradigm shift towards many-core parallelism is accompanied by two fundamental questions: how should the many processors on a single die communicate to each other and what are suitable programming models for these novel architectures? In this thesis, the author tackles both questions by reviewing the reconfigurable mesh model of massively parallel computation for many-cores.\r\n\r\nThe book presents the design, implementation and evaluation of a many-core architecture that is based on the execution principles and communication infrastructure of the reconfigurable mesh. This work fundamentally rests on FPGA implementations and shows that reconfigurable mesh processors with hundreds of autonomous cores are feasible. Several case studies demonstrate the effectiveness of programming and illustrate why the reconfigurable mesh is a promising model for many-cores.","lang":"eng"}],"place":"Berlin","user_id":"3118","title":"Design and Programming of Reconfigurable Mesh based Many-Cores","department":[{"_id":"78"}],"author":[{"last_name":"Giefers","first_name":"Heiner","full_name":"Giefers, Heiner"}],"publisher":"Logos Verlag Berlin GmbH","date_created":"2019-07-10T11:13:12Z","status":"public","publication_identifier":{"isbn":["978-3-8325-3165-2"]},"publication_status":"published"}]