Post-configuration Activation of Hardware Trojans in FPGAs - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (Journal of Hardware and Systems Security)
Keywords: General Engineering; Energy Engineering and Power Technology

RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures - Jentzsch, Felix; Umuroglu, Yaman; Pappalardo, Alessandro; Blott, Michaela; Platzner, Marco (IEEE Micro)
Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.

Design of Distributed Reconfigurable Robotics Systems with ReconROS - Lienen, Christian; Platzner, Marco (ACM Transactions on Reconfigurable Technology and Systems)
Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach.

Immersive augmented reality system for the training of pattern classification control with a myoelectric prosthesis - Boschmann, Alexander; Neuhaus, Dorothee; Vogt, Sarah; Kaltschmidt, Christian; Platzner, Marco; Dosen, Strahinja (Journal of NeuroEngineering and Rehabilitation)
Abstract Background Hand amputation can have a truly debilitating impact on the life of the affected person. A multifunctional myoelectric prosthesis controlled using pattern classification can be used to restore some of the lost motor abilities. However, learning to control an advanced prosthesis can be a challenging task, but virtual and augmented reality (AR) provide means to create an engaging and motivating training. Methods In this study, we present a novel training framework that integrates virtual elements within a real scene (AR) while allowing the view from the first-person perspective. The framework was evaluated in 13 able-bodied subjects and a limb-deficient person divided into intervention (IG) and control (CG) groups. The IG received training by performing simulated clothespin task and both groups conducted a pre- and posttest with a real prosthesis. When training with the AR, the subjects received visual feedback on the generated grasping force. The main outcome measure was the number of pins that were successfully transferred within 20 min (task duration), while the number of dropped and broken pins were also registered. The participants were asked to score the difficulty of the real task (posttest), fun-factor and motivation, as well as the utility of the feedback. Results The performance (median/interquartile range) consistently increased during the training sessions (4/3 to 22/4). While the results were similar for the two groups in the pretest, the performance improved in the posttest only in IG. In addition, the subjects in IG transferred significantly more pins (28/10.5 versus 14.5/11), and dropped (1/2.5 versus 3.5/2) and broke (5/3.8 versus 14.5/9) significantly fewer pins in the posttest compared to CG. The participants in IG assigned (mean ± std) significantly lower scores to the difficulty compared to CG (5.2 ± 1.9 versus 7.1 ± 0.9), and they highly rated the fun factor (8.7 ± 1.3) and usefulness of feedback (8.5 ± 1.7). Conclusion The results demonstrated that the proposed AR system allows for the transfer of skills from the simulated to the real task while providing a positive user experience. The present study demonstrates the effectiveness and flexibility of the proposed AR framework. Importantly, the developed system is open source and available for download and further development.
Keywords: Health Informatics; Rehabilitation

Exploiting Hardware-Based Data-Parallel and Multithreading Models for Smart Edge Computing in Reconfigurable FPGAs - Rodriguez, Alfonso; Otero, Andres; Platzner, Marco; De la Torre, Eduardo (IEEE Transactions on Computers)
Keywords: Computational Theory and Mathematics; Hardware and Architecture; Theoretical Computer Science; Software

Software/Hardware Co-Verification for Custom Instruction Set Processors - Jakobs, Marie-Christine; Pauck, Felix; Platzner, Marco; Wehrheim, Heike; Wiersema, Tobias (IEEE Access)
Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.
Keywords: Software Analysis; Abstract Interpretation; Custom Instruction; Hardware Verification

Proof-carrying Approximate Circuits - Witschen, Linus Matthias; Wiersema, Tobias; Platzner, Marco (IEEE Transactions On Very Large Scale Integration Systems)
Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.
Keywords: Approximate circuit synthesis; approximate computing; error metrics; formal verification; proof-carrying hardware

Evolution of Application-Specific Cache Mappings - Ho, Nam; Kaufmann, Paul; Platzner, Marco (International Journal of Hybrid intelligent Systems)

Dynamic Reliability Management for FPGA-Based Systems - Anwer, Jahanzeb; Meisner, Sebastian; Platzner, Marco (International Journal of Reconfigurable Computing)
Radiation tolerance in FPGAs is an important field of research particularly for reliable computation in electronics used in aerospace and satellite missions. The motivation behind this research is the degradation of reliability in FPGA hardware due to single-event effects caused by radiation particles. Redundancy is a commonly used technique to enhance the fault-tolerance capability of radiation-sensitive applications. However, redundancy comes with an overhead in terms of excessive area consumption, latency, and power dissipation. Moreover, the redundant circuit implementations vary in structure and resource usage with the redundancy insertion algorithms as well as number of used redundant stages. The radiation environment varies during the operation time span of the mission depending on the orbit and space weather conditions. Therefore, the overheads due to redundancy should also be optimized at run-time with respect to the current radiation level. In this paper, we propose a technique called Dynamic Reliability Management (DRM) that utilizes the radiation data, interprets it, selects a suitable redundancy level, and performs the run-time reconfiguration, thus varying the reliability levels of the target computation modules. DRM is composed of two parts. The design-time tool flow of DRM generates a library of various redundant implementations of the circuit with different magnitudes of performance factors. The run-time tool flow, while utilizing the radiation/error-rate data, selects a required redundancy level and reconfigures the computation module with the corresponding redundant implementation. Both parts of DRM have been verified by experimentation on various benchmarks. The most significant finding we have from this experimentation is that the performance can be scaled multiple times by using partial reconfiguration feature of DRM, e.g., 7.7 and 3.7 times better performance results obtained for our data sorter and matrix multiplier case studies compared with static reliability management techniques. Therefore, DRM allows for maintaining a suitable trade-off between computation reliability and performance overhead during run-time of an application.

Self-aware Cyber-Physical Systems - Bellman, K.; Dutt, N.; Esterle, L.; Herkersdorf, A.; Jantsch, A.; Landauer, C.; R. Lewis, P.; Platzner, Marco; TaheriNejad, N.; Tammemäe, K. (ACM Transactions on Cyber-Physical Systems)

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation - Witschen, Linus Matthias; Wiersema, Tobias; Ghasemzadeh Mohammadi, Hassan; Awais, Muhammad; Platzner, Marco (Microelectronics Reliability)
Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.
Keywords: Approximate Computing; Framework; Pareto Front; Accuracy

Zynq-based acceleration of robust high density myoelectric signal processing - Boschmann, Alexander; Agne, Andreas; Thombansen, Georg; Witschen, Linus Matthias; Kraus, Florian; Platzner, Marco (Journal of Parallel and Distributed Computing)
Advances in electromyographic (EMG) sensor technology and machine learning algorithms have led to an increased research effort into high density EMG-based pattern recognition methods for prosthesis control. With the goal set on an autonomous multi-movement prosthesis capable of performing training and classification of an amputee’s EMG signals, the focus of this paper lies in the acceleration of the embedded signal processing chain. We present two Xilinx Zynq-based architectures for accelerating two inherently different high density EMG-based control algorithms. The first hardware accelerated design achieves speed-ups of up to 4.8 over the software-only solution, allowing for a processing delay lower than the sample period of 1 ms. The second system achieved a speed-up of 5.5 over the software-only version and operates at a still satisfactory low processing delay of up to 15 ms while providing a higher reliability and robustness against electrode shift and noisy channels.
Keywords: High density electromyography; FPGA acceleration; Medical signal processing; Pattern recognition; Prosthetics

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology - Hansmeier, Tim; Platzner, Marco; Pantho, Md Jubaer Hossain; Andrews, David (Journal of Signal Processing Systems)
Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

FPGAs im Rechenzentrum - Platzner, Marco; Plessl, Christian (Informatik Spektrum)

R-Codesign: Codesign Methodology for Real-Time Reconfigurable Embedded Systems Under Energy Constraints - Ghribi, Ines; Abdallah, Riadh Ben; Khalgui, Mohamed; Li, Zhiwu; Alnowibet, Khalid; Platzner, Marco (IEEE Access)

Three-Stage Power System Restoration Methodology Considering Renewable Energies - Shen, Cong; Kaufmann, Paul; Braun, Martin (Elsevier International Journal of Electrical Power and Energy Systems (IJEPES))
This is a study of a combined load restoration and generator start-up procedure. The procedure is structured into three stages according to the power system status and the goal of load restoration. Moreover, for each load restoration stage, the proposed algorithm determines a load restoration sequence by considering renewable energy such as solar and wind park to achieve objective functions. The validity and performance of the proposed algorithm is demonstrated through simulations using IEEE-39 network.
Keywords: Load restorationRestoration stageRenewable energyVoltage/frequency fluctuations

Proof-Carrying Hardware via Inductive Invariants - Isenberg, Tobias; Platzner, Marco; Wehrheim, Heike; Wiersema, Tobias (ACM Transactions on Design Automation of Electronic Systems)
Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.

The First 25 Years of the FPL Conference – Significant Papers - H.W. Leong, Philip; Amano, Hideharu; Anderson, Jason; Bertels, Koen; M.P. Cardoso, João; Diessel, Oliver; Gogniat, Guy; Hutton, Mike; Lee, JunKyu; Luk, Wayne; Lysaght, Patrick; Platzner, Marco; et al. (ACM Transactions on Reconfigurable Technology and Systems)

Innovation in Reconfigurable Computing Fabrics: from Devices to Architectures (guest editorial) - F. DeMara, Ronald; Platzner, Marco; Ottavi, Marco (IEEE Transactions on Computers and IEEE Transactions on Emerging Topics in Computing)

Evaluating fault-tolerance of redundant FPGA structures using Boolean difference calculus - Anwer, Jahanzeb; Platzner, Marco (Microprocessors and Microsystems)

Three-Stage Power System Restoration Methodology Considering Renewable Energies - Shen, Cong; Kaufmann, Paul; Braun, Martin (Elsevier International Journal of Electrical Power and Energy Systems (IJEPES))

Fast Network Restoration by Partitioning of Parallel Black Start Zones - Shen, Cong; Kaufmann, Paul; Braun, Martin (The Journal of Engineering)

An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Computers & Electrical Engineering)
Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

Adaptive playouts for online learning of policies during Monte Carlo Tree Search - Graf, Tobias; Platzner, Marco (Journal Theoretical Computer Science)

Optimal Generation Dispatch of Distributed Generators Considering Fair Contribution to Grid Voltage Control - Ma, Chenjie; Kaufmann, Paul; Töbermann, J.-Christian; Braun, Martin (Renewable Energy)

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems)

Self-Aware and Self-Expressive Systems – Guest Editor's Introduction - Torresen, Jim; Plessl, Christian; Yao, Xin (IEEE Computer)
Keywords: self-awareness; self-expression

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires - Ghasemzadeh Mohammadi, Hassan; Gaillardon, Pierre-Emmanuel; De Micheli, Giovanni (IEEE Transactions on Nanotechnology)

Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (International Journal of Reconfigurable Computing (IJRC))
FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

Aktuelles Schlagwort: Approximate Computing - Plessl, Christian; Platzner, Marco; Schreier, Peter J. (Informatik Spektrum)
Keywords: approximate computing; survey

A Novel Technique and its Application to Computer Go - Schaefers, Lars; Platzner, Marco (IEEE Transactions on Computational Intelligence and AI in Games)

An FPGA-based Reconfigurable Mesh Many-Core - Giefers, Heiner; Platzner, Marco (IEEE Transactions on Computers)

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators - Agne, Andreas; Hangmann, Hendrik; Happe, Markus; Platzner, Marco; Plessl, Christian (Microprocessors and Microsystems)
Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores - Agne, Andreas; Happe, Markus; Lösch, Achim; Plessl, Christian; Platzner, Marco (ACM Transactions on Reconfigurable Technology and Systems (TRETS))
Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.

ReconOS - An Operating System Approach for Reconfigurable Computing - Agne, Andreas; Happe, Markus; Keller, Ariane; Lübbers, Enno; Plattner, Bernhard; Platzner, Marco; Plessl, Christian (IEEE Micro)
The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers - Giefers, Heiner; Plessl, Christian; Förstner, Jens (ACM SIGARCH Computer Architecture News)
Keywords: funding-maxup; tet_topic_hpc

Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices - Kasap, Server; Redif, Soydan (IEEE Trans. on Very Large Scale Integration (VLSI) Systems)

A Self-adaptive Heterogeneous Multi-core Architecture for Embedded Real-time Video Object Tracking - Happe, Markus; Lübbers, Enno; Platzner, Marco (International Journal of Real-time Image Processing)

Classification of Electromyographic Signals: Comparing Evolvable Hardware to Conventional Classifiers - Kaufmann, Paul; Glette, Kyrre; Gruber, Tiemo; Platzner, Marco; Torresen, Jim; Sick, Bernhard (IEEE Transactions on Evolutionary Computation)

STIR: Software for Tomographic Image Reconstruction Release 2 - Thielemans, Kris; Tsoumpas, Charalampos; Mustafovic, Sanida; Beisel, Tobias; Aguiar, Pablo; Dikaios, Nikolaos; W Jacobson, Matthew (Physics in Medicine and Biology)

Parallel algorithm for computation of second-order sequential best rotations - Redif, Soydan; Kasap, Server (Int. Journal of Electronics)

Parallel Processor Design and Implementation for Molecular Dynamics Simulations on a FPGA Parallel Computer - Kasap, Server; Benkrid, Khaled (Journal of Computers)

Compensating Resource Fluctuations by Means of Evolvable Hardware: The Run-Time Reconfigurable Functional Unit Row Classifier Architecture - Kaufmann, Paul; Glette, Kyrre; Platzner, Marco; Torresen, Jim (International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS))

IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators - Schumacher, Tobias; Plessl, Christian; Platzner, Marco (Microprocessors and Microsystems)
Keywords: funding-altera

On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors - Grad, Mariusz; Plessl, Christian (Int. Journal of Reconfigurable Computing (IJRC))

FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study - Schumacher, Tobias; Süß, Tim; Plessl, Christian; Platzner, Marco (Int. Journal of Recon- figurable Computing (IJRC))
Keywords: funding-altera

Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification - Drzevitzky, Stephanie; Kastens, Uwe; Platzner, Marco (International Journal of Reconfigurable Computing)

Selected papers from the 18th International Conference on Field Programmable Logic and Applications, FPL 2008 (editorial) - Kebschull, Udo; Platzner, Marco; Teich, Jürgen (IET Computers Digital Techniques)

ReconOS: Multithreaded Programming for Reconfigurable Computers - Lübbers, Enno; Platzner, Marco (ACM Transactions on Embedded Computing Systems)
Keywords: Reconfigurable computing; multithreading; operating systems

Dynamically Reconfigurable Architectures (editorial) - Bergmann, Neil; Platzner, Marco; Teich, Jürgen (EURASIP Journal on Embedded Systems)