TY - GEN AU - Raeisi Nafchi, Masood ID - 46075 TI - Reconfigurable Random Forest Implementation on FPGA ER - TY - GEN AU - Raeisi Nafchi, Masood ID - 45917 TI - Reconfigurable Random Forest Implementation on FPGA ER - TY - GEN AU - Yadalam Murali Kumar, Nihal ID - 45916 TI - Data Analytics for Predictive Maintenance of Time Series Data ER - TY - GEN AU - Kaur , Parvinder ID - 45915 TI - Analysis of Time-Series Classification in Conditional Monitoring Systems ER - TY - GEN AU - Manjunatha, Suraj ID - 45914 TI - Dealing With Pre-Processing And Feature Extraction Of Time-Series Data In Predictive Maintenance ER - TY - GEN AU - Tcheussi Ngayap, Vanessa Ingrid ID - 45715 TI - FreeRTOS on a MicroBlaze Soft-Core Processor with Hardware Accelerators ER - TY - GEN AB - Autonomous mobile robots are becoming increasingly more capable and widespread. Reliable Obstacle avoidance is an integral part of autonomous navigation. This involves real time interpretation and processing of a complex environment. Strict time and energy constraints of a mobile autonomous system make efficient computation extremely desirable. The benefits of employing Hardware/Software co-designed applications are obvious and significant. Hardware accelerators are used for efficient processing of the algorithms by exploiting parallelism. FPGAs are a class of hardware accelerators, which can contain hundreds of small execution units, and can be used for Hardware/Software co-designed application. However, there is a reluctance when it comes to adoption of these devices in well established application domains, such as Robotics, due to a steep learning curve needed for FPGA application design. ReconROS has successfully bridged the gap between robotic and FPGA application development, by providing an intuitive, common development platform for robotic application development for FPGA. It does so by integrating Robotics Operating System(ROS) which is an industry and academia standard for robotics application development, with ReconOS, an operating system for re-configurable hardware. In this thesis an obstacle avoidance system is designed and implemented for an autonomous vehicle using ReconROS. The objectives of the thesis is to demonstrate and explore ReconROS integration within the ROS ecosystem and explore the design process within ReconROS framework, and to demonstrate the effectiveness of Hardware Acceleration in Robotics, by analysing the resulting architectures for Latency and Power Consumption. AU - Sheikh, Muhammad Aamir ID - 29540 TI - Design and Implementation of a ReconROS-based Obstacle Avoidance System ER - TY - GEN AB - Automation becomes a vital part in the High-Performance computing system in situational dynamics to take the decisions on the fly. Heterogeneous compute nodes consist of computing resources such as CPU, GPU and FPGA and are the important components of the high-performance computing system that can adapt the automation to achieve the given goal. While implanting automation in the computing resources, management of the resources is one of the essential aspects that need to be taken care of. Tasks are continuously executed on the resources using its unique characteristics. Effective scheduling is essential to make the best use of the characteristics provided by each resource. Scheduling enables the execution of each task by allocating resources so that they take advantage of all the characteristics of the compute resources. Various scheduling heuristics can be used to create effective scheduling, which might require the execution time to schedule the task efficiently. Providing actual execution time is not possible in many cases; hence we can provide the estimations for the actual execution time . The purpose of this master's thesis is to design a predictive model or system that estimates the execution time required to execute tasks using historical execution time data on the heterogeneous compute nodes. In this thesis, regression techniques(SGD Regressor, Passive-Aggressive Regressor, MLP Regressor, and XCSF Regressor) are compared in terms of their prediction accuracy in order to determine which technique produces reliable predictions for the execution time. These estimations must be generated in an online learning environment in which data points arrive in any sequence, one by one, and the regression model must learn from them. After evaluating the regression algorithms, it is seen that the XCSF regressor provides the highest overall prediction accuracy for the supplied data sets. The regression technique's parameters also play a significant role in achieving an acceptable prediction accuracy. As a remark, when using online learning in regression analysis, the accuracy depends upon both the order of sequential data points that are coming to train the model and the parameter configuration for each regression technique. AU - Kashikar, Chinmay ID - 29151 TI - A Comparison of Machine Learning Techniques for the On-line Characterization of Tasks Executed on Heterogeneous Compute Nodes ER - TY - GEN AB - Modern machine learning (ML) techniques continue to move into the embedded system space because traditional centralized compute resources do not suit certain application domains, for example in mobile or real-time environments. Google’s TensorFlow Lite (TFLite) framework supports this shift from cloud to edge computing and makes ML inference accessible on resource-constrained devices. While it offers the possibility to partially delegate computation to hardware accelerators, there is no such “delegate” available to utilize the promising characteristics of reconfigurable hardware. This thesis incorporates modern platform FPGAs into TFLite by implementing a modular delegate framework, which allows accelerators within the programmable logic to take over the execution of neural network layers. To facilitate the necessary hardware/software codesign, the FPGA delegate is based on the operating system for reconfigurable computing (ReconOS), whose partial reconfiguration support enables the instantiation of model-tailored accelerator architectures. In the hardware back-end, a streaming-based prototype accelerator for the MobileNet model family showcases the working order of the platform, but falls short of the desired performance. Thus, it indicates the need for further exploration of alternative accelerator designs, which the delegate could automatically synthesize to meet a model’s demands. AU - Jentzsch, Felix P. ID - 21433 TI - Design and Implementation of a ReconOS-based TensorFlow Lite Delegate Architecture ER - TY - GEN AU - Chandrakar, Khushboo ID - 21324 TI - Comparison of Feature Selection Techniques to Improve Approximate Circuit Synthesis ER - TY - GEN AU - Jaganath, Vivek ID - 20821 TI - Extension and Evaluation of Python-based High-Level Synthesis Tool Flows ER - TY - GEN AU - Mehta, Jinay D ID - 52478 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Reconfigurable System-on-Chip ER - TY - GEN AU - Lienen, Christian ID - 15874 TI - Implementing a Real-time System on a Platform FPGA operated with ReconOS ER - TY - GEN AB - Secure hardware design is the most important aspect to be considered in addition to functional correctness. Achieving hardware security in today’s globalized Integrated Cir- cuit(IC) supply chain is a challenging task. One solution that is widely considered to help achieve secure hardware designs is Information Flow Tracking(IFT). It provides an ap- proach to verify that the systems adhere to security properties either by static verification during design phase or dynamic checking during runtime. Proof-Carrying Hardware(PCH) is an approach to verify a functional design prior to using it in hardware. It is a two-party verification approach, where the target party, the consumer requests new functionalities with pre-defined properties to the producer. In response, the producer designs the IP (Intellectual Property) cores with the requested functionalities that adhere to the consumer-defined properties. The producer provides the IP cores and a proof certificate combined into a proof-carrying bitstream to the consumer to verify it. If the verification is successful, the consumer can use the IP cores in his hardware. In essence, the consumer can only run verified IP cores. Correctly applied, PCH techniques can help consumers to defend against many unintentional modifications and malicious alterations of the modules they receive. There are numerous published examples of how to use PCH to detect any change in the functionality of a circuit, i.e., pairing a PCH approach with functional equivalence checking for combinational or sequential circuits. For non-functional properties, since opening new covert channels to leak secret information from secure circuits is a viable attack vector for hardware trojans, i.e., intentionally added malicious circuitry, IFT technique is employed to make sure that secret/untrusted information never reaches any unclassified/trusted outputs. This master thesis aims to explore the possibility of adapting Information Flow Tracking into a Proof-Carrying Hardware scenario. It aims to create a method that combines Infor- mation Flow Tracking(IFT) with a PCH approach at bitstream level enabling consumers to validate the trustworthiness of a module’s information flow without the computational costs of a complete flow analysis. AU - Keerthipati, Monica ID - 15920 TI - A Bitstream-Level Proof-Carrying Hardware Technique for Information Flow Tracking ER - TY - GEN AU - Mehta, Jinay ID - 15946 TI - Multithreaded Software/Hardware Programming with ReconOS/freeRTOS on a Recon􏰃gurable System-on-Chip ER - TY - GEN AU - Kumar Jeyakumar, Shankar ID - 15883 TI - Incremental learning with Support Vector Machine on embedded platforms ER - TY - GEN AU - Sabu, Nithin S. ID - 14831 TI - FPGA Acceleration of String Search Techniques in Huge Data Sets ER - TY - GEN AU - Hansmeier, Tim ID - 14546 TI - Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers ER - TY - GEN AU - Clausing, Lennart ID - 10782 TI - Development of a Hardware / Software Codesign for sonification of LIDAR-based sensor data ER - TY - GEN AU - Knorr, Christoph ID - 74 TI - OpenCL-basierte Videoverarbeitung auf heterogenen Rechenknoten ER - TY - GEN AU - Witschen, Linus Matthias ID - 1157 TI - A Framework for the Synthesis of Approximate Circuits ER - TY - GEN AU - Dietrich, Andreas ID - 10708 TI - Reconfigurable Cryptographic Services ER - TY - GEN AU - Riaz, Umair ID - 10666 TI - Acceleration of Industrial Analytics Functions on a Platform FPGA ER - TY - GEN AU - Makeswaran, Vignesh ID - 10706 TI - Operating System Support for Reconfigurable Cache ER - TY - GEN AU - Ibne Ashraf, Ishraq ID - 10707 TI - Private/Shared Data Classification and Implementation for a Multi-Softcore Platform ER - TY - GEN AU - Cedric Mertens, Jan ID - 10612 TI - Sprint Diagnostic with RTK-GPS \& IMU Sensor Fusion ER - TY - GEN AU - Nassery, Abdul Sami ID - 10616 TI - Implementation of Bilinear Pairings on Reconfigurable Hardware ER - TY - GEN AU - Amin, Omair ID - 10617 TI - Acceleration of EMTP for Distribution Networks on Data Flow Machines using the Latency Insertion Method ER - TY - GEN AU - Posewsky, Thorbjörn ID - 10726 TI - Acceleration of Artificial Neural Networks on a Zynq Platform ER - TY - GEN AU - Hangmann, Hendrik ID - 10668 TI - Evolution of Heat Flow Prediction Models for FPGA Devices ER - TY - GEN AU - Haupt, Christian ID - 10671 TI - Computer Vision basierte Klassifikation von HD EMG Signalen ER - TY - GEN AU - Ahmed, Abdullah Fathi ID - 10615 TI - Self-Optimizing Organic Cache ER - TY - GEN AU - Koch, Benjamin ID - 10701 TI - Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - GEN AU - Mittendorf, Robert ID - 10715 TI - Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs ER - TY - GEN AU - Surmund, Sebastian ID - 10744 TI - Multithreaded Parallelization of Mechatronic Controllers on a Zynq Platform FPGA ER - TY - GEN AU - Brand, Marcel ID - 10640 TI - A Generalized Loop Accelerator Implemented as a Coarse-Grained Array ER - TY - GEN AU - Damschen, Marvin ID - 10645 TI - Easy-to-use-on-the-fly binary program acceleration on many-cores ER - TY - GEN AU - Riebler, Heinrich ID - 10730 TI - Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs ER - TY - GEN AU - Wistuba, Martin ID - 10754 TI - Analysis of Pattern Based Model Design and Learning in Computer-Go ER - TY - GEN AU - Dridger, Denis ID - 10650 TI - Design and Implementation of a Nanophotonics Simulation Personality for the Convey HC-1 Hybrid Core Computer ER - TY - GEN AU - Graf, Tobias ID - 10658 TI - Adaptive Playouts in der Monte-Carlo Spielbaumsuche am Anwendungsfall Go ER - TY - GEN AU - Schwabe, Arne ID - 10736 TI - Analysis of Algorithmic Approaches for Temporal Partitioning ER - TY - GEN AU - Welp, Daniel ID - 10750 TI - User Space Scheduling for Heterogeneous Systems ER - TY - GEN AU - Meiche, Robert ID - 10710 TI - FPGA/CPU Multicore-Plattform für ReconOS/eCos ER - TY - GEN AU - Niekamp, Manuel ID - 10717 TI - Transparente Hardwarebeschleunigung durch Shared Library Interposing ER - TY - GEN AU - Runde, Bodo ID - 10731 TI - A Token-Ring Network-On-Chip for Message Passing in ReconOS ER - TY - GEN AU - Wiersema, Tobias ID - 10752 TI - Scheduling Support for Heterogeneous Hardware Accelerators under Linux ER - TY - GEN AU - Breitlauch, Daniel ID - 10642 TI - Evolvable Cache Controller ER - TY - GEN AU - Knieper, Tobias ID - 10697 TI - Hybridization of Global Multi-Objective and Local Search Techniques ER - TY - GEN AU - Boschmann, Alexander ID - 10629 TI - EMG-basierte Ganganalyse ER - TY - GEN AU - Agne, Andreas ID - 10614 TI - Virtuelle Speicherverwaltung für Hardware Threads in Rekonfigurierbaren Systemen ER - TY - GEN AU - Kostin, Alexander ID - 10702 TI - Evolvable Robot Controller ER - TY - GEN AU - Tofall, Martin ID - 10746 TI - Compiler for a Custom Instruction Set CPU ER - TY - GEN AU - Warkentin, Alexander ID - 10749 TI - Coarse-grained CGP Model using Xilinx Virtex5 DSP48E Functional Units ER - TY - GEN AU - Happe, Markus ID - 10669 TI - Parallelisierung und Hardware- / Software - Codesign von Partikelfiltern ER - TY - GEN AU - Reisch, Waldemar ID - 10728 TI - Bildverarbeitungs-Architekturen und -Bibliotheken für das rekonfigurierbare Betriebssystem ReconOS ER - TY - GEN AU - Rethmeier, Eike ID - 10729 TI - Konzeption und Implementierung einer Microsoft Windows CE 5.0 Plattform für ein ARM-basiertes eingebettetes Rechnersystem ER - TY - GEN AU - Defo, Bertrand ID - 10647 TI - A Comparison of Multi-Objective Evolutionary Algorithms for Automated Circuit Design and Optimization ER - TY - GEN AU - Döhre, Sven ID - 10648 TI - Entwurf und Implementierung einer RocketIO-basierten Kommunikationsschnittstelle für Multi-FPGA Systeme ER - TY - GEN AU - Beisel, Tobias ID - 10623 TI - Entwurf und Evaluation eines parallelen Verfahrens zur Bildrekonstruktion in der Positronen-Emissions-Tomographie auf Multi-Core-Architekturen ER -