Selbsttestbare Steuerwerke - Strukturen und Syntheseverfahren - Hellebrand, Sybille

Exploiting Symmetries to Speed Up Transparent BIST - Hellebrand, Sybille; Wunderlich, Hans-Joachim; N. Yarmolik, Vyacheslav
Keywords: WORKSHOP

Error Detecting Refreshment for Embedded DRAMs - Hellebrand, Sybille; Wunderlich, Hans-Joachim; A. Ivaniuk, Alexander; V. Klimets, Yuri; N. Yarmolik, Vyacheslav (17th IEEE VLSI Test Symposium (VTS'99))

Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms - N. Yarmolik, Vyacheslav; V. Bykov, Iuri; Hellebrand, Sybille; Wunderlich, Hans-Joachim (Third European Dependable Computing Conference (EDCC-3))

Symmetric Transparent BIST for RAMs - Hellebrand, Sybille; Wunderlich, Hans-Joachim; N. Yarmolik, Vyacheslav (Design Automation and Test in Europe (DATE'99))

Test und Synthese schneller eingebetteter Systeme - Hellebrand, Sybille; Wunderlich, Hans-Joachim

Efficient Consistency Checking for Embedded Memories - N. Yarmolik, Vyacheslav; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Efficient Consistency Checking for Embedded Memories - N. Yarmolik, Vyacheslav; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Mixed-Mode BIST Using Embedded Processors - Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre (Mixed-Mode BIST Using Embedded Processors)

Mixed-Mode BIST Using Embedded Processors - Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre (Journal of Electronic Testing Theory and Applications - JETTA)

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications - Hellebrand, Sybille; Hertwig, Andre; Wunderlich, Hans-Joachim (IEEE Design and Test)

Fast Self-Recovering Controllers - Hertwig, Andre; Hellebrand, Sybille; Wunderlich, Hans-Joachim (16th IEEE VLSI Test Symposium (VTS'98))

Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs - Hellebrand, Sybille; Wunderlich, Hans-Joachim; N. Yarmolik, Vyacheslav (Design Automation and Test in Europe (DATE'98))

New Transparent RAM BIST Based on Self-Adjusting Output Data Compression - N. Yarmolik, Vyacheslav; V. Klimets, Yuri; Hellebrand, Sybille; Wunderlich, Hans-Joachim (Design & Diagnostics of Electronic Circuits & Systems (DDECS'98))

STARBIST: Scan Autocorrelated Random Pattern Generation - Tsai, Kun-Han; Hellebrand, Sybille; Rajski, Janusz; Marek-Sadowska, Malgorzata
Keywords: WORKSHOP

Synthesis of Fast On-Line Testable Controllers for Data-Dominated Applications - Hertwig, Andre; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

STARBIST: Scan Autocorrelated Random Pattern Generation - Tsai, Kun-Han; Hellebrand, Sybille; Marek-Sadowska, Malgorzata; Rajski, Janusz (34th ACM/IEEE Design Automation Conference (DAC'97))

Using Embedded Processors for BIST - Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Mixed-Mode BIST Using Embedded Processors - Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre
Keywords: WORKSHOP

Mixed-Mode BIST Using Embedded Processors - Hellebrand, Sybille; Wunderlich, Hans-Joachim; Hertwig, Andre (IEEE International Test Conference (ITC'96))

Synthesis Procedures for Self-Testable Controllers - Hellebrand, Sybille; Wunderlich, Hans-Joachim

Evaluation of Self-Testable Controller Architectures Based on Realistic Fault Analysis - Hellebrand, Sybille; Wunderlich, Hans-Joachim; Goncalves, F.; Paulo Teixeira, Joao

Partitioning of CMOS-Circuits for On-Chip IDDQ-Testing - Hellebrand, Sybille; Herzog, Maik; Wunderlich, Hans-Joachim

Pattern Generation for a Deterministic BIST Scheme - Hellebrand, Sybille; Reeb, Birgit; Tarnick, Steffen; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers - Hellebrand, Sybille; Rajski, Janusz; Tarnick, Steffen; Venkataraman, Srikanth; Courtois, B. (IEEE Transactions on Computers)

Pattern Generation for a Deterministic BIST Scheme - Hellebrand, Sybille; Reeb, Birgit; Tarnick, Steffen; Wunderlich, Hans-Joachim (ACM/IEEE International Conference on Computer Aided Design (ICCAD'95))

Synthesis for Off-line Testability - Hellebrand, Sybille; Juergensen, Arne; Wunderlich, Hans-Joachim

Chip Level Test Planning for Controlling the Tradeoff between Hardware Overhead and Test Time - Hellebrand, Sybille; Juergensen, Arne; Stroele, Albrecht; Wunderlich, Hans-Joachim

Effiziente Testsatzkodierung für Prüfpfad-basierte Selbsttestarchitekturen - Venkataraman, Srikanth; Rajski, Janusz; Hellebrand, Sybille; Tarnick, Steffen
Keywords: WORKSHOP

Ein Verfahren zur testfreundlichen Steuerwerkssynthese - Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Synthesis for Testability - the ARCHIMEDES Approach - Hellebrand, Sybille; Paulo Teixeira, Joao; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

An Efficient Procedure for the Synthesis of Fast Self-Testable Controller Structures - Hellebrand, Sybille; Wunderlich, Hans-Joachim (ACM/IEEE International Conference on Computer-Aided Design (ICCAD'94))

Synthese schneller selbsttestbarer Steuerwerke - Hellebrand, Sybille; Wunderlich, Hans-Joachim (Tagungsband der GI/GME/ITG-Fachtagung & Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme)

Synthesis of Self-Testable Controllers - Hellebrand, Sybille; Wunderlich, Hans-Joachim (European Design and Test Conference (EDAC/ETC/EUROASIC))

Effiziente Erzeugung deterministischer Muster im Selbsttest - Hellebrand, Sybille; Tarnick, Steffen; Rajski, Janusz; Courtois, Bernard
Keywords: WORKSHOP

Synthesis of Self-Testable Controllers - Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

An Efficient Bist Scheme Based On Reseeding Of Multiple Polynomial Linear Feedback Shift Registers - Venkataraman, Srikanth; Rajski, Janusz; Hellebrand, Sybille; Tarnick, Steffen (ACM/IEEE International Conference on Computer Aided Design (ICCAD'93))

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs - Hellebrand, Sybille; Tarnick, Steffen; Rajski, Janusz; Courtois, Bernard

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs - Hellebrand, Sybille; Tarnick, Steffen; Rajski, Janusz; Courtois, Bernard
Keywords: WORKSHOP

Generation of Vector Patterns through Reseeding of Multiple-Polynomial LFSRs - Hellebrand, Sybille; Tarnick, Steffen; Rajski, Janusz; Courtois, Bernard
Keywords: WORKSHOP

The Pseudoexhaustive Test of Sequential Circuits - Wunderlich, Hans-Joachim; Hellebrand, Sybille (IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD))

Generation of Vector Patterns through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers - Hellebrand, Sybille; Tarnick, Steffen; Rajski, Janusz; Courtois, Bernard (IEEE International Test Conference (ITC'92))

Synthese vollständig testbarer Schaltungen - Hellebrand, Sybille

Generating Pseudo-Exhaustive Vectors for External Testing - Hellebrand, Sybille; Wunderlich, Hans-Joachim; F. Haberl, Oliver
Keywords: WORKSHOP

Tools and Devices Supporting the Pseudo-Exhaustive Test - Hellebrand, Sybille; Wunderlich, Hans-Joachim (European Design Automation Conference (EDAC'90))

Generating Pseudo-Exhaustive Vectors for External Testing - Hellebrand, Sybille; Wunderlich, Hans-Joachim; F. Haberl, Oliver (IEEE International Test Conference (ITC'90))

The Pseudo-Exhaustive Test of Sequential Circuits - Wunderlich, Hans-Joachim; Hellebrand, Sybille (IEEE International Test Conference (ITC'89))

Generating Pattern Sequences for the Pseudo-Exhaustive Test of MOS-Circuits - Wunderlich, Hans-Joachim; Hellebrand, Sybille (18th International Symposium on Fault-Tolerant Computing, FTCS-18)

Integrated Tools for Automatic Design for Testability - Schmid, Detlef; Wunderlich, Hans-Joachim; Feldbusch, Fridtjof; Hellebrand, Sybille; Holzinger, Juergen; Kunzmann, Arno (Tool Integration and Design Environments, F.J. Rammig (Editor))

Automatisierung des Entwurfs vollständig testbarer Schaltungen - Hellebrand, Sybille; Wunderlich, Hans-Joachim (GI - 18. Jahrestagung II, Hamburg, 1988, Informatik-Fachberichte 188)