Post-configuration Activation of Hardware Trojans in FPGAs - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (Journal of Hardware and Systems Security)
Keywords: General Engineering; Energy Engineering and Power Technology

Search Space Characterization for Approximate Logic Synthesis - Witschen, Linus Matthias; Wiersema, Tobias; Reuter, Lucas David; Platzner, Marco (2022 59th ACM/IEEE Design Automation Conference (DAC))

MUSCAT: MUS-based Circuit Approximation Technique - Witschen, Linus Matthias; Wiersema, Tobias; Artmann, Matthias; Platzner, Marco (Design, Automation and Test in Europe (DATE))

Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware - Wiersema, Tobias
Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts. This thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques.
Keywords: Proof-Carrying Hardware; Formal Verification; Sequential Circuits; Non-Functional Properties; Functional Properties

Timing Optimization for Virtual FPGA Configurations - Witschen, Linus Matthias; Wiersema, Tobias; Raeisi Nafchi, Masood; Bockhorn, Arne; Platzner, Marco (Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21))

Software/Hardware Co-Verification for Custom Instruction Set Processors - Jakobs, Marie-Christine; Pauck, Felix; Platzner, Marco; Wehrheim, Heike; Wiersema, Tobias (IEEE Access)
Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.
Keywords: Software Analysis; Abstract Interpretation; Custom Instruction; Hardware Verification

Malicious Routing: Circumventing Bitstream-level Verification for FPGAs - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (2021 Design, Automation & Test in Europe Conference & Exhibition (DATE))
The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques.

Proof-carrying Approximate Circuits - Witschen, Linus Matthias; Wiersema, Tobias; Platzner, Marco (IEEE Transactions On Very Large Scale Integration Systems)
Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.
Keywords: Approximate circuit synthesis; approximate computing; error metrics; formal verification; proof-carrying hardware

Search Space Characterization for AxC Synthesis - Witschen, Linus Matthias; Wiersema, Tobias; Platzner, Marco (Fifth Workshop on Approximate Computing (AxC 2020))
On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies. In the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. In this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification. In our experimental results, we present the runtimes of our approach.

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation - Witschen, Linus Matthias; Wiersema, Tobias; Ghasemzadeh Mohammadi, Hassan; Awais, Muhammad; Platzner, Marco (Microelectronics Reliability)
Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.
Keywords: Approximate Computing; Framework; Pareto Front; Accuracy

Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan - Ahmed, Qazi Arbab; Wiersema, Tobias; Platzner, Marco (Applied Reconfigurable Computing)
Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers.

CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation - Witschen, Linus Matthias; Wiersema, Tobias; Ghasemzadeh Mohammadi, Hassan; Awais, Muhammad; Platzner, Marco (Third Workshop on Approximate Computing (AxC 2018))
Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we ﬁrst analyze and classify related approaches and then present CIRCA, our ﬂexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.
Keywords: Approximate Computing; Framework; Pareto Front; Accuracy

Making the Case for Proof-carrying Approximate Circuits - Witschen, Linus Matthias; Wiersema, Tobias; Platzner, Marco (4th Workshop On Approximate Computing (WAPCO 2018))

Proof-Carrying Hardware via Inductive Invariants - Isenberg, Tobias; Platzner, Marco; Wehrheim, Heike; Wiersema, Tobias (ACM Transactions on Design Automation of Electronic Systems)
Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits.

An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Computers & Electrical Engineering)
Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved.

Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware - Wiersema, Tobias; Platzner, Marco (Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016))
Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module.

On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach - Wiersema, Tobias; Wu, Sen; Platzner, Marco (Proceedings of the International Symposium in Reconfigurable Computing (ARC))
Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level.

Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring - Wiersema, Tobias; Drzevitzky, Stephanie; Platzner, Marco (Proceedings of the International Conference on Field-Programmable Technology (FPT))
Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric.

Integrating Software and Hardware Verification - Jakobs, Marie-Christine; Platzner, Marco; Wiersema, Tobias; Wehrheim, Heike (Proceedings of the 11th International Conference on Integrated Formal Methods (iFM))
Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques.

Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA - Wiersema, Tobias; Bockhorn, Arne; Platzner, Marco (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA.

Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux - Beisel, Tobias; Wiersema, Tobias; Plessl, Christian; Brinkmann, André (Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS))
Keywords: funding-enhance

Cooperative multitasking for heterogeneous accelerators in the Linux Completely Fair Scheduler - Beisel, Tobias; Wiersema, Tobias; Plessl, Christian; Brinkmann, André (Proc. Int. Conf. on Application-Specific Systems, Architectures, and Processors (ASAP))

Scheduling Support for Heterogeneous Hardware Accelerators under Linux - Wiersema, Tobias