Compute Centers I: Heterogeneous Execution Environments - Hansmeier, Tim; Kenter, Tobias; Meyer, Marius; Riebler, Heinrich; Platzner, Marco; Plessl, Christian (On-The-Fly Computing -- Individualized IT-services in dynamic markets)

Integrating Safety Guarantees into the Learning Classifier System XCS - Hansmeier, Tim; Platzner, Marco (Applications of Evolutionary Computation, EvoApplications 2022, Proceedings)

XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion - Hansmeier, Tim; Brede, Mathis; Platzner, Marco (GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion)

An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS - Hansmeier, Tim; Platzner, Marco (GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion)

Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS - Hansmeier, Tim (HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies)

Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold - Hansmeier, Tim; Kaufmann, Paul; Platzner, Marco (GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion)

An Adaption Mechanism for the Error Threshold of XCSF - Hansmeier, Tim; Kaufmann, Paul; Platzner, Marco (GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion)

An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology - Hansmeier, Tim; Platzner, Marco; Pantho, Md Jubaer Hossain; Andrews, David (Journal of Signal Processing Systems)
Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers - Hansmeier, Tim

An FPGA/HMC-Based Accelerator for Resolution Proof Checking - Hansmeier, Tim; Platzner, Marco; Andrews, David (ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications)
Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.

An FPGA Accelerator for Checking Resolution Proofs - Hansmeier, Tim