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Johannes Gutenberg-Universität Mainz."},"date_updated":"2022-01-06T06:53:23Z","publisher":"Johannes Gutenberg-Universität Mainz","author":[{"last_name":"Meister","full_name":"Meister, Dirk","first_name":"Dirk"}],"date_created":"2018-03-26T15:13:49Z","title":"Advanced Data Deduplication Techniques and Their Application","type":"dissertation","status":"public","_id":"1791","user_id":"24135","department":[{"_id":"27"}]},{"type":"journal_article","publication":"IEEE Trans. on Very Large Scale Integration (VLSI) Systems","status":"public","user_id":"24135","department":[{"_id":"27"},{"_id":"78"}],"_id":"1792","issue":"3","citation":{"apa":"Kasap, S., &#38; Redif, S. (2013). Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, <i>22</i>(3), 522–536. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>","bibtex":"@article{Kasap_Redif_2013, title={Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices}, volume={22}, DOI={<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>}, number={3}, journal={IEEE Trans. on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE}, author={Kasap, Server and Redif, Soydan}, year={2013}, pages={522–536} }","mla":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, IEEE, 2013, pp. 522–36, doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>.","short":"S. Kasap, S. Redif, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 22 (2013) 522–536.","ama":"Kasap S, Redif S. Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices. <i>IEEE Trans on Very Large Scale Integration (VLSI) Systems</i>. 2013;22(3):522-536. doi:<a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">10.1109/TVLSI.2013.2248069</a>","ieee":"S. Kasap and S. Redif, “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices,” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i>, vol. 22, no. 3, pp. 522–536, 2013.","chicago":"Kasap, Server, and Soydan Redif. “Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices.” <i>IEEE Trans. on Very Large Scale Integration (VLSI) Systems</i> 22, no. 3 (2013): 522–36. <a href=\"https://doi.org/10.1109/TVLSI.2013.2248069\">https://doi.org/10.1109/TVLSI.2013.2248069</a>."},"intvolume":"        22","page":"522-536","year":"2013","date_created":"2018-03-26T15:15:03Z","author":[{"full_name":"Kasap, Server","last_name":"Kasap","first_name":"Server"},{"first_name":"Soydan","last_name":"Redif","full_name":"Redif, Soydan"}],"volume":22,"date_updated":"2022-01-06T06:53:23Z","publisher":"IEEE","doi":"10.1109/TVLSI.2013.2248069","title":"Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices"},{"user_id":"24135","department":[{"_id":"27"}],"_id":"1793","type":"conference","publication":"Proc. USENIX Conference on File and Storage Technologies (FAST)","status":"public","date_created":"2018-03-26T15:16:03Z","author":[{"first_name":"Dirk","full_name":"Meister, Dirk","last_name":"Meister"},{"full_name":"Brinkmann, André","last_name":"Brinkmann","first_name":"André"},{"first_name":"Tim","last_name":"Süß","full_name":"Süß, Tim"}],"publisher":"USENIX Association","date_updated":"2022-01-06T06:53:23Z","title":"File Recipe Compression in Data Deduplication Systems","citation":{"bibtex":"@inproceedings{Meister_Brinkmann_Süß_2013, title={File Recipe Compression in Data Deduplication Systems}, booktitle={Proc. USENIX Conference on File and Storage Technologies (FAST)}, publisher={USENIX Association}, author={Meister, Dirk and Brinkmann, André and Süß, Tim}, year={2013}, pages={175–182} }","mla":"Meister, Dirk, et al. “File Recipe Compression in Data Deduplication Systems.” <i>Proc. USENIX Conference on File and Storage Technologies (FAST)</i>, USENIX Association, 2013, pp. 175–82.","short":"D. Meister, A. Brinkmann, T. Süß, in: Proc. USENIX Conference on File and Storage Technologies (FAST), USENIX Association, 2013, pp. 175–182.","apa":"Meister, D., Brinkmann, A., &#38; Süß, T. (2013). File Recipe Compression in Data Deduplication Systems. In <i>Proc. USENIX Conference on File and Storage Technologies (FAST)</i> (pp. 175–182). USENIX Association.","ieee":"D. Meister, A. Brinkmann, and T. Süß, “File Recipe Compression in Data Deduplication Systems,” in <i>Proc. USENIX Conference on File and Storage Technologies (FAST)</i>, 2013, pp. 175–182.","chicago":"Meister, Dirk, André Brinkmann, and Tim Süß. “File Recipe Compression in Data Deduplication Systems.” In <i>Proc. USENIX Conference on File and Storage Technologies (FAST)</i>, 175–82. USENIX Association, 2013.","ama":"Meister D, Brinkmann A, Süß T. File Recipe Compression in Data Deduplication Systems. In: <i>Proc. USENIX Conference on File and Storage Technologies (FAST)</i>. USENIX Association; 2013:175-182."},"page":"175-182","year":"2013"},{"status":"public","type":"mastersthesis","keyword":["coldboot"],"language":[{"iso":"ger"}],"_id":"521","project":[{"name":"SFB 901","_id":"1"},{"_id":"13","name":"SFB 901 - Subprojekt C1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"477","year":"2013","citation":{"ama":"Riebler H. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn; 2013.","ieee":"H. Riebler, <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013.","chicago":"Riebler, Heinrich. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013.","apa":"Riebler, H. (2013). <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn.","bibtex":"@book{Riebler_2013, title={Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs}, publisher={Universität Paderborn}, author={Riebler, Heinrich}, year={2013} }","mla":"Riebler, Heinrich. <i>Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs</i>. Universität Paderborn, 2013.","short":"H. Riebler, Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs, Universität Paderborn, 2013."},"title":"Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs","date_updated":"2022-01-06T07:01:46Z","publisher":"Universität Paderborn","author":[{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"}],"date_created":"2017-10-17T12:42:34Z"},{"quality_controlled":"1","has_accepted_license":"1","year":"2013","page":"386-389","citation":{"apa":"Riebler, H., Kenter, T., Sorge, C., &#38; Plessl, C. (2013). FPGA-accelerated Key Search for Cold-Boot Attacks against AES. <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–389. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>","mla":"Riebler, Heinrich, et al. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, IEEE, 2013, pp. 386–89, doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","bibtex":"@inproceedings{Riebler_Kenter_Sorge_Plessl_2013, title={FPGA-accelerated Key Search for Cold-Boot Attacks against AES}, DOI={<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Sorge, Christoph and Plessl, Christian}, year={2013}, pages={386–389} }","short":"H. Riebler, T. Kenter, C. Sorge, C. Plessl, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), IEEE, 2013, pp. 386–389.","chicago":"Riebler, Heinrich, Tobias Kenter, Christoph Sorge, and Christian Plessl. “FPGA-Accelerated Key Search for Cold-Boot Attacks against AES.” In <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 386–89. IEEE, 2013. <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">https://doi.org/10.1109/FPT.2013.6718394</a>.","ieee":"H. Riebler, T. Kenter, C. Sorge, and C. Plessl, “FPGA-accelerated Key Search for Cold-Boot Attacks against AES,” in <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>, 2013, pp. 386–389, doi: <a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>.","ama":"Riebler H, Kenter T, Sorge C, Plessl C. FPGA-accelerated Key Search for Cold-Boot Attacks against AES. In: <i>Proceedings of the International Conference on Field-Programmable Technology (FPT)</i>. IEEE; 2013:386-389. doi:<a href=\"https://doi.org/10.1109/FPT.2013.6718394\">10.1109/FPT.2013.6718394</a>"},"date_updated":"2023-09-26T13:37:35Z","publisher":"IEEE","author":[{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"}],"date_created":"2017-10-17T12:42:35Z","title":"FPGA-accelerated Key Search for Cold-Boot Attacks against AES","doi":"10.1109/FPT.2013.6718394","publication":"Proceedings of the International Conference on Field-Programmable Technology (FPT)","type":"conference","abstract":[{"text":"Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.","lang":"eng"}],"status":"public","file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":822680,"access_level":"closed","file_id":"1294","file_name":"528-plessl13_fpt.pdf","date_updated":"2018-03-15T10:36:08Z","creator":"florida","date_created":"2018-03-15T10:36:08Z"}],"_id":"528","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Subproject C1","_id":"13"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","keyword":["coldboot"],"ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-15T10:36:08Z"},{"ddc":["040"],"file_date_updated":"2018-03-15T13:38:56Z","language":[{"iso":"eng"}],"_id":"505","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"63"},{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","abstract":[{"text":"In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.","lang":"eng"}],"status":"public","file":[{"file_size":1040834,"access_level":"closed","file_id":"1308","file_name":"505-Plessl13_seus.pdf","date_updated":"2018-03-15T13:38:56Z","date_created":"2018-03-15T13:38:56Z","creator":"florida","success":1,"relation":"main_file","content_type":"application/pdf"}],"publication":"Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS)","type":"conference","title":"On-The-Fly Computing: A Novel Paradigm for Individualized IT Services","doi":"10.1109/ISORC.2013.6913232","publisher":"IEEE","date_updated":"2023-09-26T13:38:20Z","date_created":"2017-10-17T12:42:30Z","author":[{"last_name":"Happe","full_name":"Happe, Markus","first_name":"Markus"},{"full_name":"Kling, Peter","last_name":"Kling","first_name":"Peter"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"},{"first_name":"Friedhelm","last_name":"Meyer auf der Heide","id":"15523","full_name":"Meyer auf der Heide, Friedhelm"}],"year":"2013","citation":{"apa":"Happe, M., Kling, P., Plessl, C., Platzner, M., &#38; Meyer auf der Heide, F. (2013). On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>","short":"M. Happe, P. Kling, C. Plessl, M. Platzner, F. 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On-The-Fly Computing: A Novel Paradigm for Individualized IT Services. In: <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE; 2013. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">10.1109/ISORC.2013.6913232</a>","chicago":"Happe, Markus, Peter Kling, Christian Plessl, Marco Platzner, and Friedhelm Meyer auf der Heide. “On-The-Fly Computing: A Novel Paradigm for Individualized IT Services.” In <i>Proceedings of the 9th IEEE Workshop on Software Technology for Future Embedded and Ubiquitous Systems (SEUS)</i>. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913232\">https://doi.org/10.1109/ISORC.2013.6913232</a>.","ieee":"M. Happe, P. Kling, C. Plessl, M. Platzner, and F. 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