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PoS(EGICF12-EMITC2)050.","chicago":"Gesing, Sandra, Sonja Herres-Pawlis, Georg Birkenheuer, André Brinkmann, Richard Grunzke, Peter Kacsuk, Oliver Kohlbacher, et al. “A Science Gateway Getting Ready for Serving the International Molecular Simulation Community.” In <i>Proceedings of Science</i>, Vol. PoS(EGICF12-EMITC2)050, 2012."},"year":"2012","title":"A Science Gateway Getting Ready for Serving the International Molecular Simulation Community","volume":"PoS(EGICF12-EMITC2)050","author":[{"full_name":"Gesing, Sandra","last_name":"Gesing","first_name":"Sandra"},{"first_name":"Sonja","last_name":"Herres-Pawlis","full_name":"Herres-Pawlis, Sonja"},{"full_name":"Birkenheuer, Georg","last_name":"Birkenheuer","first_name":"Georg"},{"full_name":"Brinkmann, André","last_name":"Brinkmann","first_name":"André"},{"full_name":"Grunzke, Richard","last_name":"Grunzke","first_name":"Richard"},{"first_name":"Peter","full_name":"Kacsuk, Peter","last_name":"Kacsuk"},{"last_name":"Kohlbacher","full_name":"Kohlbacher, Oliver","first_name":"Oliver"},{"full_name":"Kozlovszky, Miklos","last_name":"Kozlovszky","first_name":"Miklos"},{"last_name":"Krüger","full_name":"Krüger, Jens","first_name":"Jens"},{"full_name":"Müller-Pfefferkorn, Ralph","last_name":"Müller-Pfefferkorn","first_name":"Ralph"},{"first_name":"Patrick","full_name":"Schäfer, Patrick","last_name":"Schäfer"},{"first_name":"Thomas","last_name":"Steinke","full_name":"Steinke, Thomas"}],"date_created":"2018-04-03T09:15:35Z","date_updated":"2022-01-06T06:55:13Z","status":"public","publication":"Proceedings of Science","type":"conference","department":[{"_id":"27"}],"user_id":"24135","_id":"2178"},{"title":"Programming models for reconfigurable heterogeneous multi-cores","publisher":"Awareness Magazine","date_updated":"2022-01-06T07:02:44Z","author":[{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Enno","full_name":"Lübbers, Enno","last_name":"Lübbers"}],"date_created":"2017-10-17T12:42:46Z","year":"2012","citation":{"chicago":"Plessl, Christian, Marco Platzner, Andreas Agne, Markus Happe, and Enno Lübbers. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","ieee":"C. Plessl, M. Platzner, A. Agne, M. Happe, and E. Lübbers, <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine, 2012.","ama":"Plessl C, Platzner M, Agne A, Happe M, Lübbers E. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine; 2012.","apa":"Plessl, C., Platzner, M., Agne, A., Happe, M., &#38; Lübbers, E. (2012). <i>Programming models for reconfigurable heterogeneous multi-cores</i>. Awareness Magazine.","mla":"Plessl, Christian, et al. <i>Programming Models for Reconfigurable Heterogeneous Multi-Cores</i>. Awareness Magazine, 2012.","bibtex":"@book{Plessl_Platzner_Agne_Happe_Lübbers_2012, title={Programming models for reconfigurable heterogeneous multi-cores}, publisher={Awareness Magazine}, author={Plessl, Christian and Platzner, Marco and Agne, Andreas and Happe, Markus and Lübbers, Enno}, year={2012} }","short":"C. Plessl, M. Platzner, A. Agne, M. Happe, E. Lübbers, Programming Models for Reconfigurable Heterogeneous Multi-Cores, Awareness Magazine, 2012."},"has_accepted_license":"1","ddc":["040"],"file_date_updated":"2018-03-15T08:37:02Z","language":[{"iso":"eng"}],"_id":"587","project":[{"name":"SFB 901","_id":"1"},{"_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"398","status":"public","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-15T08:37:02Z","date_created":"2018-03-15T08:37:02Z","creator":"florida","file_size":353057,"access_level":"closed","file_id":"1260","file_name":"587-2012_plessl_awareness_magazine.pdf"}],"type":"misc"},{"type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"user_id":"15278","_id":"2106","file_date_updated":"2019-02-13T09:04:46Z","has_accepted_license":"1","page":"189-196","citation":{"ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>"},"author":[{"last_name":"Meyer","full_name":"Meyer, Björn","first_name":"Björn"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862"}],"date_updated":"2023-09-26T13:39:13Z","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"file_size":2148787,"file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","file_id":"7638","access_level":"closed","date_updated":"2019-02-13T09:04:46Z","date_created":"2019-02-13T09:04:46Z","creator":"fossie","success":1,"relation":"main_file","content_type":"application/pdf"}],"abstract":[{"lang":"eng","text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view."}],"language":[{"iso":"eng"}],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"ddc":["000"],"quality_controlled":"1","year":"2012","date_created":"2018-03-29T15:04:25Z","publisher":"IEEE","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","doi":"10.1016/j.micpro.2011.04.002","date_updated":"2023-09-26T13:39:30Z","volume":36,"author":[{"last_name":"Schumacher","full_name":"Schumacher, Tobias","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_created":"2018-03-29T15:12:38Z","year":"2012","intvolume":"        36","page":"110-126","citation":{"ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>"},"publication_identifier":{"issn":["0141-9331"]},"quality_controlled":"1","issue":"2","keyword":["funding-altera"],"language":[{"iso":"eng"}],"_id":"2108","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","publication":"Microprocessors and Microsystems","type":"journal_article"},{"file_date_updated":"2018-03-15T06:48:32Z","_id":"615","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","type":"conference","doi":"10.1109/ReConFig.2012.6416745","date_updated":"2023-09-26T13:42:26Z","author":[{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"first_name":"Hendrik","last_name":"Hangmann","full_name":"Hangmann, Hendrik"},{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"}],"page":"1-8","citation":{"apa":"Happe, M., Hangmann, H., Agne, A., &#38; Plessl, C. (2012). Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>","mla":"Happe, Markus, et al. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>.","bibtex":"@inproceedings{Happe_Hangmann_Agne_Plessl_2012, title={Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>}, booktitle={Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Happe, Markus and Hangmann, Hendrik and Agne, Andreas and Plessl, Christian}, year={2012}, pages={1–8} }","short":"M. Happe, H. Hangmann, A. Agne, C. Plessl, in: Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","ama":"Happe M, Hangmann H, Agne A, Plessl C. Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators. In: <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>","chicago":"Happe, Markus, Hendrik Hangmann, Andreas Agne, and Christian Plessl. “Eight Ways to Put Your FPGA on Fire – A Systematic Study of Heat Generators.” In <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">https://doi.org/10.1109/ReConFig.2012.6416745</a>.","ieee":"M. Happe, H. Hangmann, A. Agne, and C. Plessl, “Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators,” in <i>Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416745\">10.1109/ReConFig.2012.6416745</a>."},"has_accepted_license":"1","ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, the accuracy of the simulations is to some extent questionable and they require a high computational effort if a detailed thermal model is used.For experimental evaluation of real-world temperature management methods, often synthetic heat sources are employed. Therefore, in this paper we investigated the question if we can create significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments in contrast to simulations. Therefore, we have developed eight different heat-generating cores that use different subsets of the FPGA resources. Our experimental results show that, according to the built-in thermal diode of our Xilinx Virtex-5 FPGA, we can increase the chip temperature by 134 degree C in less than 12 minutes by only utilizing about 21% of the slices.","lang":"eng"}],"file":[{"creator":"florida","date_created":"2018-03-15T06:48:32Z","date_updated":"2018-03-15T06:48:32Z","access_level":"closed","file_name":"615-ReConFig12_01.pdf","file_id":"1246","file_size":730144,"content_type":"application/pdf","relation":"main_file","success":1}],"publication":"Proceedings of the International Conference on Reconfigurable Computing and FPGAs (ReConFig)","title":"Eight Ways to put your FPGA on Fire – A Systematic Study of Heat Generators","publisher":"IEEE","date_created":"2017-10-17T12:42:51Z","year":"2012","quality_controlled":"1"},{"quality_controlled":"1","year":"2012","date_created":"2017-10-17T12:42:47Z","publisher":"IEEE","title":"Pragma based parallelization - Trading hardware efficiency for ease of use?","publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","file":[{"date_updated":"2018-03-15T08:33:18Z","creator":"florida","date_created":"2018-03-15T08:33:18Z","file_size":371235,"file_name":"591-ReConFig2012Kenter_Schmitz_Plessl.pdf","access_level":"closed","file_id":"1257","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"One major obstacle for a wide spread FPGA usage in general-purpose computing is the development tool flow that requires much higher effort than for pure software solutions. Convey Computer promises a solution to this problem for their HC-1 platform, where the FPGAs are configured to run as a vector processor and the software source code can be annotated with pragmas that guide an automated vectorization process. We investigate this approach for a stereo matching algorithm that has abundant parallelism and a number of different computational patterns. We note that for this case study the automated vectorization in its current state doesn’t hold its productivity promise. However, we also show that using the Vector Personality can yield a significant speedups compared to CPU implementations in two of three investigated phases of the algorithm. Those speedups don’t match custom FPGA implementations, but can come with much reduced development effort.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["040"],"has_accepted_license":"1","citation":{"short":"T. Kenter, C. Plessl, H. Schmitz, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2012, pp. 1–8.","bibtex":"@inproceedings{Kenter_Plessl_Schmitz_2012, title={Pragma based parallelization - Trading hardware efficiency for ease of use?}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Plessl, Christian and Schmitz, Henning}, year={2012}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2012, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","apa":"Kenter, T., Plessl, C., &#38; Schmitz, H. (2012). Pragma based parallelization - Trading hardware efficiency for ease of use? <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>","chicago":"Kenter, Tobias, Christian Plessl, and Henning Schmitz. “Pragma Based Parallelization - Trading Hardware Efficiency for Ease of Use?” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2012. <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">https://doi.org/10.1109/ReConFig.2012.6416773</a>.","ieee":"T. Kenter, C. Plessl, and H. Schmitz, “Pragma based parallelization - Trading hardware efficiency for ease of use?,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2012, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>.","ama":"Kenter T, Plessl C, Schmitz H. Pragma based parallelization - Trading hardware efficiency for ease of use? In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2012:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2012.6416773\">10.1109/ReConFig.2012.6416773</a>"},"page":"1-8","author":[{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Henning","full_name":"Schmitz, Henning","last_name":"Schmitz"}],"date_updated":"2023-09-26T13:41:08Z","doi":"10.1109/ReConFig.2012.6416773","type":"conference","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"_id":"591","file_date_updated":"2018-03-15T08:33:18Z"},{"year":"2012","citation":{"mla":"Happe, Markus, et al. “Hardware/Software Platform for Self-Aware Compute Nodes.” <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","bibtex":"@inproceedings{Happe_Agne_Plessl_Platzner_2012, title={Hardware/Software Platform for Self-aware Compute Nodes}, booktitle={Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)}, author={Happe, Markus and Agne, Andreas and Plessl, Christian and Platzner, Marco}, year={2012}, pages={8–9} }","short":"M. Happe, A. Agne, C. Plessl, M. Platzner, in: Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS), 2012, pp. 8–9.","apa":"Happe, M., Agne, A., Plessl, C., &#38; Platzner, M. (2012). Hardware/Software Platform for Self-aware Compute Nodes. <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9.","ama":"Happe M, Agne A, Plessl C, Platzner M. Hardware/Software Platform for Self-aware Compute Nodes. In: <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>. ; 2012:8-9.","ieee":"M. Happe, A. Agne, C. Plessl, and M. Platzner, “Hardware/Software Platform for Self-aware Compute Nodes,” in <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 2012, pp. 8–9.","chicago":"Happe, Markus, Andreas Agne, Christian Plessl, and Marco Platzner. “Hardware/Software Platform for Self-Aware Compute Nodes.” In <i>Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)</i>, 8–9, 2012."},"page":"8-9","quality_controlled":"1","has_accepted_license":"1","title":"Hardware/Software Platform for Self-aware Compute Nodes","date_updated":"2023-09-26T13:41:36Z","date_created":"2017-10-17T12:42:50Z","author":[{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"last_name":"Agne","full_name":"Agne, Andreas","first_name":"Andreas"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Marco","last_name":"Platzner","id":"398","full_name":"Platzner, Marco"}],"abstract":[{"lang":"eng","text":"Today's design and operation principles and methods do not scale well with future reconfigurable computing systems due to an increased complexity in system architectures and applications, run-time dynamics and corresponding requirements. Hence, novel design and operation principles and methods are needed that possibly break drastically with the static ones we have built into our systems and the fixed abstraction layers we have cherished over the last decades. Thus, we propose a HW/SW platform that collects and maintains information about its state and progress which enables the system to reason about its behavior (self-awareness) and utilizes its knowledge to effectively and autonomously adapt its behavior to changing requirements (self-expression).To enable self-awareness, our compute nodes collect information using a variety of sensors, i.e. performance counters and thermal diodes, and use internal self-awareness models that process these information. For self-awareness, on-line learning is crucial such that the node learns and continuously updates its models at run-time to react to changing conditions. To enable self-expression, we break with the classic design-time abstraction layers of hardware, operating system and software. In contrast, our system is able to vertically migrate functionalities between the layers at run-time to exploit trade-offs between abstraction and optimization.This paper presents a heterogeneous multi-core architecture, that enables self-awareness and self-expression, an operating system for our proposed hardware/software platform and a novel self-expression method."}],"file":[{"file_size":146789,"file_id":"1249","access_level":"closed","file_name":"609-happe12_fpl_awareness.pdf","date_updated":"2018-03-15T08:14:17Z","creator":"florida","date_created":"2018-03-15T08:14:17Z","success":1,"relation":"main_file","content_type":"application/pdf"}],"status":"public","type":"conference","publication":"Proceedings of the Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS)","ddc":["040"],"file_date_updated":"2018-03-15T08:14:17Z","language":[{"iso":"eng"}],"project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"31","name":"Engineering Proprioception in Computing Systems","grant_number":"257906"}],"_id":"609","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}]},{"title":"Turning control flow graphs into function calls: Code generation for heterogeneous architectures","date_created":"2017-10-17T12:42:42Z","publisher":"IEEE","year":"2012","quality_controlled":"1","language":[{"iso":"eng"}],"ddc":["040"],"file":[{"date_updated":"2018-03-15T10:20:24Z","creator":"florida","date_created":"2018-03-15T10:20:24Z","file_size":288508,"file_id":"1275","file_name":"567-ba-ca-12a.pdf","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"Heterogeneous machines are gaining momentum in the High Performance Computing field, due to the theoretical speedups and power consumption. In practice, while some applications meet the performance expectations, heterogeneous architectures still require a tremendous effort from the application developers. This work presents a code generation method to port codes into heterogeneous platforms, based on transformations of the control flow into function calls. The results show that the cost of the function-call mechanism is affordable for the tested HPC kernels. The complete toolchain, based on the LLVM compiler infrastructure, is fully automated once the sequential specification is provided.","lang":"eng"}],"publication":"Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)","doi":"10.1109/HPCSim.2012.6266973","author":[{"full_name":"Barrio, Pablo","last_name":"Barrio","first_name":"Pablo"},{"first_name":"Carlos","full_name":"Carreras, Carlos","last_name":"Carreras"},{"first_name":"Roberto","full_name":"Sierra, Roberto","last_name":"Sierra"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"date_updated":"2023-09-26T13:42:54Z","page":"559-565","citation":{"ama":"Barrio P, Carreras C, Sierra R, Kenter T, Plessl C. Turning control flow graphs into function calls: Code generation for heterogeneous architectures. In: <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>. IEEE; 2012:559-565. doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>","ieee":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, and C. Plessl, “Turning control flow graphs into function calls: Code generation for heterogeneous architectures,” in <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 2012, pp. 559–565, doi: <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","chicago":"Barrio, Pablo, Carlos Carreras, Roberto Sierra, Tobias Kenter, and Christian Plessl. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” In <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–65. IEEE, 2012. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>.","short":"P. Barrio, C. Carreras, R. Sierra, T. Kenter, C. Plessl, in: Proceedings of the International Conference on High Performance Computing and Simulation (HPCS), IEEE, 2012, pp. 559–565.","bibtex":"@inproceedings{Barrio_Carreras_Sierra_Kenter_Plessl_2012, title={Turning control flow graphs into function calls: Code generation for heterogeneous architectures}, DOI={<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>}, booktitle={Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)}, publisher={IEEE}, author={Barrio, Pablo and Carreras, Carlos and Sierra, Roberto and Kenter, Tobias and Plessl, Christian}, year={2012}, pages={559–565} }","mla":"Barrio, Pablo, et al. “Turning Control Flow Graphs into Function Calls: Code Generation for Heterogeneous Architectures.” <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, IEEE, 2012, pp. 559–65, doi:<a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">10.1109/HPCSim.2012.6266973</a>.","apa":"Barrio, P., Carreras, C., Sierra, R., Kenter, T., &#38; Plessl, C. (2012). Turning control flow graphs into function calls: Code generation for heterogeneous architectures. <i>Proceedings of the International Conference on High Performance Computing and Simulation (HPCS)</i>, 559–565. <a href=\"https://doi.org/10.1109/HPCSim.2012.6266973\">https://doi.org/10.1109/HPCSim.2012.6266973</a>"},"has_accepted_license":"1","file_date_updated":"2018-03-15T10:20:24Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"567","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"}],"status":"public","type":"conference"},{"year":"2012","page":"559-562","citation":{"ama":"Rüthing C, Happe M, Agne A, Plessl C. Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. In: <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:559-562. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"C. Rüthing, M. Happe, A. Agne, and C. Plessl, “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs,” in <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 559–562, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Rüthing, Christoph, Markus Happe, Andreas Agne, and Christian Plessl. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” In <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–62. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>.","apa":"Rüthing, C., Happe, M., Agne, A., &#38; Plessl, C. (2012). Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs. <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, 559–562. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","mla":"Rüthing, Christoph, et al. “Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs.” <i>Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 559–62, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","short":"C. Rüthing, M. Happe, A. Agne, C. Plessl, in: Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 559–562.","bibtex":"@inproceedings{Rüthing_Happe_Agne_Plessl_2012, title={Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Rüthing, Christoph and Happe, Markus and Agne, Andreas and Plessl, Christian}, year={2012}, pages={559–562} }"},"quality_controlled":"1","has_accepted_license":"1","title":"Exploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs","doi":"10.1109/FPL.2012.6339370","publisher":"IEEE","date_updated":"2023-09-26T13:42:03Z","author":[{"first_name":"Christoph","last_name":"Rüthing","full_name":"Rüthing, Christoph"},{"first_name":"Markus","full_name":"Happe, Markus","last_name":"Happe"},{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"date_created":"2017-10-17T12:42:51Z","abstract":[{"lang":"eng","text":"While numerous publications have presented ring oscillator designs for temperature measurements a detailed study of the ring oscillator's design space is still missing. In this work, we introduce metrics for comparing the performance and area efficiency of ring oscillators and a methodology for determining these metrics. As a result, we present a systematic study of the design space for ring oscillators for a Xilinx Virtex-5 platform FPGA."}],"status":"public","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","access_level":"closed","file_name":"612-ruething_fpl12.pdf","file_id":"1247","file_size":202923,"creator":"florida","date_created":"2018-03-15T06:49:03Z","date_updated":"2018-03-15T06:49:03Z"}],"publication":"Proceedings of the International Conference on Field Programmable Logic and Applications (FPL)","type":"conference","ddc":["040"],"file_date_updated":"2018-03-15T06:49:03Z","language":[{"iso":"eng"}],"_id":"612","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - Subprojekt C2","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278"},{"language":[{"iso":"eng"}],"keyword":["funding-enhance"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2180","project":[{"grant_number":"01|H11004A","_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models"}],"status":"public","publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)","type":"conference","title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","author":[{"last_name":"Beisel","full_name":"Beisel, Tobias","first_name":"Tobias"},{"id":"3118","full_name":"Wiersema, Tobias","last_name":"Wiersema","first_name":"Tobias"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"full_name":"Brinkmann, André","last_name":"Brinkmann","first_name":"André"}],"date_created":"2018-04-03T09:18:33Z","date_updated":"2023-09-26T13:40:17Z","citation":{"ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012."},"year":"2012","quality_controlled":"1"},{"_id":"2177","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"language":[{"iso":"eng"}],"type":"journal_article","publication":"Int. Journal of Reconfigurable Computing (IJRC)","status":"public","publisher":"Hindawi Publishing Corp.","date_updated":"2023-09-26T13:39:48Z","author":[{"first_name":"Mariusz","last_name":"Grad","full_name":"Grad, Mariusz"},{"orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_created":"2018-04-03T09:13:22Z","title":"On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors","doi":"10.1155/2012/418315","quality_controlled":"1","year":"2012","citation":{"ieee":"M. Grad and C. Plessl, “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors,” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012, doi: <a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>.","chicago":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, 2012. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>.","ama":"Grad M, Plessl C. On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int Journal of Reconfigurable Computing (IJRC)</i>. Published online 2012. doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>","apa":"Grad, M., &#38; Plessl, C. (2012). On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors. <i>Int. Journal of Reconfigurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2012/418315\">https://doi.org/10.1155/2012/418315</a>","short":"M. Grad, C. Plessl, Int. Journal of Reconfigurable Computing (IJRC) (2012).","bibtex":"@article{Grad_Plessl_2012, title={On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-based Reconfigurable Processors}, DOI={<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>}, journal={Int. Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Grad, Mariusz and Plessl, Christian}, year={2012} }","mla":"Grad, Mariusz, and Christian Plessl. “On the Feasibility and Limitations of Just-In-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors.” <i>Int. Journal of Reconfigurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2012, doi:<a href=\"https://doi.org/10.1155/2012/418315\">10.1155/2012/418315</a>."}},{"department":[{"_id":"15"},{"_id":"170"},{"_id":"295"},{"_id":"35"},{"_id":"230"},{"_id":"27"}],"user_id":"16199","_id":"13546","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"language":[{"iso":"eng"}],"publication":"Physical Review B","type":"journal_article","status":"public","volume":85,"date_created":"2019-09-30T14:53:08Z","author":[{"last_name":"Riefer","full_name":"Riefer, A.","first_name":"A."},{"first_name":"E.","full_name":"Rauls, E.","last_name":"Rauls"},{"full_name":"Schmidt, Wolf Gero","id":"468","orcid":"0000-0002-2717-5076","last_name":"Schmidt","first_name":"Wolf Gero"},{"last_name":"Eberhard","full_name":"Eberhard, J.","first_name":"J."},{"full_name":"Stoll, I.","last_name":"Stoll","first_name":"I."},{"full_name":"Mattay, J.","last_name":"Mattay","first_name":"J."}],"date_updated":"2025-12-05T10:45:11Z","doi":"10.1103/physrevb.85.165202","title":"2-Aminopyrimidine-silver(I) based organic semiconductors: Electronic structure and optical response","issue":"16","publication_identifier":{"issn":["1098-0121","1550-235X"]},"publication_status":"published","intvolume":"        85","citation":{"bibtex":"@article{Riefer_Rauls_Schmidt_Eberhard_Stoll_Mattay_2012, title={2-Aminopyrimidine-silver(I) based organic semiconductors: Electronic structure and optical response}, volume={85}, DOI={<a href=\"https://doi.org/10.1103/physrevb.85.165202\">10.1103/physrevb.85.165202</a>}, number={16}, journal={Physical Review B}, author={Riefer, A. and Rauls, E. and Schmidt, Wolf Gero and Eberhard, J. and Stoll, I. and Mattay, J.}, year={2012} }","mla":"Riefer, A., et al. “2-Aminopyrimidine-Silver(I) Based Organic Semiconductors: Electronic Structure and Optical Response.” <i>Physical Review B</i>, vol. 85, no. 16, 2012, doi:<a href=\"https://doi.org/10.1103/physrevb.85.165202\">10.1103/physrevb.85.165202</a>.","short":"A. Riefer, E. Rauls, W.G. Schmidt, J. Eberhard, I. Stoll, J. Mattay, Physical Review B 85 (2012).","apa":"Riefer, A., Rauls, E., Schmidt, W. G., Eberhard, J., Stoll, I., &#38; Mattay, J. (2012). 2-Aminopyrimidine-silver(I) based organic semiconductors: Electronic structure and optical response. <i>Physical Review B</i>, <i>85</i>(16). <a href=\"https://doi.org/10.1103/physrevb.85.165202\">https://doi.org/10.1103/physrevb.85.165202</a>","ama":"Riefer A, Rauls E, Schmidt WG, Eberhard J, Stoll I, Mattay J. 2-Aminopyrimidine-silver(I) based organic semiconductors: Electronic structure and optical response. <i>Physical Review B</i>. 2012;85(16). doi:<a href=\"https://doi.org/10.1103/physrevb.85.165202\">10.1103/physrevb.85.165202</a>","chicago":"Riefer, A., E. Rauls, Wolf Gero Schmidt, J. Eberhard, I. Stoll, and J. Mattay. “2-Aminopyrimidine-Silver(I) Based Organic Semiconductors: Electronic Structure and Optical Response.” <i>Physical Review B</i> 85, no. 16 (2012). <a href=\"https://doi.org/10.1103/physrevb.85.165202\">https://doi.org/10.1103/physrevb.85.165202</a>.","ieee":"A. Riefer, E. Rauls, W. G. Schmidt, J. Eberhard, I. Stoll, and J. Mattay, “2-Aminopyrimidine-silver(I) based organic semiconductors: Electronic structure and optical response,” <i>Physical Review B</i>, vol. 85, no. 16, 2012, doi: <a href=\"https://doi.org/10.1103/physrevb.85.165202\">10.1103/physrevb.85.165202</a>."},"year":"2012"},{"_id":"13545","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"department":[{"_id":"15"},{"_id":"170"},{"_id":"295"},{"_id":"35"},{"_id":"230"},{"_id":"27"}],"user_id":"16199","article_number":"195503","language":[{"iso":"eng"}],"publication":"Journal of Physics: Condensed Matter","type":"journal_article","status":"public","date_updated":"2025-12-05T10:45:31Z","volume":24,"author":[{"full_name":"Landmann, M","last_name":"Landmann","first_name":"M"},{"last_name":"Rauls","full_name":"Rauls, E","first_name":"E"},{"first_name":"Wolf Gero","orcid":"0000-0002-2717-5076","last_name":"Schmidt","full_name":"Schmidt, Wolf Gero","id":"468"}],"date_created":"2019-09-30T14:51:40Z","title":"The electronic structure and optical response of rutile, anatase and brookite TiO2","doi":"10.1088/0953-8984/24/19/195503","publication_identifier":{"issn":["0953-8984","1361-648X"]},"publication_status":"published","year":"2012","intvolume":"        24","citation":{"ieee":"M. Landmann, E. Rauls, and W. G. Schmidt, “The electronic structure and optical response of rutile, anatase and brookite TiO2,” <i>Journal of Physics: Condensed Matter</i>, vol. 24, Art. no. 195503, 2012, doi: <a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">10.1088/0953-8984/24/19/195503</a>.","chicago":"Landmann, M, E Rauls, and Wolf Gero Schmidt. “The Electronic Structure and Optical Response of Rutile, Anatase and Brookite TiO2.” <i>Journal of Physics: Condensed Matter</i> 24 (2012). <a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">https://doi.org/10.1088/0953-8984/24/19/195503</a>.","ama":"Landmann M, Rauls E, Schmidt WG. The electronic structure and optical response of rutile, anatase and brookite TiO2. <i>Journal of Physics: Condensed Matter</i>. 2012;24. doi:<a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">10.1088/0953-8984/24/19/195503</a>","apa":"Landmann, M., Rauls, E., &#38; Schmidt, W. G. (2012). The electronic structure and optical response of rutile, anatase and brookite TiO2. <i>Journal of Physics: Condensed Matter</i>, <i>24</i>, Article 195503. <a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">https://doi.org/10.1088/0953-8984/24/19/195503</a>","short":"M. Landmann, E. Rauls, W.G. Schmidt, Journal of Physics: Condensed Matter 24 (2012).","mla":"Landmann, M., et al. “The Electronic Structure and Optical Response of Rutile, Anatase and Brookite TiO2.” <i>Journal of Physics: Condensed Matter</i>, vol. 24, 195503, 2012, doi:<a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">10.1088/0953-8984/24/19/195503</a>.","bibtex":"@article{Landmann_Rauls_Schmidt_2012, title={The electronic structure and optical response of rutile, anatase and brookite TiO2}, volume={24}, DOI={<a href=\"https://doi.org/10.1088/0953-8984/24/19/195503\">10.1088/0953-8984/24/19/195503</a>}, number={195503}, journal={Journal of Physics: Condensed Matter}, author={Landmann, M and Rauls, E and Schmidt, Wolf Gero}, year={2012} }"}}]