How irreversible are steady-state trajectories of a trapped active particle? - Dabelow, Lennart; Bo, Stefano; Eichhorn, Ralf (Journal of Statistical Mechanics: Theory and Experiment)
Abstract The defining feature of active particles is that they constantly propel themselves by locally converting chemical energy into directed motion. This active self-propulsion prevents them from equilibrating with their thermal environment (e.g. an aqueous solution), thus keeping them permanently out of equilibrium. Nevertheless, the spatial dynamics of active particles might share certain equilibrium features, in particular in the steady state. We here focus on the time-reversal symmetry of individual spatial trajectories as a distinct equilibrium characteristic. We investigate to what extent the steady-state trajectories of a trapped active particle obey or break this time-reversal symmetry. Within the framework of active Ornstein–Uhlenbeck particles we find that the steady-state trajectories in a harmonic potential fulfill path-wise time-reversal symmetry exactly, while this symmetry is typically broken in anharmonic potentials.
Keywords: Statistics; Probability and Uncertainty; Statistics and Probability; Statistical and Nonlinear Physics

Towards Electronic Structure-Based Ab-Initio Molecular Dynamics Simulations with Hundreds of Millions of Atoms - Schade, Robert; Kenter, Tobias; Elgabarty, Hossam; Lass, Michael; Schütt, Ole; Lazzaro, Alfio; Pabst, Hans; Mohr, Stephan; Hutter, Jürg; Kühne, Thomas D.; Plessl, Christian (arXiv:2104.08245)
We push the boundaries of electronic structure-based ab-initio molecular dynamics (AIMD) beyond 100 million atoms. This scale is otherwise barely reachable with classical force-field methods or novel neural network and machine learning potentials. We achieve this breakthrough by combining innovations in linear-scaling AIMD, efficient and approximate sparse linear algebra, low and mixed-precision floating-point computation on GPUs, and a compensation scheme for the errors introduced by numerical approximations. The core of our work is the non-orthogonalized local submatrix method (NOLSM), which scales very favorably to massively parallel computing systems and translates large sparse matrix operations into highly parallel, dense matrix operations that are ideally suited to hardware accelerators. We demonstrate that the NOLSM method, which is at the center point of each AIMD step, is able to achieve a sustained performance of 324 PFLOP/s in mixed FP16/FP32 precision corresponding to an efficiency of 67.7% when running on 1536 NVIDIA A100 GPUs.

Optimization of optical waveguide antennas for directive emission of light - Farheen, Henna; Leuteritz, Till; Linden, Stefan; Myroshnychenko, Viktor; Förstner, Jens (arXiv:2106.02468)
Optical travelling wave antennas offer unique opportunities to control and selectively guide light into a specific direction which renders them as excellent candidates for optical communication and sensing. These applications require state of the art engineering to reach optimized functionalities such as high directivity and radiation efficiency, low side lobe level, broadband and tunable capabilities, and compact design. In this work we report on the numerical optimization of the directivity of optical travelling wave antennas made from low-loss dielectric materials using full-wave numerical simulations in conjunction with a particle swarm optimization algorithm. The antennas are composed of a reflector and a director deposited on a glass substrate and an emitter placed in the feed gap between them serves as an internal source of excitation. In particular, we analysed antennas with rectangular- and horn-shaped directors made of either Hafnium dioxide or Silicon. The optimized antennas produce highly directional emission due to the presence of two dominant guided TE modes in the director in addition to leaky modes. These guided modes dominate the far-field emission pattern and govern the direction of the main lobe emission which predominately originates from the end facet of the director. Our work also provides a comprehensive analysis of the modes, radiation patterns, parametric influences, and bandwidths of the antennas that highlights their robust nature.

Steady states of $Λ$-type three-level systems excited by quantum light in lossy cavities - Rose, H.; Tikhonova, O. V.; Meier, T.; Sharapova, P. (arXiv:2109.00842)
The interaction between quantum light and matter is being intensively studied for systems that are enclosed in high-$Q$ cavities which strongly enhance the light-matter coupling. However, for many applications, cavities with lower $Q$-factors are preferred due to the increased spectral width of the cavity mode. Here, we investigate the interaction between quantum light and matter represented by a $Λ$-type three-level system in lossy cavities, assuming that cavity losses are the dominant loss mechanism. We demonstrate that cavity losses lead to non-trivial steady states of the electronic occupations that can be controlled by the loss rate and the initial statistics of the quantum fields. The mechanism of formation of such steady states can be understood on the basis of the equations of motion. Analytical expressions for steady states and their numerical simulations are presented and discussed.

Eigenvalue spectra of QCD and the fate of UA(1) breaking towards the chiral limit - Kaczmarek, Olaf; Mazur, Lukas; Sharma, Sayantan (Physical Review D)

Heavy quark momentum diffusion from the lattice using gradient flow - Altenkort, Luis; Eller, Alexander M.; Kaczmarek, O.; Mazur, Lukas; Moore, Guy D.; Shu, H.-T. (Physical Review D)

Sphaleron rate from Euclidean lattice correlators: An exploration - Altenkort, Luis; Eller, Alexander M.; Kaczmarek, O.; Mazur, Lukas; Moore, Guy D.; Shu, H.-T. (Physical Review D)

High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection - Karp, Martin; Podobas, Artur; Jansson, Niclas; Kenter, Tobias; Plessl, Christian; Schlatter, Philipp; Markidis, Stefano (2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS))

HighPerMeshes – A Domain-Specific Language for Numerical Algorithms on Unstructured Grids - Alhaddad, Samer; Förstner, Jens; Groth, Stefan; Grünewald, Daniel; Grynko, Yevgen; Hannig, Frank; Kenter, Tobias; Pfreundt, Franz-Josef; Plessl, Christian; Schotte, Merlind; Steinke, Thomas; Teich, Jürgen; et al. (Euro-Par 2020: Parallel Processing Workshops)
Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPerMeshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters, is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster.
Keywords: tet_topic_hpc

Evaluating the Design Space for Offloading 3D FFT Calculations to an FPGA for High-Performance Computing - Ramaswami, Arjun; Kenter, Tobias; Kühne, Thomas; Plessl, Christian (Applied Reconfigurable Computing. Architectures, Tools, and Applications)

The HighPerMeshes framework for numerical algorithms on unstructured grids - Alhaddad, Samer; Förstner, Jens; Groth, Stefan; Grünewald, Daniel; Grynko, Yevgen; Hannig, Frank; Kenter, Tobias; Pfreundt, Franz‐Josef; Plessl, Christian; Schotte, Merlind; Steinke, Thomas; Teich, Jürgen; et al. (Concurrency and Computation: Practice and Experience)
Keywords: tet_topic_hpc

Diffusion of the carbon dioxide–ethanol mixture in the extended critical region - Chatwell, René Spencer; Guevara-Carrion, Gabriela; Gaponenko, Yuri; Shevtsova, Valentina; Vrabec, Jadran (Physical Chemistry Chemical Physics)
The effect of traces of ethanol in supercritical carbon dioxide on the mixture's thermodynamic properties is studied by molecular simulations and Taylor dispersion measurements.
Keywords: Physical and Theoretical Chemistry; General Physics and Astronomy

High-Performance Spectral Element Methods on Field-Programmable Gate Arrays : Implementation, Evaluation, and Future Projection - Karp, Martin; Podobas, Artur; Jansson, Niclas; Kenter, Tobias; Plessl, Christian; Schlatter, Philipp; Markidis, Stefano (2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS))

Algorithm-hardware co-design of a discontinuous Galerkin shallow-water model for a dataflow architecture on FPGA - Kenter, Tobias; Shambhu, Adesh; Faghih-Naini, Sara; Aizinger, Vadym (Proceedings of the Platform for Advanced Scientific Computing Conference (PASC))

Opportunities of 3D Machine Learning for Manufacturability Analysis and Component Recognition in the Additive Manufacturing Process Chain - Nickchen, Tobias; Engels, Gregor; Lohn, Johannes (Industrializing Additive Manufacturing)

In silico investigation of Cu(In,Ga)Se2-based solar cells - Mirhosseini, Hossein; Kormath Madam Raghupathy, Ramya; Sahoo, Sudhir K.; Wiebeler, Hendrik; Chugh, Manjusha; Kühne, Thomas D. (Physical Chemistry Chemical Physics)
State-of-the-art methods in materials science such as artificial intelligence and data-driven techniques advance the investigation of photovoltaic materials.
Keywords: Physical and Theoretical Chemistry; General Physics and Astronomy

Multi-Armed Bandits with Censored Consumption of Resources - Bengs, Viktor; Hüllermeier, Eyke (arXiv:2011.00813)
We consider a resource-aware variant of the classical multi-armed bandit problem: In each round, the learner selects an arm and determines a resource limit. It then observes a corresponding (random) reward, provided the (random) amount of consumed resources remains below the limit. Otherwise, the observation is censored, i.e., no reward is obtained. For this problem setting, we introduce a measure of regret, which incorporates the actual amount of allocated resources of each learning round as well as the optimality of realizable rewards. Thus, to minimize regret, the learner needs to set a resource limit and choose an arm in such a way that the chance to realize a high reward within the predefined resource limit is high, while the resource limit itself should be kept as low as possible. We derive the theoretical lower bound on the cumulative regret and propose a learning algorithm having a regret upper bound that matches the lower bound. In a simulation study, we show that our learning algorithm outperforms straightforward extensions of standard multi-armed bandit algorithms.

CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations - Kühne, Thomas; Iannuzzi, Marcella; Ben, Mauro Del; Rybkin, Vladimir V.; Seewald, Patrick; Stein, Frederick; Laino, Teodoro; Khaliullin, Rustam Z.; Schütt, Ole; Schiffmann, Florian; Golze, Dorothea; Wilhelm, Jan; et al. (The Journal of Chemical Physics)
CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension.

A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K - Lass, Michael; Schade, Robert; Kühne, Thomas; Plessl, Christian (Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC))
Electronic structure calculations based on density-functional theory (DFT) represent a significant part of today's HPC workloads and pose high demands on high-performance computing resources. To perform these quantum-mechanical DFT calculations on complex large-scale systems, so-called linear scaling methods instead of conventional cubic scaling methods are required. In this work, we take up the idea of the submatrix method and apply it to the DFT computations in the software package CP2K. For that purpose, we transform the underlying numeric operations on distributed, large, sparse matrices into computations on local, much smaller and nearly dense matrices. This allows us to exploit the full floating-point performance of modern CPUs and to make use of dedicated accelerator hardware, where performance has been limited by memory bandwidth before. We demonstrate both functionality and performance of our implementation and show how it can be accelerated with GPUs and FPGAs.

Evaluating FPGA Accelerator Performance with a Parameterized OpenCL Adaptation of Selected Benchmarks of the HPCChallenge Benchmark Suite - Meyer, Marius; Kenter, Tobias; Plessl, Christian (2020 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC))
FPGAs have found increasing adoption in data center applications since a new generation of high-level tools have become available which noticeably reduce development time for FPGA accelerators and still provide high-quality results. There is, however, no high-level benchmark suite available, which specifically enables a comparison of FPGA architectures, programming tools, and libraries for HPC applications. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community. To fill this gap, we have developed an OpenCL-based open-source implementation of the HPCC benchmark suite for Xilinx and Intel FPGAs. This benchmark can serve to analyze the current capabilities of FPGA devices, cards, and development tool flows, track progress over time, and point out specific difficulties for FPGA acceleration in the HPC domain. Additionally, the benchmark documents proven performance optimization patterns. We will continue optimizing and porting the benchmark for new generations of FPGAs and design tools and encourage active participation to create a valuable tool for the community.
Keywords: FPGA; OpenCL; High Level Synthesis; HPC benchmarking

Accurate Sampling with Noisy Forces from Approximate Computing - Rengaraj, Varadarajan; Lass, Michael; Plessl, Christian; Kühne, Thomas (Computation)
In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.

Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL - Riebler, Heinrich; Vaz, Gavin Francis; Kenter, Tobias; Plessl, Christian (ACM Trans. Archit. Code Optim. (TACO))
Keywords: htrop

OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs - Gorlani, Paolo; Kenter, Tobias; Plessl, Christian (Proceedings of the International Conference on Field-Programmable Technology (FPT))
Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.

Efficient parallel branch-and-bound search on FPGAs using work stealing and instance-specific designs - Riebler, Heinrich

A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices - Richters, Dorothee; Lass, Michael; Walther, Andrea; Plessl, Christian; Kühne, Thomas (Communications in Computational Physics)
We address the general mathematical problem of computing the inverse p-th root of a given matrix in an efficient way. A new method to construct iteration functions that allow calculating arbitrary p-th roots and their inverses of symmetric positive definite matrices is presented. We show that the order of convergence is at least quadratic and that adaptively adjusting a parameter q always leads to an even faster convergence. In this way, a better performance than with previously known iteration schemes is achieved. The efficiency of the iterative functions is demonstrated for various matrices with different densities, condition numbers and spectral radii.

FPGAs im Rechenzentrum - Platzner, Marco; Plessl, Christian (Informatik Spektrum)

Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots - Lass, Michael; Kühne, Thomas; Plessl, Christian (Embedded Systems Letters)
Approximate computing has shown to provide new ways to improve performance and power consumption of error-resilient applications. While many of these applications can be found in image processing, data classification or machine learning, we demonstrate its suitability to a problem from scientific computing. Utilizing the self-correcting behavior of iterative algorithms, we show that approximate computing can be applied to the calculation of inverse matrix p-th roots which are required in many applications in scientific computing. Results show great opportunities to reduce the computational effort and bandwidth required for the execution of the discussed algorithm, especially when targeting special accelerator hardware.

A Data Structure for Planning Based Workload Management of Heterogeneous HPC Systems - Keller, Axel (Proc. Workshop on Job Scheduling Strategies for Parallel Processing (JSSPP))
This paper describes a data structure and a heuristic to plan and map arbitrary resources in complex combinations while applying time dependent constraints. The approach is used in the planning based workload manager OpenCCS at the Paderborn Center for Parallel Computing (PC\(^2\)) to operate heterogeneous clusters with up to 10000 cores. We also show performance results derived from four years of operation.
Keywords: Scheduling Planning Mapping Workload management

Study Effects of Approximation on Conjugate Gradient Algorithm and Accelerate it on FPGA Platform - Filmwala, Tasneem

Programmable Programs? - Designing FPGA Overlay Architectures with OpenCL - Gadewar, Onkar

Sprint diagnostic with GPS and inertial sensor fusion - Mertens, Jan Cedric; Boschmann, Alexander; Schmidt, M.; Plessl, Christian (Sports Engineering)

Accelerating Molecular Dynamic Simulations by Offloading Fast Fourier Transformations to FPGA - Ramaswami, Arjun
Molecular Dynamic (MD) simulations are computationally intensive and accelerating them using specialized hardware is a topic of investigation in many studies. One of the routines in the critical path of MD simulations is the three-dimensional Fast Fourier Transformation (FFT3d). The potential in accelerating FFT3d using hardware is usually bound by bandwidth and memory. Therefore, designing a high throughput solution for an FPGA that overcomes this problem is challenging. In this thesis, the feasibility of offloading FFT3d computations to FPGA implemented using OpenCL is investigated. In order to mask the latency in memory access, an FFT3d that overlaps computation with communication is designed. The implementa- tion of this design is synthesized for the Arria 10 GX 1150 FPGA and evaluated with the FFTW benchmark. Analysis shows a better performance using FPGA over CPU for larger FFT sizes, with the 643 FFT showing a 70% improvement in runtime using FPGAs. This FFT3d design is integrated with CP2K to explore the potential in accelerating molecular dynamic simulations. Evaluation of CP2K simulations using FPGA shows a 41% improvement in runtime in FFT3d computations over CPU for larger FFT3d designs.
Keywords: FFT: FPGA; CP2K; OpenCL

Theory of optically controlled anisotropic polariton transport in semiconductor double microcavities - Luk, Samuel M. H.; Lewandowski, P.; Kwong, N. H.; Baudin, E.; Lafont, O.; Tignon, J.; Leung, P. T.; Chan, Ch. K. P.; Babilon, M.; Schumacher, Stefan; Binder, R. (Journal of the Optical Society of America B)

OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes - Kenter, Tobias; Mahale, Gopinath; Alhaddad, Samer; Grynko, Yevgen; Schmitt, Christian; Afzal, Ayesha; Hannig, Frank; Förstner, Jens; Plessl, Christian (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.
Keywords: tet_topic_hpc

A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices - Lass, Michael; Mohr, Stephan; Wiebeler, Hendrik; Kühne, Thomas; Plessl, Christian (Proc. Platform for Advanced Scientific Computing (PASC) Conference)
We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures. We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.
Keywords: approximate computing; linear algebra; matrix inversion; matrix p-th roots; numeric algorithm; parallel computing

Automated Code Acceleration Targeting Heterogeneous OpenCL Devices - Riebler, Heinrich; Vaz, Gavin Francis; Kenter, Tobias; Plessl, Christian (Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP))
Keywords: htrop

Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs - Riebler, Heinrich; Lass, Michael; Mittendorf, Robert; Löcke, Thomas; Plessl, Christian (ACM Transactions on Reconfigurable Technology and Systems (TRETS))
Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance. We evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.
Keywords: coldboot

Flexible FPGA design for FDTD using OpenCL - Kenter, Tobias; Förstner, Jens; Plessl, Christian (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.
Keywords: tet_topic_hpc

High-Throughput and Low-Latency Network Communication with NetIO - Schumacher, Jörn; Plessl, Christian; Vandelli, Wainer (Journal of Physics: Conference Series)

Modeling and simulation of metallic, particle-damped spheres for lightweight materials - Steinle, Tobias
Lightweight materials play an ever growing role in today's world. Saving on the mass of a machine will usually translate into a lower energy consumption. However, lightweight applications are prone to develop performance problems due to vibration induced by the operation of the machine. The Fraunhofer Institute for Manufacturing Technology and Advanced Materials in Dresden conducts research into the damping properties of composite materials. They are experimenting with hollow, particle filled spheres embedded in the lightweight material. Such a system is the technical motivation of this thesis. Ultimately, a numerical experiment to derive the coefficient of restitution is required. The simulation developed in this thesis is based on a discrete element method to track the individual particle and sphere trajectories. Based on a potential based approach for the particle interactions deployed in molecular dynamics, the behavior of the particles can be controlled effectively. The simulated volume is using reflecting boundaries and encloses the hollow sphere. In this work, a highly flexible memory structure was used with a linked cell approach to cope with the highly flexible mass of particles. This allows for a linear complexity of the method in regard to the particle number by reducing the computational overhead of the interaction computation. Multiple numerical experiments show the great effect the particles have on the damping behavior of the system.

Multiobjective Optimal Control Methods for the Development of an Intelligent Cruise Control - Dellnitz, Michael; Eckstein, Julian; Flaßkamp, Kathrin; Friedel, Patrick; Horenkamp, Christian; Köhler, Ulrich; Ober-Blöbaum, Sina; Peitz, Sebastian; Tiemeyer, Sebastian (Progress in Industrial Mathematics at ECMI)

Confidentiality and Authenticity for Distributed Version Control Systems - A Mercurial Extension - Lass, Michael; Leibenger, Dominik; Sorge, Christoph (Proc. 41st Conference on Local Computer Networks (LCN))
Version Control Systems (VCS) are a valuable tool for software development and document management. Both client/server and distributed (Peer-to-Peer) models exist, with the latter (e.g., Git and Mercurial) becoming increasingly popular. Their distributed nature introduces complications, especially concerning security: it is hard to control the dissemination of contents stored in distributed VCS as they rely on replication of complete repositories to any involved user. We overcome this issue by designing and implementing a concept for cryptography-enforced access control which is transparent to the user. Use of field-tested schemes (end-to-end encryption, digital signatures) allows for strong security, while adoption of convergent encryption and content-defined chunking retains storage efficiency. The concept is seamlessly integrated into Mercurial---respecting its distributed storage concept---to ensure practical usability and compatibility to existing deployments.
Keywords: access control; distributed version control systems; mercurial; peer-to-peer; convergent encryption; confidentiality; authenticity

Sicherheit von hybriden FPGA-Systemen in der industriellen Automatisierungstechnik -- Anforderungen und Umsetzung - Tölke, Christian

Dynamic OpenCL Task Scheduling for Energy and Performance in a Heterogeneous Environment - Wüllrich, Gunnar

Reconfigurable Accelerators in the World of General-Purpose Computing - Kenter, Tobias

ReconOS - Agne, Andreas; Platzner, Marco; Plessl, Christian; Happe, Markus; Lübbers, Enno (FPGAs for Software Programmers)
In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.

Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems - Riebler, Heinrich; Vaz, Gavin Francis; Plessl, Christian; Trainiti, Ettore M. G.; Durelli, Gianluca C.; Bolchini, Cristiana (Proc. HiPEAC Workshop on Reonfigurable Computing (WRC))

Microdisk Cavity FDTD Simulation on FPGA using OpenCL - Kenter, Tobias; Plessl, Christian (Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC))

Using Approximate Computing in Scientific Codes - Lass, Michael; Kühne, Thomas; Plessl, Christian (Workshop on Approximate Computing (AC))

Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems - Riebler, Heinrich; Vaz, Gavin Francis; Plessl, Christian; Trainiti, Ettore M. G.; Durelli, Gianluca C.; Del Sozzo, Emanuele; Santambrogio, Marco D.; Bolchini, Christina (Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI))
Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.

Self-aware Compute Nodes - Agne, Andreas; Happe, Markus; Lösch, Achim; Plessl, Christian; Platzner, Marco (Self-aware Computing Systems)
Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.

Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code - Vaz, Gavin Francis; Riebler, Heinrich; Kenter, Tobias; Plessl, Christian (Computers and Electrical Engineering)
A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.

Performance-centric scheduling with task migration for a heterogeneous compute node in the data center - Lösch, Achim; Beisel, Tobias; Kenter, Tobias; Plessl, Christian; Platzner, Marco (Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE))
The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.

Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) - Kenter, Tobias; Vaz, Gavin Francis; Riebler, Heinrich; Plessl, Christian (Workshop on Reconfigurable Computing (WRC))

Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung - Hegler, Sebastian; Statz, Christoph; Mütze, Marco; Mooshofer, Hubert; Goldammer, Matthias; Fendt, Karl; Schwarzer, Stefan; Feldhoff, Kim; Flehmig, Martin; Markwardt, Ulf; E. Nagel, Wolfgang; Schütte, Maria; et al. (tm - Technisches Messen)
Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.

Self-Aware and Self-Expressive Systems – Guest Editor's Introduction - Torresen, Jim; Plessl, Christian; Yao, Xin (IEEE Computer)
Keywords: self-awareness; self-expression

Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction - Peitz, Sebastian; Dellnitz, Michael (PAMM)
In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100.

Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing - Lass, Michael
Demands for computational power and energy efficiency of computing devices are steadily increasing. At the same time, following classic methods to increase speed and reduce energy consumption of these devices becomes increasingly difficult, bringing alternative methods into focus. One of these methods is approximate computing which utilizes the fact that small errors in computations are acceptable in many applications in order to allow acceleration of these computations or to increase energy efficiency. This thesis develops elements of a workflow that can be followed to apply approximate computing to existing applications. It proposes a novel heuristic approach to the localization of code paths that are suitable to approximate computing based on findings in recent research. Additionally, an approach to identification of approximable instructions within these code paths is proposed and used to implement simulation of approximation. The parts of the workflow are implemented with the goal to lay the foundation for a partly automated toolflow. Evaluation of the developed techniques shows that the proposed methods can help providing a convenient workflow, facilitating the first steps into the application of approximate computing.

An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures - Funke, Lukas

Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems - Löcke, Thomas

Accelerating Programmable Logic Controllers with the use of FPGAs - Wallaschek, Felix

Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing - Beisel, Tobias
The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types. Enabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes. This thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies.

Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (International Journal of Reconfigurable Computing (IJRC))
FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores - Damschen, Marvin; Plessl, Christian (Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT))
This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm - Schumacher, Jörn; T. Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann-Miotto, Giovanna; Levinson, L.; et al. (Proc. Int. Conf. on Distributed Event-Based Systems (DEBS))

Aktuelles Schlagwort: Approximate Computing - Plessl, Christian; Platzner, Marco; Schreier, Peter J. (Informatik Spektrum)
Keywords: approximate computing; survey

Transparent offloading of computational hotspots from binary code to Xeon Phi - Damschen, Marvin; Riebler, Heinrich; Vaz, Gavin Francis; Plessl, Christian (Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE))
In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades - Anderson, J; Borga, A; Boterenbrood, H; Chen, H; Chen, K; Drake, G; Francis, D; Gorini, B; Lanni, F; Lehmann Miotto, G; Levinson, L; Narevicius, J; et al. (Journal of Physics: Conference Series)
The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.

Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres - Steinle, Tobias; Vrabec, Jadran; Walther, Andrea (Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC))
In light of an increasing awareness of environmental challenges, extensive research is underway to develop new light-weight materials. A problem arising with these materials is their increased response to vibration. This can be solved using a new composite material that contains embedded hollow spheres that are partially filled with particles. Progress on the adaptation of molecular dynamics towards a particle-based numerical simulation of this material is reported. This includes the treatment of specific boundary conditions and the adaption of the force computation. First results are presented that showcase the damping properties of such particle-filled spheres in a bouncing experiment.

On Semeai Detection in Monte-Carlo Go - Graf, Tobias; Schaefers, Lars; Platzner, Marco (Proc. Conf. on Computers and Games (CG))

Verschiebungen an der Grenze zwischen Hardware und Software - Platzner, Marco; Plessl, Christian (Logiken strukturbildender Prozesse: Automatismen)
Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinﬂusst und sogar zur Entstehung von neuen Forschungsrichtungen geführt. In diesem Beitrag beschäftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenständige Produkte diﬀerenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, geführt hat. Im Hardware/Software Co-design ﬁndet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software während der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen können wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom während der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonﬁgurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers während der Laufzeit verändert werden kann. Diese Technologie führt zu einer durchlässigen Grenze zwischen Hardware und Software bzw. löst sie die herkömmliche Vorstellung einer festen Hardware und einer ﬂexiblen Software damit auf.

Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer - Kenter, Tobias; Vaz, Gavin Francis; Plessl, Christian (Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC))
In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.

Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators - Agne, Andreas; Hangmann, Hendrik; Happe, Markus; Platzner, Marco; Plessl, Christian (Microprocessors and Microsystems)
Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.

Reconstructing AES Key Schedules from Decayed Memory with FPGAs - Riebler, Heinrich; Kenter, Tobias; Plessl, Christian; Sorge, Christoph (Proceedings of Field-Programmable Custom Computing Machines (FCCM))
In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.
Keywords: coldboot

Self-awareness as a Model for Designing and Operating Heterogeneous Multicores - Agne, Andreas; Happe, Markus; Lösch, Achim; Plessl, Christian; Platzner, Marco (ACM Transactions on Reconfigurable Technology and Systems (TRETS))
Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.

ReconOS - An Operating System Approach for Reconfigurable Computing - Agne, Andreas; Happe, Markus; Keller, Ariane; Lübbers, Enno; Plattner, Bernhard; Platzner, Marco; Plessl, Christian (IEEE Micro)
The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications

Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach - C. Durelli, Gianluca; Pogliani, Marcello; Miele, Antonio; Plessl, Christian; Riebler, Heinrich; Vaz, Gavin Francis; D. Santambrogio, Marco; Bolchini, Cristiana (Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA))

Deferring Accelerator Offloading Decisions to Application Runtime - Vaz, Gavin Francis; Riebler, Heinrich; Kenter, Tobias; Plessl, Christian (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.

Kernel-Centric Acceleration of High Accuracy Stereo-Matching - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig))
Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.

SAVE: Towards efficient resource management in heterogeneous system architectures - C. Durelli, Gianluca; Copolla, Marcello; Djafarian, Karim; Koranaros, George; Miele, Antonio; Paolino, Michele; Pell, Oliver; Plessl, Christian; D. Santambrogio, Marco; Bolchini, Cristiana (Proc. Int. Conf. on Reconfigurable Computing: Architectures, Tools and Applications (ARC))

Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers - Giefers, Heiner; Plessl, Christian; Förstner, Jens (ACM SIGARCH Computer Architecture News)
Keywords: funding-maxup; tet_topic_hpc

MCD: Overcoming the Data Download Bottleneck in Data Centers - Kaiser, Jürgen; Meister, Dirk; Gottfried, Viktor; Brinkmann, André (Proc. IEEE Int. Conf. on Networking, Architecture and Storage (NAS))

FPGA Implementation of a Second-Order Convolutive Blind Signal Separation Algorithm - Kasap, Server; Redif, Soydan (Proc. IEEE Signal Processing and Communications Conf. (SUI))

Distributing Storage in Cloud Environments - Berenbrink, Petra; Brinkmann, André; Friedetzky, Tom; Meister, Dirk; Nagel, Lars (Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW))

Autonomous Resource Management in Dynamic Data Centers - Niehörster, Oliver

Advanced Data Deduplication Techniques and Their Application - Meister, Dirk

Novel Field-Programmable Gate Array Architecture for Computing the Eigenvalue Decomposition of Para-Hermitian Polynomial Matrices - Kasap, Server; Redif, Soydan (IEEE Trans. on Very Large Scale Integration (VLSI) Systems)

File Recipe Compression in Data Deduplication Systems - Meister, Dirk; Brinkmann, André; Süß, Tim (Proc. USENIX Conference on File and Storage Technologies (FAST))

Identifikation und Wiederherstellung von kryptographischen Schlüsseln mit FPGAs - Riebler, Heinrich
Keywords: coldboot

FPGA-accelerated Key Search for Cold-Boot Attacks against AES - Riebler, Heinrich; Kenter, Tobias; Sorge, Christoph; Plessl, Christian (Proceedings of the International Conference on Field-Programmable Technology (FPT))
Cold-boot attacks exploit the fact that DRAM contents are not immediately lost when a PC is powered off. Instead the contents decay rather slowly, in particular if the DRAM chips are cooled to low temperatures. This effect opens an attack vector on cryptographic applications that keep decrypted keys in DRAM. An attacker with access to the target computer can reboot it or remove the RAM modules and quickly copy the RAM contents to non-volatile memory. By exploiting the known cryptographic structure of the cipher and layout of the key data in memory, in our application an AES key schedule with redundancy, the resulting memory image can be searched for sections that could correspond to decayed cryptographic keys; then, the attacker can attempt to reconstruct the original key. However, the runtime of these algorithms grows rapidly with increasing memory image size, error rate and complexity of the bit error model, which limits the practicability of the approach.In this work, we study how the algorithm for key search can be accelerated with custom computing machines. We present an FPGA-based architecture on a Maxeler dataflow computing system that outperforms a software implementation up to 205x, which significantly improves the practicability of cold-attacks against AES.
Keywords: coldboot

On-The-Fly Computing: A Novel Paradigm for Individualized IT Services - Happe, Markus; Kling, Peter; Plessl, Christian; Platzner, Marco; Meyer auf der Heide, Friedhelm (Proceedings of the 9th IEEE Workshop on Software Technology for Future embedded and Ubiquitous Systems (SEUS))
In this paper we introduce “On-The-Fly Computing”, our vision of future IT services that will be provided by assembling modular software components available on world-wide markets. After suitable components have been found, they are automatically integrated, configured and brought to execution in an On-The-Fly Compute Center. We envision that these future compute centers will continue to leverage three current trends in large scale computing which are an increasing amount of parallel processing, a trend to use heterogeneous computing resources, and—in the light of rising energy cost—energy-efficiency as a primary goal in the design and operation of computing systems. In this paper, we point out three research challenges and our current work in these areas.

Parallel Macro Pipelining on the Intel SCC Many-Core Computer - Suess, Tim; Schoenrock, Andrew; Meisner, Sebastian; Plessl, Christian (Proc. Int. Symp. on Parallel and Distributed Processing Workshops (IPDPSW))

Cost-aware and SLO Fulfilling Software as a Service - Niehörster, Oliver; Simon, Jens; Brinkmann, André; Keller, Axel; Krüger, Jens (Journal of Grid Computing)
Virtualization technology makes data centers more dynamic and easier to administrate. Today, cloud providers offer customers access to complex applications running on virtualized hardware. Nevertheless, big virtualized data centers become stochastic environments and the simplification on the user side leads to many challenges for the provider. He has to find cost-efficient configurations and has to deal with dynamic environments to ensure service level objectives (SLOs). We introduce a software solution that reduces the degree of human intervention to manage clouds. It is designed as a multi-agent system (MAS) and placed on top of the Infrastructure as a Service (IaaS) layer. Worker agents allocate resources, configure applications, check the feasibility of requests, and generate cost estimates. They are equipped with application specific knowledge allowing it to estimate the type and number of necessary resources. During runtime, a worker agent monitors the job and adapts its resources to ensure the specified quality of service—even in noisy clouds where the job instances are influenced by other jobs. They interact with a scheduler agent, which takes care of limited resources and does a cost-aware scheduling by assigning jobs to times with low costs. The whole architecture is self-optimizing and able to use public or private clouds. Building a private cloud needs to face the challenge to find a mapping of virtual machines (VMs) to hosts. We present a rule-based mapping algorithm for VMs. It offers an interface where policies can be defined and combined in a generic way. The algorithm performs the initial mapping at request time as well as a remapping during runtime. It deals with policy and infrastructure changes. An energy-aware scheduler and the availability of cheap resources provided by a spot market are analyzed. We evaluated our approach by building up an SaaS stack, which assigns resources in consideration of an energy function and that ensures SLOs of two different applications, a brokerage system and a high-performance computing software. Experiments were done on a real cloud system and by simulations.

FPGA-based design and implementation of an approximate polynomial matrix EVD algorithm - Kasap, Server; Redif, Soydan (Proc. Int. Conf. on Field Programmable Technology (ICFPT))

ESB: Ext2 Split Block Device - Kaiser, Jürgen; Meister, Dirk; Hartung, Tim; Brinkmann, André (Proc. IEEE Int. Conf. on Parallel and Distributed Systems (ICPADS))

A Study on Data Deduplication in HPC Storage Systems - Meister, Dirk; Kaiser, Jürgen; Brinkmann, André; Kuhn, Michael; Kunkel, Julian; Cortes, Toni (Proc. Int. Conf. on Supercomputing (SC))

FPGA implementation of a second-order convolutive blind signal separation algorithm - Kasap, Server; Redif, Soydan (Int. Architecture and Engineering Symp. (ARCHENG))

Towards Dynamic Scripted pNFS Layouts - Grawinkel, Matthias; Süß, Tim; Best, Georg; Popov, Ivan; Brinkmann, André (Proc. Parallel Data Storage Workshop (PDSW))

A Single Sign-On Infrastructure for Science Gateways on a Use Case for Structural Bioinformatics - Gesing, Sandra; Grunzke, Richard; Krüger, Jens; Birkenheuer, Georg; Wewior, Martin; Schäfer, Patrick; Schuller, Bernd; Schuster, Johannes; Herres-Pawlis, Sonja; Breuers, Sebastian; Balaskó, Ákos; Kozlovszky, Miklos; et al. (Journal of Grid Computing)

Comparison of Bayesian Move Prediction Systems for Computer Go - Wistuba, Martin; Schaefers, Lars; Platzner, Marco (Proc. IEEE Conf. on Computational Intelligence and Games (CIG))