---
_id: '238'
abstract:
- lang: eng
text: In this paper, we study how binary applications can be transparently accelerated
with novel heterogeneous computing resources without requiring any manual porting
or developer-provided hints. Our work is based on Binary Acceleration At Runtime
(BAAR), our previously introduced binary acceleration mechanism that uses the
LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture.
The client runs the program to be accelerated in an environment, which allows
program analysis and profiling and identifies and extracts suitable program parts
to be offloaded. The server compiles and optimizes these offloaded program parts
for the accelerator and offers access to these functions to the client with a
remote procedure call (RPC) interface. Our previous work proved the feasibility
of our approach, but also showed that communication time and overheads limit the
granularity of functions that can be meaningfully offloaded. In this work, we
motivate the importance of a lightweight, high-performance communication between
server and client and present a communication mechanism based on the Message Passing
Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as
the acceleration target and show that the communication overhead can be reduced
from 40% to 10%, thus enabling even small hotspots to benefit from offloading
to an accelerator.
author:
- first_name: Marvin
full_name: Damschen, Marvin
last_name: Damschen
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational
hotspots from binary code to Xeon Phi. In: Proceedings of the 2015 Conference
on Design, Automation and Test in Europe (DATE). EDA Consortium / IEEE; 2015:1078-1083.
doi:10.7873/DATE.2015.1124'
apa: Damschen, M., Riebler, H., Vaz, G. F., & Plessl, C. (2015). Transparent
offloading of computational hotspots from binary code to Xeon Phi. Proceedings
of the 2015 Conference on Design, Automation and Test in Europe (DATE), 1078–1083.
https://doi.org/10.7873/DATE.2015.1124
bibtex: '@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading
of computational hotspots from binary code to Xeon Phi}, DOI={10.7873/DATE.2015.1124},
booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and
Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015},
pages={1078–1083} }'
chicago: Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl.
“Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.”
In Proceedings of the 2015 Conference on Design, Automation and Test in Europe
(DATE), 1078–83. EDA Consortium / IEEE, 2015. https://doi.org/10.7873/DATE.2015.1124.
ieee: 'M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading
of computational hotspots from binary code to Xeon Phi,” in Proceedings of
the 2015 Conference on Design, Automation and Test in Europe (DATE), 2015,
pp. 1078–1083, doi: 10.7873/DATE.2015.1124.'
mla: Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots
from Binary Code to Xeon Phi.” Proceedings of the 2015 Conference on Design,
Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–83,
doi:10.7873/DATE.2015.1124.
short: 'M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015
Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE,
2015, pp. 1078–1083.'
date_created: 2017-10-17T12:41:38Z
date_updated: 2023-09-26T13:31:44Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.7873/DATE.2015.1124
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-21T10:29:49Z
date_updated: 2018-03-21T10:29:49Z
file_id: '1500'
file_name: 238-plessl15_date.pdf
file_size: 380552
relation: main_file
success: 1
file_date_updated: 2018-03-21T10:29:49Z
has_accepted_license: '1'
language:
- iso: eng
page: 1078-1083
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the 2015 Conference on Design, Automation and Test in
Europe (DATE)
publisher: EDA Consortium / IEEE
quality_controlled: '1'
status: public
title: Transparent offloading of computational hotspots from binary code to Xeon Phi
type: conference
user_id: '15278'
year: '2015'
...
---
_id: '1775'
abstract:
- lang: eng
text: The ATLAS experiment at CERN is planning full deployment of a new unified
optical link technology for connecting detector front end electronics on the timescale
of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver)
links, with transfer rates up to 10.24 Gbps, will replace existing links used
for readout, detector control and distribution of timing and trigger information.
A new class of devices will be needed to interface many GBT links to the rest
of the trigger, data-acquisition and detector control systems. In this paper FELIX
(Front End LInk eXchange) is presented, a PC-based device to route data from and
to multiple GBT links via a high-performance general purpose network capable of
a total throughput up to O(20 Tbps). FELIX implies architectural changes to the
ATLAS data acquisition system, such as the use of industry standard COTS components
early in the DAQ chain. Additionally the design and implementation of a FELIX
demonstration platform is presented and hardware and software aspects will be
discussed.
article_number: '082050'
author:
- first_name: J
full_name: Anderson, J
last_name: Anderson
- first_name: A
full_name: Borga, A
last_name: Borga
- first_name: H
full_name: Boterenbrood, H
last_name: Boterenbrood
- first_name: H
full_name: Chen, H
last_name: Chen
- first_name: K
full_name: Chen, K
last_name: Chen
- first_name: G
full_name: Drake, G
last_name: Drake
- first_name: D
full_name: Francis, D
last_name: Francis
- first_name: B
full_name: Gorini, B
last_name: Gorini
- first_name: F
full_name: Lanni, F
last_name: Lanni
- first_name: G
full_name: Lehmann Miotto, G
last_name: Lehmann Miotto
- first_name: L
full_name: Levinson, L
last_name: Levinson
- first_name: J
full_name: Narevicius, J
last_name: Narevicius
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: A
full_name: Roich, A
last_name: Roich
- first_name: S
full_name: Ryu, S
last_name: Ryu
- first_name: F
full_name: Schreuder, F
last_name: Schreuder
- first_name: Jörn
full_name: Schumacher, Jörn
last_name: Schumacher
- first_name: Wainer
full_name: Vandelli, Wainer
last_name: Vandelli
- first_name: J
full_name: Vermeulen, J
last_name: Vermeulen
- first_name: J
full_name: Zhang, J
last_name: Zhang
citation:
ama: 'Anderson J, Borga A, Boterenbrood H, et al. FELIX: a High-Throughput Network
Approach for Interfacing to Front End Electronics for ATLAS Upgrades. Journal
of Physics: Conference Series. 2015;664. doi:10.1088/1742-6596/664/8/082050'
apa: 'Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G.,
Francis, D., Gorini, B., Lanni, F., Lehmann Miotto, G., Levinson, L., Narevicius,
J., Plessl, C., Roich, A., Ryu, S., Schreuder, F., Schumacher, J., Vandelli, W.,
Vermeulen, J., & Zhang, J. (2015). FELIX: a High-Throughput Network Approach
for Interfacing to Front End Electronics for ATLAS Upgrades. Journal of Physics:
Conference Series, 664, Article 082050. https://doi.org/10.1088/1742-6596/664/8/082050'
bibtex: '@article{Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_Lehmann
Miotto_et al._2015, title={FELIX: a High-Throughput Network Approach for Interfacing
to Front End Electronics for ATLAS Upgrades}, volume={664}, DOI={10.1088/1742-6596/664/8/082050},
number={082050}, journal={Journal of Physics: Conference Series}, publisher={IOP
Publishing}, author={Anderson, J and Borga, A and Boterenbrood, H and Chen, H
and Chen, K and Drake, G and Francis, D and Gorini, B and Lanni, F and Lehmann
Miotto, G and et al.}, year={2015} }'
chicago: 'Anderson, J, A Borga, H Boterenbrood, H Chen, K Chen, G Drake, D Francis,
et al. “FELIX: A High-Throughput Network Approach for Interfacing to Front End
Electronics for ATLAS Upgrades.” Journal of Physics: Conference Series
664 (2015). https://doi.org/10.1088/1742-6596/664/8/082050.'
ieee: 'J. Anderson et al., “FELIX: a High-Throughput Network Approach for
Interfacing to Front End Electronics for ATLAS Upgrades,” Journal of Physics:
Conference Series, vol. 664, Art. no. 082050, 2015, doi: 10.1088/1742-6596/664/8/082050.'
mla: 'Anderson, J., et al. “FELIX: A High-Throughput Network Approach for Interfacing
to Front End Electronics for ATLAS Upgrades.” Journal of Physics: Conference
Series, vol. 664, 082050, IOP Publishing, 2015, doi:10.1088/1742-6596/664/8/082050.'
short: 'J. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis,
B. Gorini, F. Lanni, G. Lehmann Miotto, L. Levinson, J. Narevicius, C. Plessl,
A. Roich, S. Ryu, F. Schreuder, J. Schumacher, W. Vandelli, J. Vermeulen, J. Zhang,
Journal of Physics: Conference Series 664 (2015).'
date_created: 2018-03-23T14:19:27Z
date_updated: 2023-09-26T13:31:23Z
department:
- _id: '27'
- _id: '518'
doi: 10.1088/1742-6596/664/8/082050
intvolume: ' 664'
language:
- iso: eng
publication: 'Journal of Physics: Conference Series'
publisher: IOP Publishing
quality_controlled: '1'
status: public
title: 'FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics
for ATLAS Upgrades'
type: journal_article
user_id: '15278'
volume: 664
year: '2015'
...
---
_id: '1781'
abstract:
- lang: eng
text: In light of an increasing awareness of environmental challenges, extensive
research is underway to develop new light-weight materials. A problem arising
with these materials is their increased response to vibration. This can be solved
using a new composite material that contains embedded hollow spheres that are
partially filled with particles. Progress on the adaptation of molecular dynamics
towards a particle-based numerical simulation of this material is reported. This
includes the treatment of specific boundary conditions and the adaption of the
force computation. First results are presented that showcase the damping properties
of such particle-filled spheres in a bouncing experiment.
author:
- first_name: Tobias
full_name: Steinle, Tobias
last_name: Steinle
- first_name: Jadran
full_name: Vrabec, Jadran
last_name: Vrabec
- first_name: Andrea
full_name: Walther, Andrea
last_name: Walther
citation:
ama: 'Steinle T, Vrabec J, Walther A. Numerical Simulation of the Damping Behavior
of Particle-Filled Hollow Spheres. In: Bock HG, Hoang XP, Rannacher R, Schlöder
JP, eds. Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC).
Springer International Publishing; 2014:233-243. doi:10.1007/978-3-319-09063-4_19'
apa: Steinle, T., Vrabec, J., & Walther, A. (2014). Numerical Simulation of
the Damping Behavior of Particle-Filled Hollow Spheres. In H. G. Bock, X. P. Hoang,
R. Rannacher, & J. P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization
of Complex Processes (HPSC) (pp. 233–243). Springer International Publishing.
https://doi.org/10.1007/978-3-319-09063-4_19
bibtex: '@inproceedings{Steinle_Vrabec_Walther_2014, title={Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres}, DOI={10.1007/978-3-319-09063-4_19},
booktitle={Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)},
publisher={Springer International Publishing}, author={Steinle, Tobias and Vrabec,
Jadran and Walther, Andrea}, editor={Bock, Hans Georg and Hoang, Xuan Phu and
Rannacher, Rolf and Schlöder, Johannes P.Editors}, year={2014}, pages={233–243}
}'
chicago: Steinle, Tobias, Jadran Vrabec, and Andrea Walther. “Numerical Simulation
of the Damping Behavior of Particle-Filled Hollow Spheres.” In Proc. Modeling,
Simulation and Optimization of Complex Processes (HPSC), edited by Hans Georg
Bock, Xuan Phu Hoang, Rolf Rannacher, and Johannes P. Schlöder, 233–43. Springer
International Publishing, 2014. https://doi.org/10.1007/978-3-319-09063-4_19.
ieee: T. Steinle, J. Vrabec, and A. Walther, “Numerical Simulation of the Damping
Behavior of Particle-Filled Hollow Spheres,” in Proc. Modeling, Simulation
and Optimization of Complex Processes (HPSC), 2014, pp. 233–243.
mla: Steinle, Tobias, et al. “Numerical Simulation of the Damping Behavior of Particle-Filled
Hollow Spheres.” Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), edited by Hans Georg Bock et al., Springer International Publishing,
2014, pp. 233–43, doi:10.1007/978-3-319-09063-4_19.
short: 'T. Steinle, J. Vrabec, A. Walther, in: H.G. Bock, X.P. Hoang, R. Rannacher,
J.P. Schlöder (Eds.), Proc. Modeling, Simulation and Optimization of Complex Processes
(HPSC), Springer International Publishing, 2014, pp. 233–243.'
date_created: 2018-03-26T13:47:16Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '104'
- _id: '155'
doi: 10.1007/978-3-319-09063-4_19
editor:
- first_name: Hans Georg
full_name: Bock, Hans Georg
last_name: Bock
- first_name: Xuan Phu
full_name: Hoang, Xuan Phu
last_name: Hoang
- first_name: Rolf
full_name: Rannacher, Rolf
last_name: Rannacher
- first_name: Johannes P.
full_name: Schlöder, Johannes P.
last_name: Schlöder
page: 233-243
publication: Proc. Modeling, Simulation and Optimization of Complex Processes (HPSC)
publication_identifier:
isbn:
- 978-3-319-09063-4
publisher: Springer International Publishing
status: public
title: Numerical Simulation of the Damping Behavior of Particle-Filled Hollow Spheres
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '1782'
author:
- first_name: Tobias
full_name: Graf, Tobias
last_name: Graf
- first_name: Lars
full_name: Schaefers, Lars
last_name: Schaefers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Graf T, Schaefers L, Platzner M. On Semeai Detection in Monte-Carlo Go. In:
Proc. Conf. on Computers and Games (CG). Lecture Notes in Computer Science.
Switzerland: Springer; 2014:14-25. doi:10.1007/978-3-319-09165-5_2'
apa: 'Graf, T., Schaefers, L., & Platzner, M. (2014). On Semeai Detection in
Monte-Carlo Go. In Proc. Conf. on Computers and Games (CG) (pp. 14–25).
Switzerland: Springer. https://doi.org/10.1007/978-3-319-09165-5_2'
bibtex: '@inproceedings{Graf_Schaefers_Platzner_2014, place={Switzerland}, series={Lecture
Notes in Computer Science}, title={On Semeai Detection in Monte-Carlo Go}, DOI={10.1007/978-3-319-09165-5_2},
number={8427}, booktitle={Proc. Conf. on Computers and Games (CG)}, publisher={Springer},
author={Graf, Tobias and Schaefers, Lars and Platzner, Marco}, year={2014}, pages={14–25},
collection={Lecture Notes in Computer Science} }'
chicago: 'Graf, Tobias, Lars Schaefers, and Marco Platzner. “On Semeai Detection
in Monte-Carlo Go.” In Proc. Conf. on Computers and Games (CG), 14–25.
Lecture Notes in Computer Science. Switzerland: Springer, 2014. https://doi.org/10.1007/978-3-319-09165-5_2.'
ieee: T. Graf, L. Schaefers, and M. Platzner, “On Semeai Detection in Monte-Carlo
Go,” in Proc. Conf. on Computers and Games (CG), 2014, no. 8427, pp. 14–25.
mla: Graf, Tobias, et al. “On Semeai Detection in Monte-Carlo Go.” Proc. Conf.
on Computers and Games (CG), no. 8427, Springer, 2014, pp. 14–25, doi:10.1007/978-3-319-09165-5_2.
short: 'T. Graf, L. Schaefers, M. Platzner, in: Proc. Conf. on Computers and Games
(CG), Springer, Switzerland, 2014, pp. 14–25.'
date_created: 2018-03-26T13:50:37Z
date_updated: 2022-01-06T06:53:20Z
department:
- _id: '27'
- _id: '78'
doi: 10.1007/978-3-319-09165-5_2
issue: '8427'
page: 14-25
place: Switzerland
publication: Proc. Conf. on Computers and Games (CG)
publisher: Springer
series_title: Lecture Notes in Computer Science
status: public
title: On Semeai Detection in Monte-Carlo Go
type: conference
user_id: '24135'
year: '2014'
...
---
_id: '335'
abstract:
- lang: eng
text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware
und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten
nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung
der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung
von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen
wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren
insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir
beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der
Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige
Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem
Computersystem besser in Hardware und welche besser in Software realisiert werden
sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen
Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat.
Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze
zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt,
um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten
Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software
beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen
eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption,
dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware
und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen
auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware
eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie
f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw.
l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer
flexiblen Software damit auf.
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software.
In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender
Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.”
Wilhelm Fink; 2014:123-144.'
apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen
Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144).
Wilhelm Fink.'
bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe
des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen
Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen},
publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller,
Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144},
collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }'
chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44.
Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink,
2014.'
ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware
und Software,” in Logiken strukturbildender Prozesse: Automatismen, J.
Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink,
2014, pp. 123–144.'
mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.'
short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn,
2014, pp. 123–144.'
date_created: 2017-10-17T12:41:57Z
date_updated: 2023-09-26T13:32:49Z
ddc:
- '040'
department:
- _id: '518'
- _id: '27'
- _id: '78'
editor:
- first_name: Jörn
full_name: Künsemöller, Jörn
last_name: Künsemöller
- first_name: Norber Otto
full_name: Eke, Norber Otto
last_name: Eke
- first_name: Lioba
full_name: Foit, Lioba
last_name: Foit
- first_name: Timo
full_name: Kaerlein, Timo
last_name: Kaerlein
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:29:58Z
date_updated: 2018-03-20T07:29:58Z
file_id: '1424'
file_name: 335-2014_plessl_automatismen.pdf
file_size: 2848154
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:29:58Z
has_accepted_license: '1'
language:
- iso: ger
page: 123-144
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Logiken strukturbildender Prozesse: Automatismen'
publication_identifier:
isbn:
- 978-3-7705-5730-1
publication_status: published
publisher: Wilhelm Fink
quality_controlled: '1'
series_title: Schriftenreihe des Graduiertenkollegs "Automatismen"
status: public
title: Verschiebungen an der Grenze zwischen Hardware und Software
type: book_chapter
user_id: '15278'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '365'
abstract:
- lang: eng
text: Self-aware computing is a paradigm for structuring and simplifying the design
and operation of computing systems that face unprecedented levels of system dynamics
and thus require novel forms of adaptivity. The generality of the paradigm makes
it applicable to many types of computing systems and, previously, researchers
started to introduce concepts of self-awareness to multicore architectures. In
our work we build on a recent reference architectural framework as a model for
self-aware computing and instantiate it for an FPGA-based heterogeneous multicore
running the ReconOS reconfigurable architecture and operating system. After presenting
the model for self-aware computing and ReconOS, we demonstrate with a case study
how a multicore application built on the principle of self-awareness, autonomously
adapts to changes in the workload and system state. Our work shows that the reference
architectural framework as a model for self-aware computing can be practically
applied and allows us to structure and simplify the design process, which is essential
for designing complex future computing systems.
article_number: '13'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for
Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable
Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions
on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13.
https://doi.org/10.1145/2617596
bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as
a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM
Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM},
author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian
and Platzner, Marco}, year={2014} }'
chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner.
“Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no.
2 (2014). https://doi.org/10.1145/2617596.
ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions
on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no.
13, 2014, doi: 10.1145/2617596.'
mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating
Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on
Reconfigurable Technology and Systems (TRETS) 7 (2014).
date_created: 2017-10-17T12:42:03Z
date_updated: 2023-09-26T13:33:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '78'
- _id: '518'
doi: 10.1145/2617596
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:19:19Z
date_updated: 2018-03-20T07:19:19Z
file_id: '1406'
file_name: 365-plessl14_trets_01.pdf
file_size: 916052
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:19:19Z
has_accepted_license: '1'
intvolume: ' 7'
issue: '2'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publisher: ACM
quality_controlled: '1'
status: public
title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
type: journal_article
user_id: '15278'
volume: 7
year: '2014'
...
---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...