--- _id: '31' author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Ettore M. G. full_name: Trainiti, Ettore M. G. last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Cristiana full_name: Bolchini, Cristiana last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). ; 2016.' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proc. HiPEAC Workshop on Reonfigurable Computing (WRC). bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. ieee: H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016. mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.' date_created: 2017-07-26T15:16:31Z date_updated: 2023-09-26T13:25:59Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: deffel date_created: 2019-01-11T11:56:55Z date_updated: 2019-01-11T11:56:55Z file_id: '6626' file_name: wrc_upb_polimi_final.pdf file_size: 394563 relation: main_file success: 1 file_date_updated: 2019-01-11T11:56:55Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC) quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '24' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Plessl C. Microdisk Cavity FDTD Simulation on FPGA using OpenCL. In: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). ; 2016.' apa: Kenter, T., & Plessl, C. (2016). Microdisk Cavity FDTD Simulation on FPGA using OpenCL. Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC). bibtex: '@inproceedings{Kenter_Plessl_2016, title={Microdisk Cavity FDTD Simulation on FPGA using OpenCL}, booktitle={Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}, author={Kenter, Tobias and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” In Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. ieee: T. Kenter and C. Plessl, “Microdisk Cavity FDTD Simulation on FPGA using OpenCL,” 2016. mla: Kenter, Tobias, and Christian Plessl. “Microdisk Cavity FDTD Simulation on FPGA Using OpenCL.” Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016. short: 'T. Kenter, C. Plessl, in: Proc. Workshop on Heterogeneous High-Performance Reconfigurable Computing (H2RC), 2016.' date_created: 2017-07-26T15:00:43Z date_updated: 2023-09-26T13:26:17Z ddc: - '004' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: kenter date_created: 2018-11-14T12:38:45Z date_updated: 2018-11-14T12:38:45Z file_id: '5602' file_name: paper_26.pdf file_size: 129552 relation: main_file success: 1 file_date_updated: 2018-11-14T12:38:45Z has_accepted_license: '1' language: - iso: eng project: - _id: '32' grant_number: PL 595/2-1 / 320898746 name: Performance and Efficiency in HPC with Custom Computing - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' grant_number: '160364472' name: SFB 901 - Subproject C2 publication: Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC) quality_controlled: '1' status: public title: Microdisk Cavity FDTD Simulation on FPGA using OpenCL type: conference user_id: '15278' year: '2016' ... --- _id: '25' author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 - first_name: Thomas full_name: Kühne, Thomas id: '49079' last_name: Kühne - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Lass M, Kühne T, Plessl C. Using Approximate Computing in Scientific Codes. In: Workshop on Approximate Computing (AC). ; 2016.' apa: Lass, M., Kühne, T., & Plessl, C. (2016). Using Approximate Computing in Scientific Codes. Workshop on Approximate Computing (AC). bibtex: '@inproceedings{Lass_Kühne_Plessl_2016, title={Using Approximate Computing in Scientific Codes}, booktitle={Workshop on Approximate Computing (AC)}, author={Lass, Michael and Kühne, Thomas and Plessl, Christian}, year={2016} }' chicago: Lass, Michael, Thomas Kühne, and Christian Plessl. “Using Approximate Computing in Scientific Codes.” In Workshop on Approximate Computing (AC), 2016. ieee: M. Lass, T. Kühne, and C. Plessl, “Using Approximate Computing in Scientific Codes,” 2016. mla: Lass, Michael, et al. “Using Approximate Computing in Scientific Codes.” Workshop on Approximate Computing (AC), 2016. short: 'M. Lass, T. Kühne, C. Plessl, in: Workshop on Approximate Computing (AC), 2016.' date_created: 2017-07-26T15:02:20Z date_updated: 2023-09-26T13:25:17Z department: - _id: '27' - _id: '518' - _id: '304' language: - iso: eng project: - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Workshop on Approximate Computing (AC) quality_controlled: '1' status: public title: Using Approximate Computing in Scientific Codes type: conference user_id: '15278' year: '2016' ... --- _id: '138' abstract: - lang: eng text: Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads. author: - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: 'Ettore M. G. ' full_name: 'Trainiti, Ettore M. G. ' last_name: Trainiti - first_name: Gianluca C. full_name: Durelli, Gianluca C. last_name: Durelli - first_name: Emanuele full_name: Del Sozzo, Emanuele last_name: Del Sozzo - first_name: 'Marco D. ' full_name: 'Santambrogio, Marco D. ' last_name: Santambrogio - first_name: Christina full_name: Bolchini, Christina last_name: Bolchini citation: ama: 'Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI). IEEE; 2016:1-5. doi:10.1109/RTSI.2016.7740545' apa: Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., & Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. https://doi.org/10.1109/RTSI.2016.7740545 bibtex: '@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={10.1109/RTSI.2016.7740545}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}, year={2016}, pages={1–5} }' chicago: Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D. Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 1–5. IEEE, 2016. https://doi.org/10.1109/RTSI.2016.7740545. ieee: 'H. Riebler et al., “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), 2016, pp. 1–5, doi: 10.1109/RTSI.2016.7740545.' mla: Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5, doi:10.1109/RTSI.2016.7740545. short: 'H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5.' date_created: 2017-10-17T12:41:18Z date_updated: 2023-09-26T13:28:11Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1109/RTSI.2016.7740545 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:01:09Z date_updated: 2018-03-21T13:01:09Z file_id: '1560' file_name: 138-07740545.pdf file_size: 184334 relation: main_file success: 1 file_date_updated: 2018-03-21T13:01:09Z has_accepted_license: '1' language: - iso: eng page: 1-5 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI) publisher: IEEE quality_controlled: '1' status: public title: Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems type: conference user_id: '15278' year: '2016' ... --- _id: '156' abstract: - lang: eng text: Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level. author: - first_name: Andreas full_name: Agne, Andreas last_name: Agne - first_name: Markus full_name: Happe, Markus last_name: Happe - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-aware Compute Nodes. In: Self-Aware Computing Systems. Natural Computing Series (NCS). Springer International Publishing; 2016:145-165. doi:10.1007/978-3-319-39675-0_8' apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2016). Self-aware Compute Nodes. In Self-aware Computing Systems (pp. 145–165). Springer International Publishing. https://doi.org/10.1007/978-3-319-39675-0_8 bibtex: '@inbook{Agne_Happe_Lösch_Plessl_Platzner_2016, place={Cham}, series={Natural Computing Series (NCS)}, title={Self-aware Compute Nodes}, DOI={10.1007/978-3-319-39675-0_8}, booktitle={Self-aware Computing Systems}, publisher={Springer International Publishing}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2016}, pages={145–165}, collection={Natural Computing Series (NCS)} }' chicago: 'Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Aware Compute Nodes.” In Self-Aware Computing Systems, 145–65. Natural Computing Series (NCS). Cham: Springer International Publishing, 2016. https://doi.org/10.1007/978-3-319-39675-0_8.' ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-aware Compute Nodes,” in Self-aware Computing Systems, Cham: Springer International Publishing, 2016, pp. 145–165.' mla: Agne, Andreas, et al. “Self-Aware Compute Nodes.” Self-Aware Computing Systems, Springer International Publishing, 2016, pp. 145–65, doi:10.1007/978-3-319-39675-0_8. short: 'A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, in: Self-Aware Computing Systems, Springer International Publishing, Cham, 2016, pp. 145–165.' date_created: 2017-10-17T12:41:22Z date_updated: 2023-09-26T13:27:44Z ddc: - '040' department: - _id: '518' - _id: '27' - _id: '78' doi: 10.1007/978-3-319-39675-0_8 file: - access_level: closed content_type: application/pdf creator: aloesch date_created: 2018-11-14T13:20:32Z date_updated: 2018-11-14T13:20:32Z file_id: '5613' file_name: chapter8.pdf file_size: 833054 relation: main_file success: 1 file_date_updated: 2018-11-14T13:20:32Z has_accepted_license: '1' language: - iso: eng page: 145-165 place: Cham project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Self-aware Computing Systems publisher: Springer International Publishing quality_controlled: '1' series_title: Natural Computing Series (NCS) status: public title: Self-aware Compute Nodes type: book_chapter user_id: '15278' year: '2016' ... --- _id: '165' abstract: - lang: eng text: A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes. author: - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering. 2016;55:91-111. doi:10.1016/j.compeleceng.2016.04.021 apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. Computers and Electrical Engineering, 55, 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021 bibtex: '@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={10.1016/j.compeleceng.2016.04.021}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }' chicago: 'Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering 55 (2016): 91–111. https://doi.org/10.1016/j.compeleceng.2016.04.021.' ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” Computers and Electrical Engineering, vol. 55, pp. 91–111, 2016, doi: 10.1016/j.compeleceng.2016.04.021.' mla: Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” Computers and Electrical Engineering, vol. 55, Elsevier, 2016, pp. 91–111, doi:10.1016/j.compeleceng.2016.04.021. short: G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111. date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:26:38Z ddc: - '040' department: - _id: '27' - _id: '518' doi: 10.1016/j.compeleceng.2016.04.021 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:45:47Z date_updated: 2018-03-21T12:45:47Z file_id: '1544' file_name: 165-1-s2.0-S0045790616301021-main.pdf file_size: 3037854 relation: main_file success: 1 file_date_updated: 2018-03-21T12:45:47Z has_accepted_license: '1' intvolume: ' 55' language: - iso: eng page: 91-111 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Computers and Electrical Engineering publication_identifier: issn: - 0045-7906 publisher: Elsevier quality_controlled: '1' status: public title: Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code type: journal_article user_id: '15278' volume: 55 year: '2016' ... --- _id: '168' abstract: - lang: eng text: The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative. author: - first_name: Achim full_name: Lösch, Achim id: '43646' last_name: Lösch - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Lösch A, Beisel T, Kenter T, Plessl C, Platzner M. Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. In: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). EDA Consortium / IEEE; 2016:912-917.' apa: Lösch, A., Beisel, T., Kenter, T., Plessl, C., & Platzner, M. (2016). Performance-centric scheduling with task migration for a heterogeneous compute node in the data center. Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–917. bibtex: '@inproceedings{Lösch_Beisel_Kenter_Plessl_Platzner_2016, title={Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}, booktitle={Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={EDA Consortium / IEEE}, author={Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}, year={2016}, pages={912–917} }' chicago: Lösch, Achim, Tobias Beisel, Tobias Kenter, Christian Plessl, and Marco Platzner. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” In Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 912–17. EDA Consortium / IEEE, 2016. ieee: A. Lösch, T. Beisel, T. Kenter, C. Plessl, and M. Platzner, “Performance-centric scheduling with task migration for a heterogeneous compute node in the data center,” in Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pp. 912–917. mla: Lösch, Achim, et al. “Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center.” Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–17. short: 'A. Lösch, T. Beisel, T. Kenter, C. Plessl, M. Platzner, in: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), EDA Consortium / IEEE, 2016, pp. 912–917.' date_created: 2017-10-17T12:41:24Z date_updated: 2023-09-26T13:27:00Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:41:55Z date_updated: 2018-03-21T12:41:55Z file_id: '1541' file_name: 168-07459438.pdf file_size: 261356 relation: main_file success: 1 file_date_updated: 2018-03-21T12:41:55Z has_accepted_license: '1' language: - iso: eng page: 912-917 project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '30' grant_number: 01|H11004A name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication: Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) publisher: EDA Consortium / IEEE quality_controlled: '1' status: public title: Performance-centric scheduling with task migration for a heterogeneous compute node in the data center type: conference user_id: '15278' year: '2016' ... --- _id: '171' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Gavin Francis full_name: Vaz, Gavin Francis id: '30332' last_name: Vaz - first_name: Heinrich full_name: Riebler, Heinrich id: '8961' last_name: Riebler - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: Workshop on Reconfigurable Computing (WRC). ; 2016.' apa: Kenter, T., Vaz, G. F., Riebler, H., & Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). Workshop on Reconfigurable Computing (WRC). bibtex: '@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }' chicago: Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In Workshop on Reconfigurable Computing (WRC), 2016. ieee: T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016. mla: Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” Workshop on Reconfigurable Computing (WRC), 2016. short: 'T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.' date_created: 2017-10-17T12:41:25Z date_updated: 2023-09-26T13:27:21Z ddc: - '040' department: - _id: '27' - _id: '518' file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T12:39:46Z date_updated: 2018-03-21T12:39:46Z file_id: '1538' file_name: 171-plessl16_fpl_wrc.pdf file_size: 54421 relation: main_file success: 1 file_date_updated: 2018-03-21T12:39:46Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Workshop on Reconfigurable Computing (WRC) quality_controlled: '1' status: public title: Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract) type: conference user_id: '15278' year: '2016' ... --- _id: '1769' abstract: - lang: eng text: 'Große zylindrische Stahlprüflinge werden mittels der Methode der finiten Differenzen im Zeitbereich (engl. finite differences in time domain, FDTD) simulativ untersucht. Dabei werden Pitch-Catch-Messanordnungen verwendet. Es werden zwei Bildgebungsansätze vorgestellt: ersterer basiert auf dem Imaging Principle nach Claerbout, letzterer basiert auf gradientenbasierter Optimierung eines Zielfunktionals.' author: - first_name: Sebastian full_name: Hegler, Sebastian last_name: Hegler - first_name: Christoph full_name: Statz, Christoph last_name: Statz - first_name: Marco full_name: Mütze, Marco last_name: Mütze - first_name: Hubert full_name: Mooshofer, Hubert last_name: Mooshofer - first_name: Matthias full_name: Goldammer, Matthias last_name: Goldammer - first_name: Karl full_name: Fendt, Karl last_name: Fendt - first_name: Stefan full_name: Schwarzer, Stefan last_name: Schwarzer - first_name: Kim full_name: Feldhoff, Kim last_name: Feldhoff - first_name: Martin full_name: Flehmig, Martin last_name: Flehmig - first_name: Ulf full_name: Markwardt, Ulf last_name: Markwardt - first_name: Wolfgang full_name: E. Nagel, Wolfgang last_name: E. Nagel - first_name: Maria full_name: Schütte, Maria last_name: Schütte - first_name: Andrea full_name: Walther, Andrea last_name: Walther - first_name: Michael full_name: Meinel, Michael last_name: Meinel - first_name: Achim full_name: Basermann, Achim last_name: Basermann - first_name: Dirk full_name: Plettemeier, Dirk last_name: Plettemeier citation: ama: Hegler S, Statz C, Mütze M, et al. Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. tm - Technisches Messen. 2015;82(9):440-450. doi:doi:10.1515/teme-2015-0031 apa: Hegler, S., Statz, C., Mütze, M., Mooshofer, H., Goldammer, M., Fendt, K., … Plettemeier, D. (2015). Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung. Tm - Technisches Messen, 82(9), 440–450. https://doi.org/doi:10.1515/teme-2015-0031 bibtex: '@article{Hegler_Statz_Mütze_Mooshofer_Goldammer_Fendt_Schwarzer_Feldhoff_Flehmig_Markwardt_et al._2015, title={Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung}, volume={82}, DOI={doi:10.1515/teme-2015-0031}, number={9}, journal={tm - Technisches Messen}, publisher={Walter de Gruyter}, author={Hegler, Sebastian and Statz, Christoph and Mütze, Marco and Mooshofer, Hubert and Goldammer, Matthias and Fendt, Karl and Schwarzer, Stefan and Feldhoff, Kim and Flehmig, Martin and Markwardt, Ulf and et al.}, year={2015}, pages={440–450} }' chicago: 'Hegler, Sebastian, Christoph Statz, Marco Mütze, Hubert Mooshofer, Matthias Goldammer, Karl Fendt, Stefan Schwarzer, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen 82, no. 9 (2015): 440–50. https://doi.org/doi:10.1515/teme-2015-0031.' ieee: S. Hegler et al., “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung,” tm - Technisches Messen, vol. 82, no. 9, pp. 440–450, 2015. mla: Hegler, Sebastian, et al. “Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen Für Große Zylindrische Stahl-Prüflinge Und Gradientenbasierte Bildgebung.” Tm - Technisches Messen, vol. 82, no. 9, Walter de Gruyter, 2015, pp. 440–50, doi:doi:10.1515/teme-2015-0031. short: S. Hegler, C. Statz, M. Mütze, H. Mooshofer, M. Goldammer, K. Fendt, S. Schwarzer, K. Feldhoff, M. Flehmig, U. Markwardt, W. E. Nagel, M. Schütte, A. Walther, M. Meinel, A. Basermann, D. Plettemeier, Tm - Technisches Messen 82 (2015) 440–450. date_created: 2018-03-23T14:01:39Z date_updated: 2022-01-06T06:53:17Z department: - _id: '27' - _id: '104' doi: doi:10.1515/teme-2015-0031 intvolume: ' 82' issue: '9' page: 440-450 publication: tm - Technisches Messen publisher: Walter de Gruyter status: public title: Simulative Ultraschall-Untersuchung von Pitch-Catch-Messanordnungen für große zylindrische Stahl-Prüflinge und gradientenbasierte Bildgebung type: journal_article user_id: '24135' volume: 82 year: '2015' ... --- _id: '1772' author: - first_name: Jim full_name: Torresen, Jim last_name: Torresen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Xin full_name: Yao, Xin last_name: Yao citation: ama: Torresen J, Plessl C, Yao X. Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer. 2015;48(7):18-20. doi:10.1109/MC.2015.205 apa: Torresen, J., Plessl, C., & Yao, X. (2015). Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction. IEEE Computer, 48(7), 18–20. https://doi.org/10.1109/MC.2015.205 bibtex: '@article{Torresen_Plessl_Yao_2015, title={Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction}, volume={48}, DOI={10.1109/MC.2015.205}, number={7}, journal={IEEE Computer}, publisher={IEEE Computer Society}, author={Torresen, Jim and Plessl, Christian and Yao, Xin}, year={2015}, pages={18–20} }' chicago: 'Torresen, Jim, Christian Plessl, and Xin Yao. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer 48, no. 7 (2015): 18–20. https://doi.org/10.1109/MC.2015.205.' ieee: J. Torresen, C. Plessl, and X. Yao, “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction,” IEEE Computer, vol. 48, no. 7, pp. 18–20, 2015. mla: Torresen, Jim, et al. “Self-Aware and Self-Expressive Systems – Guest Editor’s Introduction.” IEEE Computer, vol. 48, no. 7, IEEE Computer Society, 2015, pp. 18–20, doi:10.1109/MC.2015.205. short: J. Torresen, C. Plessl, X. Yao, IEEE Computer 48 (2015) 18–20. date_created: 2018-03-23T14:06:12Z date_updated: 2022-01-06T06:53:19Z ddc: - '000' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1109/MC.2015.205 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T15:47:45Z date_updated: 2018-11-02T15:47:45Z file_id: '5313' file_name: 07163237.pdf file_size: 5605009 relation: main_file success: 1 file_date_updated: 2018-11-02T15:47:45Z has_accepted_license: '1' intvolume: ' 48' issue: '7' keyword: - self-awareness - self-expression language: - iso: eng page: 18-20 project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: IEEE Computer publisher: IEEE Computer Society status: public title: Self-Aware and Self-Expressive Systems – Guest Editor's Introduction type: journal_article user_id: '16153' volume: 48 year: '2015' ... --- _id: '1774' abstract: - lang: eng text: In this article an efficient numerical method to solve multiobjective optimization problems for fluid flow governed by the Navier Stokes equations is presented. In order to decrease the computational effort, a reduced order model is introduced using Proper Orthogonal Decomposition and a corresponding Galerkin Projection. A global, derivative free multiobjective optimization algorithm is applied to compute the Pareto set (i.e. the set of optimal compromises) for the concurrent objectives minimization of flow field fluctuations and control cost. The method is illustrated for a 2D flow around a cylinder at Re = 100. author: - first_name: Sebastian full_name: Peitz, Sebastian last_name: Peitz - first_name: Michael full_name: Dellnitz, Michael last_name: Dellnitz citation: ama: Peitz S, Dellnitz M. Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM. 2015;15(1):613-614. doi:10.1002/pamm.201510296 apa: Peitz, S., & Dellnitz, M. (2015). Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction. PAMM, 15(1), 613–614. https://doi.org/10.1002/pamm.201510296 bibtex: '@article{Peitz_Dellnitz_2015, title={Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction}, volume={15}, DOI={10.1002/pamm.201510296}, number={1}, journal={PAMM}, publisher={WILEY-VCH Verlag}, author={Peitz, Sebastian and Dellnitz, Michael}, year={2015}, pages={613–614} }' chicago: 'Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM 15, no. 1 (2015): 613–14. https://doi.org/10.1002/pamm.201510296.' ieee: S. Peitz and M. Dellnitz, “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction,” PAMM, vol. 15, no. 1, pp. 613–614, 2015. mla: Peitz, Sebastian, and Michael Dellnitz. “Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction.” PAMM, vol. 15, no. 1, WILEY-VCH Verlag, 2015, pp. 613–14, doi:10.1002/pamm.201510296. short: S. Peitz, M. Dellnitz, PAMM 15 (2015) 613–614. date_created: 2018-03-23T14:14:24Z date_updated: 2022-01-06T06:53:19Z department: - _id: '27' - _id: '101' doi: 10.1002/pamm.201510296 intvolume: ' 15' issue: '1' page: 613-614 publication: PAMM publication_identifier: issn: - 1617-7061 publisher: WILEY-VCH Verlag status: public title: Multiobjective Optimization of the Flow Around a Cylinder Using Model Order Reduction type: journal_article user_id: '24135' volume: 15 year: '2015' ... --- _id: '1794' abstract: - lang: eng text: Demands for computational power and energy efficiency of computing devices are steadily increasing. At the same time, following classic methods to increase speed and reduce energy consumption of these devices becomes increasingly difficult, bringing alternative methods into focus. One of these methods is approximate computing which utilizes the fact that small errors in computations are acceptable in many applications in order to allow acceleration of these computations or to increase energy efficiency. This thesis develops elements of a workflow that can be followed to apply approximate computing to existing applications. It proposes a novel heuristic approach to the localization of code paths that are suitable to approximate computing based on findings in recent research. Additionally, an approach to identification of approximable instructions within these code paths is proposed and used to implement simulation of approximation. The parts of the workflow are implemented with the goal to lay the foundation for a partly automated toolflow. Evaluation of the developed techniques shows that the proposed methods can help providing a convenient workflow, facilitating the first steps into the application of approximate computing. author: - first_name: Michael full_name: Lass, Michael id: '24135' last_name: Lass orcid: 0000-0002-5708-7632 citation: ama: 'Lass M. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University; 2015.' apa: 'Lass, M. (2015). Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University.' bibtex: '@book{Lass_2015, place={Paderborn}, title={Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing}, publisher={Paderborn University}, author={Lass, Michael}, year={2015} }' chicago: 'Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn: Paderborn University, 2015.' ieee: 'M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing. Paderborn: Paderborn University, 2015.' mla: Lass, Michael. Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing. Paderborn University, 2015. short: M. Lass, Localization and Analysis of Code Paths Suitable for Acceleration Using Approximate Computing, Paderborn University, Paderborn, 2015. date_created: 2018-03-26T15:24:10Z date_updated: 2022-01-06T06:53:23Z department: - _id: '27' - _id: '518' place: Paderborn publisher: Paderborn University status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Localization and Analysis of Code Paths Suitable for Acceleration using Approximate Computing type: mastersthesis user_id: '24135' year: '2015' ... --- _id: '5413' author: - first_name: Lukas full_name: Funke, Lukas last_name: Funke citation: ama: Funke L. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn; 2015. apa: Funke, L. (2015). An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn. bibtex: '@book{Funke_2015, title={An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures}, publisher={Universität Paderborn}, author={Funke, Lukas}, year={2015} }' chicago: Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015. ieee: L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures. Universität Paderborn, 2015. mla: Funke, Lukas. An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures. Universität Paderborn, 2015. short: L. Funke, An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications Using FPGA Overlay Architectures, Universität Paderborn, 2015. date_created: 2018-11-07T15:10:35Z date_updated: 2022-01-06T07:01:52Z department: - _id: '27' - _id: '518' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 publisher: Universität Paderborn status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: An LLVM Based Toolchain for Transparent Acceleration of Digital Image Processing Applications using FPGA Overlay Architectures type: mastersthesis user_id: '477' year: '2015' ... --- _id: '5416' author: - first_name: Thomas full_name: Löcke, Thomas last_name: Löcke citation: ama: Löcke T. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn; 2015. apa: Löcke, T. (2015). Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn. bibtex: '@book{Löcke_2015, title={Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems}, publisher={Universität Paderborn}, author={Löcke, Thomas}, year={2015} }' chicago: Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015. ieee: T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015. mla: Löcke, Thomas. Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems. Universität Paderborn, 2015. short: T. Löcke, Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems, Universität Paderborn, 2015. date_created: 2018-11-07T16:06:53Z date_updated: 2022-01-06T07:01:52Z department: - _id: '27' - _id: '518' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 publisher: Universität Paderborn status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Instance-Specific Computing in Hard- and Software for Faster Solving of Complex Problems type: mastersthesis user_id: '477' year: '2015' ... --- _id: '5419' author: - first_name: Felix full_name: Wallaschek, Felix last_name: Wallaschek citation: ama: Wallaschek F. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn; 2015. apa: Wallaschek, F. (2015). Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn. bibtex: '@book{Wallaschek_2015, title={Accelerating Programmable Logic Controllers with the use of FPGAs}, publisher={Universität Paderborn}, author={Wallaschek, Felix}, year={2015} }' chicago: Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015. ieee: F. Wallaschek, Accelerating Programmable Logic Controllers with the use of FPGAs. Universität Paderborn, 2015. mla: Wallaschek, Felix. Accelerating Programmable Logic Controllers with the Use of FPGAs. Universität Paderborn, 2015. short: F. Wallaschek, Accelerating Programmable Logic Controllers with the Use of FPGAs, Universität Paderborn, 2015. date_created: 2018-11-07T16:14:30Z date_updated: 2022-01-06T07:01:52Z department: - _id: '27' - _id: '518' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '4' name: SFB 901 - Project Area C - _id: '14' name: SFB 901 - Subproject C2 publisher: Universität Paderborn status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Accelerating Programmable Logic Controllers with the use of FPGAs type: mastersthesis user_id: '477' year: '2015' ... --- _id: '10624' abstract: - lang: eng text: "The use of heterogeneous computing resources, such as graphics processing units or other specialized co-processors, has become widespread in recent years because of their performance and energy efficiency advantages. Operating system approaches that are limited to optimizing CPU usage are no longer sufficient for the efficient utilization of systems that comprise diverse resource types.\r\n\r\nEnabling task preemption on these architectures and migration of tasks between different resource types at run-time is not only key to improving the performance and energy consumption but also to enabling automatic scheduling methods for heterogeneous compute nodes.\r\n\r\nThis thesis proposes novel techniques for run-time management of heterogeneous resources and enabling tasks to migrate between diverse hardware. It provides fundamental work towards future operating systems by discussing implications, limitations, and chances of the heterogeneity and introducing solutions for energy- and performance-efficient run-time systems. Scheduling methods to utilize heterogeneous systems by the use of a centralized scheduler are presented that show benefits over existing approaches in varying case studies." author: - first_name: Tobias full_name: Beisel, Tobias last_name: Beisel citation: ama: 'Beisel T. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH; 2015.' apa: 'Beisel, T. (2015). Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH.' bibtex: '@book{Beisel_2015, place={Berlin}, title={Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing}, publisher={Logos Verlag Berlin GmbH}, author={Beisel, Tobias}, year={2015} }' chicago: 'Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' ieee: 'T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Berlin: Logos Verlag Berlin GmbH, 2015.' mla: Beisel, Tobias. Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing. Logos Verlag Berlin GmbH, 2015. short: T. Beisel, Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing, Logos Verlag Berlin GmbH, Berlin, 2015. date_created: 2019-07-10T09:36:58Z date_updated: 2022-01-06T06:50:48Z department: - _id: '78' - _id: '27' - _id: '518' language: - iso: eng page: '183' place: Berlin project: - _id: '30' grant_number: 01|H11004 name: Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models publication_identifier: isbn: - 978-3-8325-4155-2 publisher: Logos Verlag Berlin GmbH status: public supervisor: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 title: Management and Scheduling of Accelerators for Heterogeneous High-Performance Computing type: dissertation user_id: '3118' year: '2015' ... --- _id: '296' abstract: - lang: eng text: FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x. article_number: '859425' author: - first_name: Tobias full_name: Kenter, Tobias id: '3145' last_name: Kenter - first_name: Henning full_name: Schmitz, Henning last_name: Schmitz - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: Kenter T, Schmitz H, Plessl C. Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC). 2015;2015. doi:10.1155/2015/859425 apa: Kenter, T., Schmitz, H., & Plessl, C. (2015). Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study. International Journal of Reconfigurable Computing (IJRC), 2015, Article 859425. https://doi.org/10.1155/2015/859425 bibtex: '@article{Kenter_Schmitz_Plessl_2015, title={Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study}, volume={2015}, DOI={10.1155/2015/859425}, number={859425}, journal={International Journal of Reconfigurable Computing (IJRC)}, publisher={Hindawi}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2015} }' chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC) 2015 (2015). https://doi.org/10.1155/2015/859425. ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study,” International Journal of Reconfigurable Computing (IJRC), vol. 2015, Art. no. 859425, 2015, doi: 10.1155/2015/859425.' mla: Kenter, Tobias, et al. “Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study.” International Journal of Reconfigurable Computing (IJRC), vol. 2015, 859425, Hindawi, 2015, doi:10.1155/2015/859425. short: T. Kenter, H. Schmitz, C. Plessl, International Journal of Reconfigurable Computing (IJRC) 2015 (2015). date_created: 2017-10-17T12:41:49Z date_updated: 2023-09-26T13:29:08Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1155/2015/859425 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T07:47:56Z date_updated: 2018-03-20T07:47:56Z file_id: '1444' file_name: 296-859425.pdf file_size: 2993898 relation: main_file success: 1 file_date_updated: 2018-03-20T07:47:56Z has_accepted_license: '1' intvolume: ' 2015' language: - iso: eng project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: International Journal of Reconfigurable Computing (IJRC) publisher: Hindawi quality_controlled: '1' status: public title: Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study type: journal_article user_id: '15278' volume: 2015 year: '2015' ... --- _id: '303' abstract: - lang: eng text: This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement. author: - first_name: Marvin full_name: Damschen, Marvin last_name: Damschen - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 citation: ama: 'Damschen M, Plessl C. Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. In: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). ; 2015.' apa: Damschen, M., & Plessl, C. (2015). Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores. Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT). bibtex: '@inproceedings{Damschen_Plessl_2015, title={Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores}, booktitle={Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT)}, author={Damschen, Marvin and Plessl, Christian}, year={2015} }' chicago: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” In Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. ieee: M. Damschen and C. Plessl, “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores,” 2015. mla: Damschen, Marvin, and Christian Plessl. “Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores.” Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015. short: 'M. Damschen, C. Plessl, in: Proceedings of the 5th International Workshop on Adaptive Self-Tuning Computing Systems (ADAPT), 2015.' date_created: 2017-10-17T12:41:51Z date_updated: 2023-09-26T13:29:59Z ddc: - '040' department: - _id: '27' - _id: '518' - _id: '78' external_id: arxiv: - '1412.3906' file: - access_level: open_access content_type: application/pdf creator: florida date_created: 2018-03-20T07:46:46Z date_updated: 2019-08-01T09:10:44Z file_id: '1442' file_name: 303-plessl15_adapt.pdf file_size: 1176620 relation: main_file file_date_updated: 2019-08-01T09:10:44Z has_accepted_license: '1' language: - iso: eng oa: '1' project: - _id: '1' grant_number: '160364472' name: SFB 901 - _id: '14' grant_number: '160364472' name: SFB 901 - Subprojekt C2 - _id: '4' name: SFB 901 - Project Area C - _id: '34' grant_number: '610996' name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures publication: Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT) quality_controlled: '1' status: public title: Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores type: conference user_id: '15278' year: '2015' ... --- _id: '1773' author: - first_name: Jörn full_name: Schumacher, Jörn last_name: Schumacher - first_name: J. full_name: T. Anderson, J. last_name: T. Anderson - first_name: A. full_name: Borga, A. last_name: Borga - first_name: H. full_name: Boterenbrood, H. last_name: Boterenbrood - first_name: H. full_name: Chen, H. last_name: Chen - first_name: K. full_name: Chen, K. last_name: Chen - first_name: G. full_name: Drake, G. last_name: Drake - first_name: D. full_name: Francis, D. last_name: Francis - first_name: B. full_name: Gorini, B. last_name: Gorini - first_name: F. full_name: Lanni, F. last_name: Lanni - first_name: Giovanna full_name: Lehmann-Miotto, Giovanna last_name: Lehmann-Miotto - first_name: L. full_name: Levinson, L. last_name: Levinson - first_name: J. full_name: Narevicius, J. last_name: Narevicius - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: A. full_name: Roich, A. last_name: Roich - first_name: S. full_name: Ryu, S. last_name: Ryu - first_name: F. full_name: P. Schreuder, F. last_name: P. Schreuder - first_name: Wainer full_name: Vandelli, Wainer last_name: Vandelli - first_name: J. full_name: Vermeulen, J. last_name: Vermeulen - first_name: J. full_name: Zhang, J. last_name: Zhang citation: ama: 'Schumacher J, T. Anderson J, Borga A, et al. Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. In: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM; 2015. doi:10.1145/2675743.2771824' apa: Schumacher, J., T. Anderson, J., Borga, A., Boterenbrood, H., Chen, H., Chen, K., Drake, G., Francis, D., Gorini, B., Lanni, F., Lehmann-Miotto, G., Levinson, L., Narevicius, J., Plessl, C., Roich, A., Ryu, S., P. Schreuder, F., Vandelli, W., Vermeulen, J., & Zhang, J. (2015). Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm. Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). https://doi.org/10.1145/2675743.2771824 bibtex: '@inproceedings{Schumacher_T. Anderson_Borga_Boterenbrood_Chen_Chen_Drake_Francis_Gorini_Lanni_et al._2015, title={Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm}, DOI={10.1145/2675743.2771824}, booktitle={Proc. Int. Conf. on Distributed Event-Based Systems (DEBS)}, publisher={ACM}, author={Schumacher, Jörn and T. Anderson, J. and Borga, A. and Boterenbrood, H. and Chen, H. and Chen, K. and Drake, G. and Francis, D. and Gorini, B. and Lanni, F. and et al.}, year={2015} }' chicago: Schumacher, Jörn, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” In Proc. Int. Conf. on Distributed Event-Based Systems (DEBS). ACM, 2015. https://doi.org/10.1145/2675743.2771824. ieee: 'J. Schumacher et al., “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm,” 2015, doi: 10.1145/2675743.2771824.' mla: Schumacher, Jörn, et al. “Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm.” Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015, doi:10.1145/2675743.2771824. short: 'J. Schumacher, J. T. Anderson, A. Borga, H. Boterenbrood, H. Chen, K. Chen, G. Drake, D. Francis, B. Gorini, F. Lanni, G. Lehmann-Miotto, L. Levinson, J. Narevicius, C. Plessl, A. Roich, S. Ryu, F. P. Schreuder, W. Vandelli, J. Vermeulen, J. Zhang, in: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS), ACM, 2015.' date_created: 2018-03-23T14:09:33Z date_updated: 2023-09-26T13:31:01Z department: - _id: '27' - _id: '518' - _id: '78' doi: 10.1145/2675743.2771824 language: - iso: eng publication: Proc. Int. Conf. on Distributed Event-Based Systems (DEBS) publisher: ACM quality_controlled: '1' status: public title: Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm type: conference user_id: '15278' year: '2015' ... --- _id: '1768' author: - first_name: Christian full_name: Plessl, Christian id: '16153' last_name: Plessl orcid: 0000-0001-5728-9982 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Peter J. full_name: Schreier, Peter J. last_name: Schreier citation: ama: 'Plessl C, Platzner M, Schreier PJ. Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum. 2015;(5):396-399. doi:10.1007/s00287-015-0911-z' apa: 'Plessl, C., Platzner, M., & Schreier, P. J. (2015). Aktuelles Schlagwort: Approximate Computing. Informatik Spektrum, 5, 396–399. https://doi.org/10.1007/s00287-015-0911-z' bibtex: '@article{Plessl_Platzner_Schreier_2015, title={Aktuelles Schlagwort: Approximate Computing}, DOI={10.1007/s00287-015-0911-z}, number={5}, journal={Informatik Spektrum}, publisher={Springer}, author={Plessl, Christian and Platzner, Marco and Schreier, Peter J.}, year={2015}, pages={396–399} }' chicago: 'Plessl, Christian, Marco Platzner, and Peter J. Schreier. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5 (2015): 396–99. https://doi.org/10.1007/s00287-015-0911-z.' ieee: 'C. Plessl, M. Platzner, and P. J. Schreier, “Aktuelles Schlagwort: Approximate Computing,” Informatik Spektrum, no. 5, pp. 396–399, 2015, doi: 10.1007/s00287-015-0911-z.' mla: 'Plessl, Christian, et al. “Aktuelles Schlagwort: Approximate Computing.” Informatik Spektrum, no. 5, Springer, 2015, pp. 396–99, doi:10.1007/s00287-015-0911-z.' short: C. Plessl, M. Platzner, P.J. Schreier, Informatik Spektrum (2015) 396–399. date_created: 2018-03-23T13:58:34Z date_updated: 2023-09-26T13:30:22Z department: - _id: '27' - _id: '518' - _id: '263' - _id: '78' doi: 10.1007/s00287-015-0911-z issue: '5' keyword: - approximate computing - survey language: - iso: eng page: 396-399 publication: Informatik Spektrum publisher: Springer quality_controlled: '1' status: public title: 'Aktuelles Schlagwort: Approximate Computing' type: journal_article user_id: '15278' year: '2015' ...