@inproceedings{24021,
  abstract     = {{This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.}},
  author       = {{Wu, Liang and Weizel, Maxim and Scheytt, Christoph}},
  booktitle    = {{2020 IEEE International Symposium on Circuits and Systems (ISCAS)}},
  isbn         = {{978-1-7281-3320-1}},
  issn         = {{2158-1525 }},
  publisher    = {{IEEE}},
  title        = {{{Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology}}},
  doi          = {{10.1109/ISCAS45731.2020.9180947}},
  year         = {{2020}},
}

@article{24029,
  abstract     = {{In this paper we present the system and circuit level analysis and feasibility study of applying microwave Radio Frequency Identification (RFID) systems with multipleinput multiple-output (MIMO) reader technology for tracking machining tools in multipath fading conditions of production environments. In the proposed system the MIMO reader interrogates single-antenna tags, and a high RFID frequency of 5.8 GHz is chosen to reduce the size of the reader's antenna array. According to the requirements dictated by the performed system analysis at 5.8 GHz, a low power fully integrated analog frontend (AFE) is designed and fabricated in a standard 65-nm CMOS technology for low power passive transponders. Performance of the Differential Drive Rectifier (DDR) topology as the core of the energy harvesting unit is investigated in detail. A multi-stage DDR power scavenging unit is dimensioned to provide a 1.2 V rectified voltage for 20-30 kQ load range, with a high power conversion efficiency (PCE) for high frequency and low input power level signals. The rectified voltage is then converted to a 1 V regulated voltage for the AFE and the baseband processor with 30 to 50 μW of estimated power consumption. Transistors with standard threshold voltage (VT) have been used for implementation. Measurements of the fabricated multi-stage configuration of the circuit show a maximum PCE of 68.8% at -12.46 dBm, and an input quality factor (Q-factor) of approximately 10. Amplitude-shift keying (ASK) demodulator and backscattering modulator with 80% modulation index, operating according to EPC-C1G2 protocol are applied for data transfer. The AFE consumes less than 1 μW in the reading mode. The AFE tag chip is 0.55 × 0.58 mm 2 .}},
  author       = {{Haddadian, Sanaz and Scheytt, Christoph}},
  journal      = {{IEEE Journal of Radio Frequency Identification}},
  pages        = {{1--1}},
  title        = {{{Analysis, Design and Implementation of a Fully Integrated Analog Front-End for Microwave RFIDs at 5.8 GHz to be Used with Compact MIMO Readers}}},
  doi          = {{10.1109/JRFID.2020.3009741}},
  year         = {{2020}},
}

@inproceedings{24026,
  abstract     = {{In this paper we present a new system concept for an optoelectronic wireless phased array system. Like in a conventional phased array system with optical carrier distribution, optical fibers are used to distribute the carrier from the basestation to the wireless frontends. However in contrast to prior concepts, we propose to use an optical IQ return path from the wireless frontends back to the basestation. Furthermore, we reuse the optical carrier signal for the IQ return path which allows to avoid local oscillator lasers in the wireless frontends and reduces the hardware effort significantly. The system concept allows to integrate all components of an optoelectronic wireless frontend in a single chip using silicon photonics technology.}},
  author       = {{Kruse, Stephan and Kress, Christian and Scheytt, Christoph and Kurz, Heiko G. and Schneider, Thomas}},
  booktitle    = {{GeMiC 2020 - German Microwave Conference}},
  title        = {{{Analysis and Simulation of a Wireless Phased Array System with Optical Carrier Distribution and an Optical IQ Return Path}}},
  year         = {{2020}},
}

@article{34841,
  abstract     = {{We give an exact formula for the number of G-extensions of local function fields Fq((t)) for finite abelian groups G up to a conductor bound. As an application we give a lower bound for the corresponding counting problem by discriminant.
}},
  author       = {{Klüners, Jürgen and Müller, Raphael}},
  issn         = {{0022-314X}},
  journal      = {{Journal of Number Theory}},
  keywords     = {{Algebra and Number Theory}},
  pages        = {{311--322}},
  publisher    = {{Elsevier BV}},
  title        = {{{The conductor density of local function fields with abelian Galois group}}},
  doi          = {{10.1016/j.jnt.2019.11.007}},
  volume       = {{212}},
  year         = {{2020}},
}

@article{60386,
  abstract     = {{<jats:p>We propose a novel approach to represent maps between two discrete surfaces of the same genus and to minimize intrinsic mapping distortion. Our maps are well-defined at every surface point and are guaranteed to be continuous bijections (surface homeomorphisms). As a key feature of our approach, only the images of vertices need to be represented explicitly, since the images of all other points (on edges or in faces) are properly defined implicitly. This definition is via unique geodesics in metrics of constant Gaussian curvature. Our method is built upon the fact that such metrics exist on surfaces of arbitrary topology, without the need for any cuts or cones (as asserted by the uniformization theorem). Depending on the surfaces' genus, these metrics exhibit one of the three classical geometries: Euclidean, spherical or hyperbolic. Our formulation handles constructions in all three geometries in a unified way. In addition, by considering not only the vertex images but also the discrete metric as degrees of freedom, our formulation enables us to simultaneously optimize the images of these vertices and images of all other points.</jats:p>}},
  author       = {{Schmidt, Patrick and Campen, Marcel and Born, Janis and Kobbelt, Leif}},
  issn         = {{0730-0301}},
  journal      = {{ACM Transactions on Graphics}},
  number       = {{4}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Inter-surface maps via constant-curvature metrics}}},
  doi          = {{10.1145/3386569.3392399}},
  volume       = {{39}},
  year         = {{2020}},
}

@article{60385,
  abstract     = {{<jats:p>We present a mesh generation algorithm for the curvilinear triangulation of planar domains with piecewise polynomial boundary. The resulting mesh consists of regular, injective higher-order triangular elements and precisely conforms with the domain's curved boundary. No smoothness requirements are imposed on the boundary. Prescribed piecewise polynomial curves in the interior, like material interfaces or feature curves, can be taken into account for precise interpolation by the resulting mesh's edges as well. In its core, the algorithm is based on a novel explicit construction of guaranteed injective Bézier triangles with certain edge curves and edge parametrizations prescribed. Due to the use of only rational arithmetic, the algorithm can optionally be performed using exact number types in practice, so as to provide robustness guarantees.</jats:p>}},
  author       = {{Mandad, Manish and Campen, Marcel}},
  issn         = {{0730-0301}},
  journal      = {{ACM Transactions on Graphics}},
  number       = {{4}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Bézier guarding}}},
  doi          = {{10.1145/3386569.3392372}},
  volume       = {{39}},
  year         = {{2020}},
}

@article{60383,
  abstract     = {{<jats:title>Abstract</jats:title><jats:p>The problem of seamless parametrization of surfaces is of interest in the context of structured quadrilateral mesh generation and spline‐based surface approximation. It has been tackled by a variety of approaches, commonly relying on continuous numerical optimization to ultimately obtain suitable parameter domains. We present a general combinatorial seamless parameter domain construction, free from the potential numerical issues inherent to continuous optimization techniques in practice. The domains are constructed as abstract polygonal complexes which can be embedded in a discrete planar grid space, as unions of unit squares. We ensure that the domain structure matches any prescribed parametrization singularities (cones) and satisfies seamlessness conditions. Surfaces of arbitrary genus are supported. Once a domain suitable for a given surface is constructed, a seamless and locally injective parametrization over this domain can be obtained using existing planar disk mapping techniques, making recourse to Tutte's classical embedding theorem.</jats:p>}},
  author       = {{Zhou, Jiaran and Tu, Changhe and Zorin, Denis and Campen, Marcel}},
  issn         = {{0167-7055}},
  journal      = {{Computer Graphics Forum}},
  number       = {{2}},
  pages        = {{179--190}},
  publisher    = {{Wiley}},
  title        = {{{Combinatorial Construction of Seamless Parameter Domains}}},
  doi          = {{10.1111/cgf.13922}},
  volume       = {{39}},
  year         = {{2020}},
}

@article{60382,
  author       = {{Mandad, Manish and Campen, Marcel}},
  issn         = {{0010-4485}},
  journal      = {{Computer-Aided Design}},
  publisher    = {{Elsevier BV}},
  title        = {{{Efficient piecewise higher-order parametrization of discrete surfaces with local and global injectivity}}},
  doi          = {{10.1016/j.cad.2020.102862}},
  volume       = {{127}},
  year         = {{2020}},
}

@article{21267,
  author       = {{Budde, Lea and Schulte, Carsten and Buhl, Heike M. and Muehling, Andreas}},
  journal      = {{Seventh International Conference on Learning and Teaching in Computing and Engineeringe}},
  keywords     = {{⛔ No DOI found}},
  publisher    = {{(IEEE)}},
  title        = {{{Understanding and Explaining Digital Artefacts - the Role of a Duality (Accepted Paper - Digital Publication Follows)}}},
  year         = {{2020}},
}

@article{15266,
  author       = {{Yigitbas, Enes and Jovanovikj, Ivan and Biermeier, Kai and Sauer, Stefan and Engels, Gregor}},
  journal      = {{International Journal on Software and Systems Modeling (SoSyM)}},
  publisher    = {{Springer}},
  title        = {{{Integrated Model-driven Development of Self-adaptive User Interfaces }}},
  year         = {{2020}},
}

@inproceedings{16726,
  author       = {{Razzaghi Kouchaksaraei, Hadi and Shivarpatna Venkatesh, Ashwin Prasad and Churi, Amey and Illian, Marvin and Karl, Holger}},
  booktitle    = {{European Conference on Networks and Communications (EUCNC 2020)}},
  title        = {{{Dynamic Provisioning of Network Services on Heterogeneous Resources}}},
  year         = {{2020}},
}

@unpublished{19523,
  abstract     = {{We study the problem of learning choice functions, which play an important
role in various domains of application, most notably in the field of economics.
Formally, a choice function is a mapping from sets to sets: Given a set of
choice alternatives as input, a choice function identifies a subset of most
preferred elements. Learning choice functions from suitable training data comes
with a number of challenges. For example, the sets provided as input and the
subsets produced as output can be of any size. Moreover, since the order in
which alternatives are presented is irrelevant, a choice function should be
symmetric. Perhaps most importantly, choice functions are naturally
context-dependent, in the sense that the preference in favor of an alternative
may depend on what other options are available. We formalize the problem of
learning choice functions and present two general approaches based on two
representations of context-dependent utility functions. Both approaches are
instantiated by means of appropriate neural network architectures, and their
performance is demonstrated on suitable benchmark tasks.}},
  author       = {{Pfannschmidt, Karlson and Gupta, Pritha and Hüllermeier, Eyke}},
  booktitle    = {{arXiv:1901.10860}},
  title        = {{{Learning Choice Functions: Concepts and Architectures}}},
  year         = {{2019}},
}

@article{19945,
  abstract     = {{Many PDEs (Burgers' equation, KdV, Camassa-Holm, Euler's fluid equations, …) can be formulated as infinite-dimensional Lie-Poisson systems. These are Hamiltonian systems on manifolds equipped with Poisson brackets. The Poisson structure is connected to conservation properties and other geometric features of solutions to the PDE and, therefore, of great interest for numerical integration. For the example of Burgers' equations and related PDEs we use Clebsch variables to lift the original system to a collective Hamiltonian system on a symplectic manifold whose structure is related to the original Lie-Poisson structure. On the collective Hamiltonian system a symplectic integrator can be applied. Our numerical examples show excellent conservation properties and indicate that the disadvantage of an increased phase-space dimension can be outweighed by the advantage of symplectic integration.}},
  author       = {{McLachlan, Robert I and Offen, Christian and Tapley, Benjamin K}},
  issn         = {{2158-2505}},
  journal      = {{Journal of Computational Dynamics}},
  number       = {{1}},
  pages        = {{111--130}},
  publisher    = {{American Institute of Mathematical Sciences (AIMS)}},
  title        = {{{Symplectic integration of PDEs using Clebsch variables}}},
  doi          = {{10.3934/jcd.2019005}},
  volume       = {{6}},
  year         = {{2019}},
}

@inproceedings{24053,
  abstract     = {{We overview the 3-year Meteracom project which
will provide traceability to the SI for THz communication
measurement parameters. The key objectives are to develop new
metrological methods to characterize the measurement systems,
system components and propagation channels. The final
objective is to develop metrology for functionality and signal
integrity of THz communication systems; particularly device
discovery and beam tracking, determination of physical layer
parameters for digital transmission and real-time performance
evaluation.}},
  author       = {{Humphreys, David and Berekovic, Mladen and Kallfass, Ingmar and Scheytt, Christoph and Kuerner, Thomas and Jukan, Admela and Schneider, Thomas and Kleine-Ostmann, Thomas and Koch, Martin and Thomae, Reiner}},
  booktitle    = {{Proc. 43-nd Meeting of the Wireless World Research Forum (WWRF)",}},
  title        = {{{An overview of the Meteracom Project}}},
  year         = {{2019}},
}

@inproceedings{24058,
  abstract     = {{Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.}},
  author       = {{Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}},
  title        = {{{RISC-V Extensions for Bit Manipulation Instructions}}},
  doi          = {{10.1109/PATMOS.2019.8862170}},
  year         = {{2019}},
}

@inproceedings{24060,
  abstract     = {{In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. }},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}},
  isbn         = {{978-3-8007-4945-4}},
  title        = {{{Analyse sicherheitskritischer Software für RISC-V Prozessoren}}},
  year         = {{2019}},
}

@inproceedings{24061,
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph and Driessen, Benedikt}},
  booktitle    = {{ 2nd International Workshop on Embedded Software for Industrial IoT in conjunction with DATE 2019}},
  pages        = {{32--34}},
  title        = {{{QEMU for Dynamic Memory Analysis of Security Sensitive Software}}},
  year         = {{2019}},
}

@article{24063,
  abstract     = {{It its current Version 3.1.0 QEMU supports RISC-V RV32GC and RV64GC software emulation in user and full system mode. We will first give an overview of the current state of the QEMU RISC-V implementation. Thereafter, we will present the DecodeTree tool, which will be available with the next QEMU release. DecodeTree is a code generator included in QEMU that can generate the program logic for extracting and decoding opcodes and operands from a formal instruction list of the target architecture. This enables the structured implementation of just-in-time compilations to guarantee that the QEMU implementation meets the ISA specification. As such, we completely replaced the existing RISC-V RV32GC and RV64GC implementations by DecodeTree generations in the next official QEMU release, which is expected in spring 2019. We will demonstrate the DecodeTree applications by the example of RISC-V ISA subset configurations.}},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  journal      = {{2nd International Workshop on RISC-V Research Activities}},
  title        = {{{QEMU Support for RISC-V: Current State and Future Releases}}},
  volume       = {{(Presentation)}},
  year         = {{2019}},
}

@inproceedings{3287,
  abstract     = {{For optimal placement and orchestration of network services, it is crucial
that their structure and semantics are specified clearly and comprehensively
and are available to an orchestrator. Existing specification approaches are
either ambiguous or miss important aspects regarding the behavior of virtual
network functions (VNFs) forming a service. We propose to formally and
unambiguously specify the behavior of these functions and services using
Queuing Petri Nets (QPNs). QPNs are an established method that allows to
express queuing, synchronization, stochastically distributed processing delays,
and changing traffic volume and characteristics at each VNF. With QPNs,
multiple VNFs can be connected to complete network services in any structure,
even specifying bidirectional network services containing loops.
  We discuss how management and orchestration systems can benefit from our
clear and comprehensive specification approach, leading to better placement of
VNFs and improved Quality of Service. Another benefit of formally specifying
network services with QPNs are diverse analysis options, which allow valuable
insights such as the distribution of end-to-end delay. We propose a tool-based
workflow that supports the specification of network services and the automatic
generation of corresponding simulation code to enable an in-depth analysis of
their behavior and performance.}},
  author       = {{Schneider, Stefan Balthasar and Sharma, Arnab and Karl, Holger and Wehrheim, Heike}},
  booktitle    = {{2019 IFIP/IEEE International Symposium on Integrated Network Management (IM)}},
  location     = {{Washington, DC, USA}},
  pages        = {{116----124}},
  publisher    = {{IFIP}},
  title        = {{{Specifying and Analyzing Virtual Network Services Using Queuing Petri Nets}}},
  year         = {{2019}},
}

@article{3585,
  abstract     = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}},
  author       = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}},
  issn         = {{0026-2714}},
  journal      = {{Microelectronics Reliability}},
  keywords     = {{Approximate Computing, Framework, Pareto Front, Accuracy}},
  pages        = {{277--290}},
  publisher    = {{Elsevier}},
  title        = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}},
  doi          = {{10.1016/j.microrel.2019.04.003}},
  volume       = {{99}},
  year         = {{2019}},
}