@article{39466, author = {{Vidor, Fábio F. and Meyers, Thorsten and Wirth, Gilson I. and Hilleringmann, Ulrich}}, issn = {{0167-9317}}, journal = {{Microelectronic Engineering}}, keywords = {{Electrical and Electronic Engineering, Surfaces, Coatings and Films, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Electronic, Optical and Magnetic Materials}}, pages = {{155--158}}, publisher = {{Elsevier BV}}, title = {{{ZnO nanoparticle thin-film transistors on flexible substrate using spray-coating technique}}}, doi = {{10.1016/j.mee.2016.02.059}}, volume = {{159}}, year = {{2016}}, } @article{39467, author = {{Vidor, Fábio and Meyers, Thorsten and Hilleringmann, Ulrich}}, issn = {{2079-4991}}, journal = {{Nanomaterials}}, keywords = {{General Materials Science, General Chemical Engineering}}, number = {{9}}, publisher = {{MDPI AG}}, title = {{{Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications}}}, doi = {{10.3390/nano6090154}}, volume = {{6}}, year = {{2016}}, } @article{42792, abstract = {{We enumerate all positive definite ternary quadratic forms over number fields with class number at most 2. This is done by constructing all definite quaternion orders of type number at most 2 over number fields. Finally, we list all definite quaternion orders of ideal class number 1 or 2.}}, author = {{Kirschmer, Markus and Lorch, David}}, issn = {{0022-314X}}, journal = {{Journal of Number Theory}}, keywords = {{Algebra and Number Theory}}, pages = {{343--361}}, publisher = {{Elsevier BV}}, title = {{{Ternary quadratic forms over number fields with small class number}}}, doi = {{10.1016/j.jnt.2014.11.001}}, volume = {{161}}, year = {{2016}}, } @inproceedings{39476, author = {{Romero, Adrian and Gonzalez, Jesus and Hilleringmann, Ulrich and Gloesekoetter, Peter}}, booktitle = {{ANALOG 2016; 15. ITG/GMM-Symposium}}, pages = {{1--6}}, title = {{{Organic Field-Effect and Nanoparticle Thin-Film Transistors: Static Model}}}, year = {{2016}}, } @inproceedings{39480, author = {{Vidor, F. F. and Meyers, T. and Hilleringmann, Ulrich and Wirth, G. I.}}, booktitle = {{2015 IEEE 15th International Conference on Nanotechnology (IEEE-NANO)}}, publisher = {{IEEE}}, title = {{{Influence of UV irradiation and humidity on a low-cost ZnO nanoparticle TFT for flexible electronics}}}, doi = {{10.1109/nano.2015.7388836}}, year = {{2016}}, } @inproceedings{39478, author = {{Hangmann, C and Mager, T and Khan, S and Hedayat, C and Hilleringmann, Ulrich}}, booktitle = {{Smart System Integration-International Conference and Exhibition on Integration Issues of Miniaturized Systems}}, title = {{{Improved rf design using precise 3d near-field measurements and near-field to far-field transformations}}}, year = {{2016}}, } @article{39456, author = {{Hett, T. and Krämmer, S. and Hilleringmann, Ulrich and Kalt, H. and Zrenner, A.}}, issn = {{0022-2313}}, journal = {{Journal of Luminescence}}, keywords = {{Condensed Matter Physics, Biochemistry, General Chemistry, Atomic and Molecular Physics, and Optics, Biophysics}}, pages = {{131--134}}, publisher = {{Elsevier BV}}, title = {{{High-Q whispering gallery microdisk resonators based on silicon oxynitride}}}, doi = {{10.1016/j.jlumin.2016.11.016}}, volume = {{191}}, year = {{2016}}, } @misc{43454, abstract = {{Die Gitter von Klassenzahl eins oder zwei sind hier verfügbar: http://www.math.rwth-aachen.de/~Markus.Kirschmer/forms/}}, author = {{Kirschmer, Markus}}, pages = {{166}}, title = {{{Definite quadratic and hermitian forms with small class number (Habilitation)}}}, year = {{2016}}, } @article{44339, author = {{Burban, Igor and Gnedin, W.}}, journal = {{Journal of Pure and Applied Algebra}}, number = {{12}}, pages = {{3777–3815}}, title = {{{Cohen-Macaulay modules over some non-reduced curve singularities}}}, volume = {{220}}, year = {{2016}}, } @inproceedings{45332, author = {{Schönherr, Johanna and Schukajlow, S.}}, booktitle = {{Proceedings of the 40th Conference of the International Group for the Psychology of Mathematics Education}}, editor = {{Csíkos, C. and Rausch, A. and Szitányi, J.}}, pages = {{131–138}}, publisher = {{PME}}, title = {{{Are mathematical problems boring? Boredom while solving problems with and without a connection to reality from students’ and pre-service teachers’ perspectives}}}, volume = {{4}}, year = {{2016}}, } @article{13863, author = {{Olfert, Sergei and Henning, Bernd}}, journal = {{Technisches Messen}}, number = {{4}}, pages = {{219--224}}, title = {{{Erweiterung des Raman-Nath-Modells zur Analyse von Schlierenabbildungen}}}, doi = {{10.1515/teme-2015-0116}}, volume = {{83}}, year = {{2016}}, } @inbook{29, abstract = {{In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.}}, author = {{Agne, Andreas and Platzner, Marco and Plessl, Christian and Happe, Markus and Lübbers, Enno}}, booktitle = {{FPGAs for Software Programmers}}, editor = {{Koch, Dirk and Hannig, Frank and Ziener, Daniel}}, isbn = {{978-3-319-26406-6}}, pages = {{227--244}}, publisher = {{Springer International Publishing}}, title = {{{ReconOS}}}, doi = {{10.1007/978-3-319-26408-0_13}}, year = {{2016}}, } @inproceedings{31, author = {{Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}}, booktitle = {{Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}}, title = {{{Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}}}, year = {{2016}}, } @inproceedings{24, author = {{Kenter, Tobias and Plessl, Christian}}, booktitle = {{Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)}}, title = {{{Microdisk Cavity FDTD Simulation on FPGA using OpenCL}}}, year = {{2016}}, } @inproceedings{25, author = {{Lass, Michael and Kühne, Thomas and Plessl, Christian}}, booktitle = {{Workshop on Approximate Computing (AC)}}, title = {{{Using Approximate Computing in Scientific Codes}}}, year = {{2016}}, } @inproceedings{138, abstract = {{Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.}}, author = {{Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D. and Bolchini, Christina}}, booktitle = {{Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}}, pages = {{1--5}}, publisher = {{IEEE}}, title = {{{Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}}}, doi = {{10.1109/RTSI.2016.7740545}}, year = {{2016}}, } @inbook{156, abstract = {{Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, booktitle = {{Self-aware Computing Systems}}, pages = {{145--165}}, publisher = {{Springer International Publishing}}, title = {{{Self-aware Compute Nodes}}}, doi = {{10.1007/978-3-319-39675-0_8}}, year = {{2016}}, } @article{165, abstract = {{A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.}}, author = {{Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}}, issn = {{0045-7906}}, journal = {{Computers and Electrical Engineering}}, pages = {{91--111}}, publisher = {{Elsevier}}, title = {{{Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}}}, doi = {{10.1016/j.compeleceng.2016.04.021}}, volume = {{55}}, year = {{2016}}, } @inproceedings{168, abstract = {{The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.}}, author = {{Lösch, Achim and Beisel, Tobias and Kenter, Tobias and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)}}, pages = {{912--917}}, publisher = {{EDA Consortium / IEEE}}, title = {{{Performance-centric scheduling with task migration for a heterogeneous compute node in the data center}}}, year = {{2016}}, } @inproceedings{171, author = {{Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}}, booktitle = {{Workshop on Reconfigurable Computing (WRC)}}, title = {{{Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}}}, year = {{2016}}, }