@inproceedings{39494, author = {{Kanwar, Kelash and Mager, Thomas and Hilleringmann, Ulrich and Geneiss, Volker and Hedayat, Christian}}, booktitle = {{2014 IEEE RFID Technology and Applications Conference (RFID-TA)}}, publisher = {{IEEE}}, title = {{{Embedded UHF RFID tag design process for rubber transmission belt using 3D model}}}, doi = {{10.1109/rfid-ta.2014.6934208}}, year = {{2014}}, } @inproceedings{39486, author = {{Hangmann, Christian and Wullner, Ingo and Hedayat, Christian and Hilleringmann, Ulrich}}, booktitle = {{2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS)}}, publisher = {{IEEE}}, title = {{{Modeling and characterization of CP-PLL phase noise in presence of dead zone}}}, doi = {{10.1109/newcas.2014.6934054}}, year = {{2014}}, } @inproceedings{39518, author = {{Hilleringmann, Ulrich and Schonhoff, M. and Assion, F.}}, booktitle = {{2013 Africon}}, publisher = {{IEEE}}, title = {{{Titanium disilicide as hot side metallization layer for thermoelectric generators}}}, doi = {{10.1109/afrcon.2013.6757616}}, year = {{2014}}, } @article{42801, abstract = {{We exhibit a practical algorithm for solving the constructive membership problem for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R) is discrete and free, have been implemented in Magma for groups defined over real algebraic number fields.}}, author = {{Kirschmer, Markus and LEEDHAM-GREEN, CHARLES}}, issn = {{0017-0895}}, journal = {{Glasgow Mathematical Journal}}, keywords = {{General Mathematics}}, number = {{1}}, pages = {{173--180}}, publisher = {{Cambridge University Press (CUP)}}, title = {{{Computing with subgroups of the modular group }}}, doi = {{10.1017/s0017089514000202}}, volume = {{57}}, year = {{2014}}, } @article{42794, abstract = {{We exhibit a practical algorithm for solving the constructive membership problem for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R) is discrete and free, have been implemented in Magma for groups defined over real algebraic number fields.}}, author = {{Eick, B. and Kirschmer, Markus and Leedham-Green, C.}}, issn = {{1461-1570}}, journal = {{LMS Journal of Computation and Mathematics}}, keywords = {{Computational Theory and Mathematics, General Mathematics}}, number = {{1}}, pages = {{345--359}}, publisher = {{Wiley}}, title = {{{The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R)}}}, doi = {{10.1112/s1461157014000047}}, volume = {{17}}, year = {{2014}}, } @inproceedings{3939, abstract = {{Optical and infrared antennas provide a promising way to couple photons in and out of nanoscale structures. As counterpart to conventional radio antennas, they are able to increase optical felds in sub-wavelength volumes, to enhance excitation and emission of quantum emitters or to direct light, radiated by quantum emitters. The directed emission of these antennas has been mainly pursued by surface plasmon based devices, e.g. Yagi-Uda like antennas, which are rather complicated due to the coupling of several metallic particles. Also, like all metallic structures in optical or infrared regime, these devices are very sensitive to fabrication tolerances and are affected by strong losses. It has been shown recently, that such directed emission can be accomplished by dielectric materials as well. In this paper we present an optimization of nanoscopic antennas in the near infrared regime starting from a metallic Yagi-Uda structure. The optimization is done via a particle-swarm algorithm, using full time domain finite integration simulations to obtain the characteristics of the investigated structure, also taking into account substrates. Furthermore we present a dielectric antenna, which performs even better, due to the lack of losses by an appropriate choice of the dielectric material. These antennas are robust concerning fabrication tolerances and can be realized with different materials for both the antenna and the substrate, without using high index materials.}}, author = {{Hildebrandt, Andre and Reichelt, Matthias and Meier, Torsten and Förstner, Jens}}, booktitle = {{Ultrafast Phenomena and Nanophotonics XVIII}}, editor = {{Betz, Markus and Elezzabi, Abdulhakem Y. and Song, Jin-Joo and Tsen, Kong-Thon}}, keywords = {{tet_topic_opticalantenna}}, pages = {{89841G--8941G--6}}, publisher = {{SPIE}}, title = {{{Engineering plasmonic and dielectric directional nanoantennas}}}, doi = {{10.1117/12.2036588}}, volume = {{8984}}, year = {{2014}}, } @article{44341, author = {{Burban, Igor and Kreußler, B.}}, journal = {{Mathematische Nachrichten}}, number = {{2–3}}, pages = {{173–183}}, title = {{{Analytic moduli spaces of simple sheaves on families of integral curves}}}, volume = {{287}}, year = {{2014}}, } @inproceedings{45686, author = {{Bruns, Julia and Walter-Laager, C. and Pfiffner, M. and Schwarz, J.}}, booktitle = {{Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik}}, editor = {{Walter-Laager, C. and Pfiffner, M. and Fasseing-Heim, K.}}, pages = {{132–168}}, publisher = {{hep Verlag}}, title = {{{Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags}}}, year = {{2014}}, } @book{36474, author = {{Bruns, Julia}}, publisher = {{Waxmann}}, title = {{{Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik}}}, volume = {{21}}, year = {{2014}}, } @inproceedings{36533, author = {{Bruns, Julia and Eichen, Lars}}, booktitle = {{Beiträge zum Mathematikunterricht 2014}}, editor = {{Roth, Jürgen and Ames, Judith}}, location = {{Koblenz}}, pages = {{277--280}}, publisher = {{WTM-Verlag}}, title = {{{Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen}}}, doi = {{10.17877/DE290R-5105}}, year = {{2014}}, } @article{46266, author = {{Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}}, issn = {{0018-9340}}, journal = {{IEEE Transactions on Computers}}, keywords = {{Computational Theory and Mathematics, Hardware and Architecture, Theoretical Computer Science, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}}}, doi = {{10.1109/tc.2014.2329687}}, year = {{2014}}, } @inproceedings{46268, author = {{Mohammadi, Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{An off-line MDSI interconnect BIST incorporated in BS 1149.1}}}, doi = {{10.1109/ets.2014.6847847}}, year = {{2014}}, } @inproceedings{46267, author = {{Sadeghi-Kohan, Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi, Zainalabedin}}, booktitle = {{2014 19th IEEE European Test Symposium (ETS)}}, publisher = {{IEEE}}, title = {{{Improving polynomial datapath debugging with HEDs}}}, doi = {{10.1109/ets.2014.6847797}}, year = {{2014}}, } @inbook{335, abstract = {{Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf.}}, author = {{Platzner, Marco and Plessl, Christian}}, booktitle = {{Logiken strukturbildender Prozesse: Automatismen}}, editor = {{Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}}, isbn = {{978-3-7705-5730-1}}, pages = {{123--144}}, publisher = {{Wilhelm Fink}}, title = {{{Verschiebungen an der Grenze zwischen Hardware und Software}}}, year = {{2014}}, } @inproceedings{388, abstract = {{In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.}}, author = {{Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}}, booktitle = {{Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}}, pages = {{144--155}}, publisher = {{Springer International Publishing}}, title = {{{Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}}}, doi = {{10.1007/978-3-319-05960-0_13}}, volume = {{8405}}, year = {{2014}}, } @article{363, abstract = {{Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.}}, author = {{Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}}, journal = {{Microprocessors and Microsystems}}, number = {{8, Part B}}, pages = {{911--919}}, publisher = {{Elsevier}}, title = {{{Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}}}, doi = {{10.1016/j.micpro.2013.12.001}}, volume = {{38}}, year = {{2014}}, } @inproceedings{377, abstract = {{In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.}}, author = {{Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}}, booktitle = {{Proceedings of Field-Programmable Custom Computing Machines (FCCM)}}, keywords = {{coldboot}}, pages = {{222--229}}, publisher = {{IEEE}}, title = {{{Reconstructing AES Key Schedules from Decayed Memory with FPGAs}}}, doi = {{10.1109/FCCM.2014.67}}, year = {{2014}}, } @article{365, abstract = {{Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.}}, author = {{Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}}, journal = {{ACM Transactions on Reconfigurable Technology and Systems (TRETS)}}, number = {{2}}, publisher = {{ACM}}, title = {{{Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}}}, doi = {{10.1145/2617596}}, volume = {{7}}, year = {{2014}}, } @article{328, abstract = {{The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications}}, author = {{Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}}, journal = {{IEEE Micro}}, number = {{1}}, pages = {{60--71}}, publisher = {{IEEE}}, title = {{{ReconOS - An Operating System Approach for Reconfigurable Computing}}}, doi = {{10.1109/MM.2013.110}}, volume = {{34}}, year = {{2014}}, } @inproceedings{1778, author = {{C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}}, booktitle = {{Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}}, pages = {{142--149}}, publisher = {{IEEE}}, title = {{{Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}}}, doi = {{10.1109/ISPA.2014.27}}, year = {{2014}}, }