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Conf. on Field Programmable Logic and Applications (FPL). ; 2014:1-4. doi:10.1109/FPL.2014.6927437","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL) (pp. 1–4). https://doi.org/10.1109/FPL.2014.6927437","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 1–4, 2014. https://doi.org/10.1109/FPL.2014.6927437.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={10.1109/FPL.2014.6927437}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4, doi:10.1109/FPL.2014.6927437."},"doi":"10.1109/FPL.2014.6927437","_id":"10674","date_updated":"2022-01-06T06:50:49Z"},{"date_updated":"2022-01-06T06:50:49Z","_id":"10677","doi":"10.1109/ICES.2014.7008719","page":"31-37","year":"2014","citation":{"mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37."},"type":"conference","language":[{"iso":"eng"}],"title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","user_id":"3118","publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"department":[{"_id":"78"}],"author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","first_name":"Paul","last_name":"Kaufmann"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2019-07-10T11:23:00Z","status":"public"},{"date_updated":"2022-01-06T06:50:49Z","_id":"10679","language":[{"iso":"eng"}],"supervisor":[{"first_name":"Alexander","full_name":"Boschmann, Alexander","last_name":"Boschmann"}],"year":"2014","citation":{"short":"F. König, EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese, Paderborn University, 2014.","ieee":"F. König, EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University, 2014.","chicago":"König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","apa":"König, F. (2014). EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese. Paderborn University.","ama":"König F. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University; 2014.","mla":"König, Fabian. EMG-Basierte Simultane Und Proportionale Online-Steuerung Einer Virtuellen Prothese. Paderborn University, 2014.","bibtex":"@book{König_2014, title={EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese}, publisher={Paderborn University}, author={König, Fabian}, year={2014} }"},"type":"bachelorsthesis","user_id":"3118","title":"EMG-basierte simultane und proportionale Online-Steuerung einer virtuellen Prothese","department":[{"_id":"78"}],"author":[{"full_name":"König, Fabian","first_name":"Fabian","last_name":"König"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:23:20Z","status":"public"},{"department":[{"_id":"78"}],"author":[{"last_name":"Koch","full_name":"Koch, Benjamin","first_name":"Benjamin"}],"publisher":"Paderborn University","date_created":"2019-07-10T11:38:27Z","status":"public","title":"Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA","user_id":"3118","type":"mastersthesis","citation":{"mla":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","bibtex":"@book{Koch_2014, title={Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA}, publisher={Paderborn University}, author={Koch, Benjamin}, year={2014} }","apa":"Koch, B. (2014). Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University.","ama":"Koch B. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University; 2014.","chicago":"Koch, Benjamin. Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","ieee":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA. Paderborn University, 2014.","short":"B. Koch, Hardware Acceleration of Mechatronic Controllers on a Zynq Platform FPGA, Paderborn University, 2014."},"year":"2014","supervisor":[{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"language":[{"iso":"eng"}],"_id":"10701","date_updated":"2022-01-06T06:50:50Z"},{"date_created":"2019-07-10T11:48:26Z","status":"public","department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"full_name":"Mittendorf, Robert","first_name":"Robert","last_name":"Mittendorf"}],"title":"Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs","user_id":"3118","year":"2014","citation":{"ieee":"R. Mittendorf, Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University, 2014.","short":"R. Mittendorf, Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs, Paderborn University, 2014.","mla":"Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014.","bibtex":"@book{Mittendorf_2014, title={Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs}, publisher={Paderborn University}, author={Mittendorf, Robert}, year={2014} }","apa":"Mittendorf, R. (2014). Advanced AES-key recovery from decayed RAM using multi-threading and FPGAs. Paderborn University.","ama":"Mittendorf R. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University; 2014.","chicago":"Mittendorf, Robert. Advanced AES-Key Recovery from Decayed RAM Using Multi-Threading and FPGAs. Paderborn University, 2014."},"type":"mastersthesis","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:50Z","_id":"10715"},{"department":[{"_id":"78"}],"publisher":"Paderborn University","author":[{"last_name":"Rüthing","first_name":"Christoph","full_name":"Rüthing, Christoph"}],"date_created":"2019-07-10T11:58:05Z","status":"public","user_id":"3118","title":"The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores","language":[{"iso":"eng"}],"year":"2014","type":"bachelorsthesis","citation":{"ieee":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","short":"C. Rüthing, The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores, Paderborn University, 2014.","mla":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014.","bibtex":"@book{Rüthing_2014, title={The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores}, publisher={Paderborn University}, author={Rüthing, Christoph}, year={2014} }","apa":"Rüthing, C. (2014). The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University.","ama":"Rüthing C. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University; 2014.","chicago":"Rüthing, Christoph. The Xilinx Zynq Architecture as a Platform for Reconfigurable Heterogeneous Multi-Cores. Paderborn University, 2014."},"date_updated":"2022-01-06T06:50:50Z","_id":"10732"},{"year":"2014","citation":{"mla":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Logos Verlag Berlin GmbH, 2014.","bibtex":"@book{Schäfers_2014, place={Berlin}, title={Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go}, publisher={Logos Verlag Berlin GmbH}, author={Schäfers, Lars}, year={2014} }","chicago":"Schäfers, Lars. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","ama":"Schäfers L. Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH; 2014.","apa":"Schäfers, L. (2014). Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH.","ieee":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go. Berlin: Logos Verlag Berlin GmbH, 2014.","short":"L. Schäfers, Parallel Monte-Carlo Tree Search for HPC Systems and Its Application to Computer Go, Logos Verlag Berlin GmbH, Berlin, 2014."},"type":"dissertation","page":"133","language":[{"iso":"eng"}],"supervisor":[{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"_id":"10733","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Schäfers","first_name":"Lars","full_name":"Schäfers, Lars"}],"publisher":"Logos Verlag Berlin GmbH","department":[{"_id":"78"}],"publication_status":"published","publication_identifier":{"isbn":["978-3-8325-3748-7"]},"status":"public","date_created":"2019-07-10T11:58:06Z","place":"Berlin","abstract":[{"text":"Monte-Carlo Tree Search (MCTS) is a class of simulation-based search algorithms. It brought about great success in the past few years regarding the evaluation of deterministic two-player games such as the Asian board game Go.\r\n\r\nIn this thesis, we present a parallelization of the most popular MCTS variant for large HPC compute clusters that efficiently shares a single game tree representation in a distributed memory environment and scales up to 128 compute nodes and 2048 cores. It is hereby one of the most powerful MCTS parallelizations to date.\r\n\r\nIn order to measure the impact of our parallelization on the search quality and remain comparable to the most advanced MCTS implementations to date, we implemented it in a state-of-the-art Go engine Gomorra, making it competitive with the strongest Go programs in the world.\r\n\r\nWe further present an empirical comparison of different Bayesian ranking systems when being used for predicting expert moves for the game of Go and introduce a novel technique for automated detection and analysis of evaluation uncertainties that show up during MCTS searches.","lang":"eng"}],"title":"Parallel Monte-Carlo Tree Search for HPC Systems and its Application to Computer Go","user_id":"3118"}]