[{"publication":"2013 Africon","citation":{"mla":"Hilleringmann, Ulrich, et al. “Titanium Disilicide as Hot Side Metallization Layer for Thermoelectric Generators.” <i>2013 Africon</i>, IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">10.1109/afrcon.2013.6757616</a>.","bibtex":"@inproceedings{Hilleringmann_Schonhoff_Assion_2014, title={Titanium disilicide as hot side metallization layer for thermoelectric generators}, DOI={<a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">10.1109/afrcon.2013.6757616</a>}, booktitle={2013 Africon}, publisher={IEEE}, author={Hilleringmann, Ulrich and Schonhoff, M. and Assion, F.}, year={2014} }","ama":"Hilleringmann U, Schonhoff M, Assion F. Titanium disilicide as hot side metallization layer for thermoelectric generators. In: <i>2013 Africon</i>. IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">10.1109/afrcon.2013.6757616</a>","ieee":"U. Hilleringmann, M. Schonhoff, and F. Assion, “Titanium disilicide as hot side metallization layer for thermoelectric generators,” 2014, doi: <a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">10.1109/afrcon.2013.6757616</a>.","apa":"Hilleringmann, U., Schonhoff, M., &#38; Assion, F. (2014). Titanium disilicide as hot side metallization layer for thermoelectric generators. <i>2013 Africon</i>. <a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">https://doi.org/10.1109/afrcon.2013.6757616</a>","chicago":"Hilleringmann, Ulrich, M. Schonhoff, and F. Assion. “Titanium Disilicide as Hot Side Metallization Layer for Thermoelectric Generators.” In <i>2013 Africon</i>. IEEE, 2014. <a href=\"https://doi.org/10.1109/afrcon.2013.6757616\">https://doi.org/10.1109/afrcon.2013.6757616</a>.","short":"U. Hilleringmann, M. Schonhoff, F. Assion, in: 2013 Africon, IEEE, 2014."},"type":"conference","department":[{"_id":"59"}],"date_created":"2023-01-24T11:53:18Z","date_updated":"2023-03-22T10:18:06Z","publication_status":"published","title":"Titanium disilicide as hot side metallization layer for thermoelectric generators","year":"2014","status":"public","author":[{"id":"20179","full_name":"Hilleringmann, Ulrich","last_name":"Hilleringmann","first_name":"Ulrich"},{"full_name":"Schonhoff, M.","first_name":"M.","last_name":"Schonhoff"},{"first_name":"F.","last_name":"Assion","full_name":"Assion, F."}],"doi":"10.1109/afrcon.2013.6757616","user_id":"20179","language":[{"iso":"eng"}],"_id":"39518","publisher":"IEEE"},{"doi":"10.1017/s0017089514000202","language":[{"iso":"eng"}],"date_updated":"2023-04-04T07:55:16Z","publication_status":"published","intvolume":"        57","title":"Computing with subgroups of the modular group ","year":"2014","author":[{"first_name":"Markus","last_name":"Kirschmer","full_name":"Kirschmer, Markus","id":"82258"},{"last_name":"LEEDHAM-GREEN","first_name":"CHARLES","full_name":"LEEDHAM-GREEN, CHARLES"}],"publication_identifier":{"issn":["0017-0895","1469-509X"]},"keyword":["General Mathematics"],"type":"journal_article","department":[{"_id":"102"}],"date_created":"2023-03-07T08:47:42Z","abstract":[{"text":"We exhibit a practical algorithm for solving the constructive membership problem for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R) is discrete and free, have been implemented in Magma for groups defined over real algebraic number fields.","lang":"eng"}],"extern":"1","publication":"Glasgow Mathematical Journal","issue":"1","user_id":"93826","volume":57,"page":"173-180","_id":"42801","publisher":"Cambridge University Press (CUP)","status":"public","citation":{"ama":"Kirschmer M, LEEDHAM-GREEN C. Computing with subgroups of the modular group . <i>Glasgow Mathematical Journal</i>. 2014;57(1):173-180. doi:<a href=\"https://doi.org/10.1017/s0017089514000202\">10.1017/s0017089514000202</a>","bibtex":"@article{Kirschmer_LEEDHAM-GREEN_2014, title={Computing with subgroups of the modular group }, volume={57}, DOI={<a href=\"https://doi.org/10.1017/s0017089514000202\">10.1017/s0017089514000202</a>}, number={1}, journal={Glasgow Mathematical Journal}, publisher={Cambridge University Press (CUP)}, author={Kirschmer, Markus and LEEDHAM-GREEN, CHARLES}, year={2014}, pages={173–180} }","mla":"Kirschmer, Markus, and CHARLES LEEDHAM-GREEN. “Computing with Subgroups of the Modular Group .” <i>Glasgow Mathematical Journal</i>, vol. 57, no. 1, Cambridge University Press (CUP), 2014, pp. 173–80, doi:<a href=\"https://doi.org/10.1017/s0017089514000202\">10.1017/s0017089514000202</a>.","chicago":"Kirschmer, Markus, and CHARLES LEEDHAM-GREEN. “Computing with Subgroups of the Modular Group .” <i>Glasgow Mathematical Journal</i> 57, no. 1 (2014): 173–80. <a href=\"https://doi.org/10.1017/s0017089514000202\">https://doi.org/10.1017/s0017089514000202</a>.","short":"M. Kirschmer, C. LEEDHAM-GREEN, Glasgow Mathematical Journal 57 (2014) 173–180.","apa":"Kirschmer, M., &#38; LEEDHAM-GREEN, C. (2014). Computing with subgroups of the modular group . <i>Glasgow Mathematical Journal</i>, <i>57</i>(1), 173–180. <a href=\"https://doi.org/10.1017/s0017089514000202\">https://doi.org/10.1017/s0017089514000202</a>","ieee":"M. Kirschmer and C. LEEDHAM-GREEN, “Computing with subgroups of the modular group ,” <i>Glasgow Mathematical Journal</i>, vol. 57, no. 1, pp. 173–180, 2014, doi: <a href=\"https://doi.org/10.1017/s0017089514000202\">10.1017/s0017089514000202</a>."}},{"issue":"1","publication":"LMS Journal of Computation and Mathematics","abstract":[{"lang":"eng","text":"We exhibit a practical algorithm for solving the constructive membership problem for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R) is discrete and free, have been implemented in Magma for groups defined over real algebraic number fields."}],"extern":"1","date_created":"2023-03-07T08:30:15Z","keyword":["Computational Theory and Mathematics","General Mathematics"],"type":"journal_article","department":[{"_id":"102"}],"title":"The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R)","year":"2014","publication_identifier":{"issn":["1461-1570"]},"author":[{"full_name":"Eick, B.","last_name":"Eick","first_name":"B."},{"last_name":"Kirschmer","first_name":"Markus","full_name":"Kirschmer, Markus","id":"82258"},{"full_name":"Leedham-Green, C.","first_name":"C.","last_name":"Leedham-Green"}],"date_updated":"2023-04-04T09:31:17Z","publication_status":"published","intvolume":"        17","language":[{"iso":"eng"}],"doi":"10.1112/s1461157014000047","citation":{"ama":"Eick B, Kirschmer M, Leedham-Green C. The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R). <i>LMS Journal of Computation and Mathematics</i>. 2014;17(1):345-359. doi:<a href=\"https://doi.org/10.1112/s1461157014000047\">10.1112/s1461157014000047</a>","bibtex":"@article{Eick_Kirschmer_Leedham-Green_2014, title={The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R)}, volume={17}, DOI={<a href=\"https://doi.org/10.1112/s1461157014000047\">10.1112/s1461157014000047</a>}, number={1}, journal={LMS Journal of Computation and Mathematics}, publisher={Wiley}, author={Eick, B. and Kirschmer, Markus and Leedham-Green, C.}, year={2014}, pages={345–359} }","mla":"Eick, B., et al. “The Constructive Membership Problem for Discrete Free Subgroups of Rank 2 of SL₂(R).” <i>LMS Journal of Computation and Mathematics</i>, vol. 17, no. 1, Wiley, 2014, pp. 345–59, doi:<a href=\"https://doi.org/10.1112/s1461157014000047\">10.1112/s1461157014000047</a>.","short":"B. Eick, M. Kirschmer, C. Leedham-Green, LMS Journal of Computation and Mathematics 17 (2014) 345–359.","chicago":"Eick, B., Markus Kirschmer, and C. Leedham-Green. “The Constructive Membership Problem for Discrete Free Subgroups of Rank 2 of SL₂(R).” <i>LMS Journal of Computation and Mathematics</i> 17, no. 1 (2014): 345–59. <a href=\"https://doi.org/10.1112/s1461157014000047\">https://doi.org/10.1112/s1461157014000047</a>.","apa":"Eick, B., Kirschmer, M., &#38; Leedham-Green, C. (2014). The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R). <i>LMS Journal of Computation and Mathematics</i>, <i>17</i>(1), 345–359. <a href=\"https://doi.org/10.1112/s1461157014000047\">https://doi.org/10.1112/s1461157014000047</a>","ieee":"B. Eick, M. Kirschmer, and C. Leedham-Green, “The constructive membership problem for discrete free subgroups of rank 2 of SL₂(R),” <i>LMS Journal of Computation and Mathematics</i>, vol. 17, no. 1, pp. 345–359, 2014, doi: <a href=\"https://doi.org/10.1112/s1461157014000047\">10.1112/s1461157014000047</a>."},"status":"public","page":"345-359","publisher":"Wiley","_id":"42794","user_id":"93826","volume":17},{"year":"2014","title":"Engineering plasmonic and dielectric directional nanoantennas","author":[{"full_name":"Hildebrandt, Andre","last_name":"Hildebrandt","first_name":"Andre"},{"id":"138","first_name":"Matthias","last_name":"Reichelt","full_name":"Reichelt, Matthias"},{"orcid":"0000-0001-8864-2072","first_name":"Torsten","last_name":"Meier","full_name":"Meier, Torsten","id":"344"},{"orcid":"0000-0001-7059-9862","first_name":"Jens","last_name":"Förstner","full_name":"Förstner, Jens","id":"158"}],"publication_status":"published","date_updated":"2023-04-16T22:09:25Z","intvolume":"      8984","series_title":"SPIE Proceedings","language":[{"iso":"eng"}],"doi":"10.1117/12.2036588","publication":"Ultrafast Phenomena and Nanophotonics XVIII","abstract":[{"lang":"eng","text":"Optical and infrared antennas provide a promising way to couple photons in and out of nanoscale structures. As\r\ncounterpart to conventional radio antennas, they are able to increase optical felds in sub-wavelength volumes,\r\nto enhance excitation and emission of quantum emitters or to direct light, radiated by quantum emitters. The\r\ndirected emission of these antennas has been mainly pursued by surface plasmon based devices, e.g. Yagi-Uda\r\nlike antennas, which are rather complicated due to the coupling of several metallic particles. Also, like all metallic\r\nstructures in optical or infrared regime, these devices are very sensitive to fabrication tolerances and are affected\r\nby strong losses. It has been shown recently, that such directed emission can be accomplished by dielectric\r\nmaterials as well.\r\nIn this paper we present an optimization of nanoscopic antennas in the near infrared regime starting from a\r\nmetallic Yagi-Uda structure. The optimization is done via a particle-swarm algorithm, using full time domain\r\nfinite integration simulations to obtain the characteristics of the investigated structure, also taking into account\r\nsubstrates. Furthermore we present a dielectric antenna, which performs even better, due to the lack of losses\r\nby an appropriate choice of the dielectric material. These antennas are robust concerning fabrication tolerances\r\nand can be realized with different materials for both the antenna and the substrate, without using high index\r\nmaterials."}],"file":[{"relation":"main_file","date_updated":"2018-08-20T10:10:25Z","file_name":"2014 Hildebrandt,Reichelt,Meier,Förstner_Engineering plasmonic and dielectric directional nanoantennas_SPIE OPTO.pdf","file_size":1744539,"access_level":"closed","file_id":"3940","success":1,"content_type":"application/pdf","creator":"hclaudia","date_created":"2018-08-20T10:10:25Z"}],"date_created":"2018-08-20T10:04:52Z","type":"conference","keyword":["tet_topic_opticalantenna"],"department":[{"_id":"61"},{"_id":"15"},{"_id":"293"},{"_id":"230"},{"_id":"170"}],"status":"public","has_accepted_license":"1","page":"89841G-8941G-6","publisher":"SPIE","_id":"3939","user_id":"49063","ddc":["530"],"volume":8984,"editor":[{"last_name":"Betz","first_name":"Markus","full_name":"Betz, Markus"},{"first_name":"Abdulhakem Y.","last_name":"Elezzabi","full_name":"Elezzabi, Abdulhakem Y."},{"last_name":"Song","first_name":"Jin-Joo","full_name":"Song, Jin-Joo"},{"first_name":"Kong-Thon","last_name":"Tsen","full_name":"Tsen, Kong-Thon"}],"file_date_updated":"2018-08-20T10:10:25Z","citation":{"ieee":"A. Hildebrandt, M. Reichelt, T. Meier, and J. Förstner, “Engineering plasmonic and dielectric directional nanoantennas,” in <i>Ultrafast Phenomena and Nanophotonics XVIII</i>, 2014, vol. 8984, pp. 89841G-8941G–6, doi: <a href=\"https://doi.org/10.1117/12.2036588\">10.1117/12.2036588</a>.","apa":"Hildebrandt, A., Reichelt, M., Meier, T., &#38; Förstner, J. (2014). Engineering plasmonic and dielectric directional nanoantennas. In M. Betz, A. Y. Elezzabi, J.-J. Song, &#38; K.-T. Tsen (Eds.), <i>Ultrafast Phenomena and Nanophotonics XVIII</i> (Vol. 8984, pp. 89841G-8941G – 6). SPIE. <a href=\"https://doi.org/10.1117/12.2036588\">https://doi.org/10.1117/12.2036588</a>","short":"A. Hildebrandt, M. Reichelt, T. Meier, J. Förstner, in: M. Betz, A.Y. Elezzabi, J.-J. Song, K.-T. Tsen (Eds.), Ultrafast Phenomena and Nanophotonics XVIII, SPIE, 2014, pp. 89841G-8941G–6.","chicago":"Hildebrandt, Andre, Matthias Reichelt, Torsten Meier, and Jens Förstner. “Engineering Plasmonic and Dielectric Directional Nanoantennas.” In <i>Ultrafast Phenomena and Nanophotonics XVIII</i>, edited by Markus Betz, Abdulhakem Y. Elezzabi, Jin-Joo Song, and Kong-Thon Tsen, 8984:89841G-8941G – 6. SPIE Proceedings. SPIE, 2014. <a href=\"https://doi.org/10.1117/12.2036588\">https://doi.org/10.1117/12.2036588</a>.","mla":"Hildebrandt, Andre, et al. “Engineering Plasmonic and Dielectric Directional Nanoantennas.” <i>Ultrafast Phenomena and Nanophotonics XVIII</i>, edited by Markus Betz et al., vol. 8984, SPIE, 2014, pp. 89841G-8941G – 6, doi:<a href=\"https://doi.org/10.1117/12.2036588\">10.1117/12.2036588</a>.","bibtex":"@inproceedings{Hildebrandt_Reichelt_Meier_Förstner_2014, series={SPIE Proceedings}, title={Engineering plasmonic and dielectric directional nanoantennas}, volume={8984}, DOI={<a href=\"https://doi.org/10.1117/12.2036588\">10.1117/12.2036588</a>}, booktitle={Ultrafast Phenomena and Nanophotonics XVIII}, publisher={SPIE}, author={Hildebrandt, Andre and Reichelt, Matthias and Meier, Torsten and Förstner, Jens}, editor={Betz, Markus and Elezzabi, Abdulhakem Y. and Song, Jin-Joo and Tsen, Kong-Thon}, year={2014}, pages={89841G-8941G–6}, collection={SPIE Proceedings} }","ama":"Hildebrandt A, Reichelt M, Meier T, Förstner J. Engineering plasmonic and dielectric directional nanoantennas. In: Betz M, Elezzabi AY, Song J-J, Tsen K-T, eds. <i>Ultrafast Phenomena and Nanophotonics XVIII</i>. Vol 8984. SPIE Proceedings. SPIE; 2014:89841G-8941G - 6. doi:<a href=\"https://doi.org/10.1117/12.2036588\">10.1117/12.2036588</a>"}},{"type":"journal_article","department":[{"_id":"602"}],"date_created":"2023-05-03T00:24:25Z","extern":"1","issue":"2–3","publication":"Mathematische Nachrichten","citation":{"apa":"Burban, I., &#38; Kreußler, B. (2014). Analytic moduli spaces of simple sheaves on families of integral curves. <i>Mathematische Nachrichten</i>, <i>287</i>(2–3), 173–183.","ieee":"I. Burban and B. Kreußler, “Analytic moduli spaces of simple sheaves on families of integral curves,” <i>Mathematische Nachrichten</i>, vol. 287, no. 2–3, pp. 173–183, 2014.","short":"I. Burban, B. Kreußler, Mathematische Nachrichten 287 (2014) 173–183.","chicago":"Burban, Igor, and B. Kreußler. “Analytic Moduli Spaces of Simple Sheaves on Families of Integral Curves.” <i>Mathematische Nachrichten</i> 287, no. 2–3 (2014): 173–183.","mla":"Burban, Igor, and B. Kreußler. “Analytic Moduli Spaces of Simple Sheaves on Families of Integral Curves.” <i>Mathematische Nachrichten</i>, vol. 287, no. 2–3, 2014, pp. 173–183.","ama":"Burban I, Kreußler B. Analytic moduli spaces of simple sheaves on families of integral curves. <i>Mathematische Nachrichten</i>. 2014;287(2–3):173–183.","bibtex":"@article{Burban_Kreußler_2014, title={Analytic moduli spaces of simple sheaves on families of integral curves}, volume={287}, number={2–3}, journal={Mathematische Nachrichten}, author={Burban, Igor and Kreußler, B.}, year={2014}, pages={173–183} }"},"user_id":"49063","volume":287,"page":"173–183","_id":"44341","language":[{"iso":"eng"}],"date_updated":"2023-05-07T01:42:01Z","publication_status":"published","intvolume":"       287","year":"2014","status":"public","title":"Analytic moduli spaces of simple sheaves on families of integral curves","author":[{"id":"72064","full_name":"Burban, Igor","first_name":"Igor","last_name":"Burban"},{"last_name":"Kreußler","first_name":"B.","full_name":"Kreußler, B."}]},{"type":"conference","department":[{"_id":"97"},{"_id":"611"}],"date_created":"2023-06-20T18:45:01Z","place":"Bern","extern":"1","publication":"Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik","citation":{"mla":"Bruns, Julia, et al. “Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags.” <i>Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik</i>, edited by C. Walter-Laager et al., hep Verlag, 2014, pp. 132–168.","bibtex":"@inproceedings{Bruns_Walter-Laager_Pfiffner_Schwarz_2014, place={Bern}, title={Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags}, booktitle={Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik}, publisher={hep Verlag}, author={Bruns, Julia and Walter-Laager, C. and Pfiffner, M. and Schwarz, J.}, editor={Walter-Laager, C. and Pfiffner, M. and Fasseing-Heim, K.}, year={2014}, pages={132–168} }","ama":"Bruns J, Walter-Laager C, Pfiffner M, Schwarz J. Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags. In: Walter-Laager C, Pfiffner M, Fasseing-Heim K, eds. <i>Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik</i>. hep Verlag; 2014:132–168.","ieee":"J. Bruns, C. Walter-Laager, M. Pfiffner, and J. Schwarz, “Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags,” in <i>Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik</i>, 2014, pp. 132–168.","apa":"Bruns, J., Walter-Laager, C., Pfiffner, M., &#38; Schwarz, J. (2014). Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags. In C. Walter-Laager, M. Pfiffner, &#38; K. Fasseing-Heim (Eds.), <i>Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik</i> (pp. 132–168). hep Verlag.","short":"J. Bruns, C. Walter-Laager, M. Pfiffner, J. Schwarz, in: C. Walter-Laager, M. Pfiffner, K. Fasseing-Heim (Eds.), Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik, hep Verlag, Bern, 2014, pp. 132–168.","chicago":"Bruns, Julia, C. Walter-Laager, M. Pfiffner, and J. Schwarz. “Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags.” In <i>Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik</i>, edited by C. Walter-Laager, M. Pfiffner, and K. Fasseing-Heim, 132–168. Bern: hep Verlag, 2014."},"user_id":"49063","editor":[{"first_name":"C.","last_name":"Walter-Laager","full_name":"Walter-Laager, C."},{"first_name":"M.","last_name":"Pfiffner","full_name":"Pfiffner, M."},{"first_name":"K.","last_name":"Fasseing-Heim","full_name":"Fasseing-Heim, K."}],"page":"132–168","publisher":"hep Verlag","_id":"45686","language":[{"iso":"ger"}],"publication_status":"published","date_updated":"2023-06-20T18:45:06Z","year":"2014","status":"public","title":"Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags","author":[{"id":"72183","full_name":"Bruns, Julia","first_name":"Julia","last_name":"Bruns","orcid":"https://orcid.org/0000-0002-6604-5864"},{"first_name":"C.","last_name":"Walter-Laager","full_name":"Walter-Laager, C."},{"full_name":"Pfiffner, M.","first_name":"M.","last_name":"Pfiffner"},{"last_name":"Schwarz","first_name":"J.","full_name":"Schwarz, J."}]},{"date_updated":"2023-06-20T19:18:57Z","publication_status":"published","intvolume":"        21","status":"public","title":"Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik","year":"2014","author":[{"id":"72183","orcid":"https://orcid.org/0000-0002-6604-5864","last_name":"Bruns","first_name":"Julia","full_name":"Bruns, Julia"}],"user_id":"49063","volume":21,"_id":"36474","series_title":"Empirische Studien zur Didaktik der Mathematik","publisher":"Waxmann","language":[{"iso":"ger"}],"extern":"1","citation":{"mla":"Bruns, Julia. <i>Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik</i>. Waxmann, 2014.","bibtex":"@book{Bruns_2014, place={Münster}, series={Empirische Studien zur Didaktik der Mathematik}, title={Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik}, volume={21}, publisher={Waxmann}, author={Bruns, Julia}, year={2014}, collection={Empirische Studien zur Didaktik der Mathematik} }","ama":"Bruns J. <i>Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik</i>. Vol 21. Waxmann; 2014.","ieee":"J. Bruns, <i>Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik</i>, vol. 21. Münster: Waxmann, 2014.","apa":"Bruns, J. (2014). <i>Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik</i> (Vol. 21). Waxmann.","chicago":"Bruns, Julia. <i>Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik</i>. Vol. 21. Empirische Studien zur Didaktik der Mathematik. Münster: Waxmann, 2014.","short":"J. Bruns, Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik, Waxmann, Münster, 2014."},"type":"book","department":[{"_id":"611"},{"_id":"97"}],"place":"Münster","date_created":"2023-01-12T15:10:14Z"},{"publication":"Beiträge zum Mathematikunterricht 2014","department":[{"_id":"97"},{"_id":"611"}],"type":"conference","date_created":"2023-01-13T09:00:17Z","file":[{"creator":"brunsj","date_created":"2023-01-13T09:00:12Z","date_updated":"2023-01-13T09:00:12Z","relation":"main_file","access_level":"open_access","file_size":1216795,"file_name":"BzMU14-4ES-Bruns-90.pdf","content_type":"application/pdf","file_id":"36534"}],"date_updated":"2023-06-28T08:27:21Z","author":[{"id":"72183","full_name":"Bruns, Julia","orcid":"https://orcid.org/0000-0002-6604-5864","first_name":"Julia","last_name":"Bruns"},{"full_name":"Eichen, Lars","last_name":"Eichen","first_name":"Lars"}],"title":"Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen","year":"2014","doi":"10.17877/DE290R-5105","language":[{"iso":"eng"}],"citation":{"mla":"Bruns, Julia, and Lars Eichen. “Adaptive Mathematische Förderung Im Elementarbereich - Empirische Ergebnisse Zum Didaktischen Handeln von Erzieherinnen.” <i>Beiträge Zum Mathematikunterricht 2014</i>, edited by Jürgen Roth and Judith Ames, WTM-Verlag, 2014, pp. 277–80, doi:<a href=\"https://doi.org/10.17877/DE290R-5105\">10.17877/DE290R-5105</a>.","ama":"Bruns J, Eichen L. Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen. In: Roth J, Ames J, eds. <i>Beiträge Zum Mathematikunterricht 2014</i>. WTM-Verlag; 2014:277-280. doi:<a href=\"https://doi.org/10.17877/DE290R-5105\">10.17877/DE290R-5105</a>","bibtex":"@inproceedings{Bruns_Eichen_2014, place={Münster}, title={Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen}, DOI={<a href=\"https://doi.org/10.17877/DE290R-5105\">10.17877/DE290R-5105</a>}, booktitle={Beiträge zum Mathematikunterricht 2014}, publisher={WTM-Verlag}, author={Bruns, Julia and Eichen, Lars}, editor={Roth, Jürgen and Ames, Judith}, year={2014}, pages={277–280} }","apa":"Bruns, J., &#38; Eichen, L. (2014). Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen. In J. Roth &#38; J. Ames (Eds.), <i>Beiträge zum Mathematikunterricht 2014</i> (pp. 277–280). WTM-Verlag. <a href=\"https://doi.org/10.17877/DE290R-5105\">https://doi.org/10.17877/DE290R-5105</a>","ieee":"J. Bruns and L. Eichen, “Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen,” in <i>Beiträge zum Mathematikunterricht 2014</i>, Koblenz, 2014, pp. 277–280, doi: <a href=\"https://doi.org/10.17877/DE290R-5105\">10.17877/DE290R-5105</a>.","short":"J. Bruns, L. Eichen, in: J. Roth, J. Ames (Eds.), Beiträge Zum Mathematikunterricht 2014, WTM-Verlag, Münster, 2014, pp. 277–280.","chicago":"Bruns, Julia, and Lars Eichen. “Adaptive Mathematische Förderung Im Elementarbereich - Empirische Ergebnisse Zum Didaktischen Handeln von Erzieherinnen.” In <i>Beiträge Zum Mathematikunterricht 2014</i>, edited by Jürgen Roth and Judith Ames, 277–80. Münster: WTM-Verlag, 2014. <a href=\"https://doi.org/10.17877/DE290R-5105\">https://doi.org/10.17877/DE290R-5105</a>."},"file_date_updated":"2023-01-13T09:00:12Z","oa":"1","place":"Münster","has_accepted_license":"1","conference":{"end_date":"14.03.2014","name":"48. Jahrestagung der Gesellschaft für Didaktik der Mathematik","start_date":"10.03.2014","location":"Koblenz"},"status":"public","editor":[{"full_name":"Roth, Jürgen","first_name":"Jürgen","last_name":"Roth"},{"full_name":"Ames, Judith","last_name":"Ames","first_name":"Judith"}],"user_id":"14931","ddc":["510"],"publisher":"WTM-Verlag","_id":"36533","page":"277-280"},{"user_id":"78614","doi":"10.1109/tc.2014.2329687","_id":"46266","language":[{"iso":"eng"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","page":"1-1","publication_status":"published","date_updated":"2023-08-02T11:32:37Z","publication_identifier":{"issn":["0018-9340"]},"author":[{"full_name":"Alizadeh, Bijan","last_name":"Alizadeh","first_name":"Bijan"},{"full_name":"Behnam, Payman","first_name":"Payman","last_name":"Behnam"},{"full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","id":"78614"}],"title":"A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs","year":"2014","status":"public","department":[{"_id":"48"}],"type":"journal_article","keyword":["Computational Theory and Mathematics","Hardware and Architecture","Theoretical Computer Science","Software"],"date_created":"2023-08-02T11:15:22Z","extern":"1","citation":{"bibtex":"@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs}, DOI={<a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>}, journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }","ama":"Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>. 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Sadeghi-Kohan, “A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs,” <i>IEEE Transactions on Computers</i>, pp. 1–1, 2014, doi: <a href=\"https://doi.org/10.1109/tc.2014.2329687\">10.1109/tc.2014.2329687</a>.","apa":"Alizadeh, B., Behnam, P., &#38; Sadeghi-Kohan, S. (2014). A Scalable Formal Debugging Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for RTL Datapath Designs. <i>IEEE Transactions on Computers</i>, 1–1. <a href=\"https://doi.org/10.1109/tc.2014.2329687\">https://doi.org/10.1109/tc.2014.2329687</a>"},"publication":"IEEE Transactions on Computers"},{"department":[{"_id":"48"}],"type":"conference","date_created":"2023-08-02T11:18:26Z","extern":"1","citation":{"short":"M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. 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An off-line MDSI interconnect BIST incorporated in BS 1149.1. <i>2014 19th IEEE European Test Symposium (ETS)</i>. <a href=\"https://doi.org/10.1109/ets.2014.6847847\">https://doi.org/10.1109/ets.2014.6847847</a>","bibtex":"@inproceedings{Mohammadi_Sadeghi-Kohan_Masoumi_Navabi_2014, title={An off-line MDSI interconnect BIST incorporated in BS 1149.1}, DOI={<a href=\"https://doi.org/10.1109/ets.2014.6847847\">10.1109/ets.2014.6847847</a>}, booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Mohammadi, Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin}, year={2014} }","ama":"Mohammadi M, Sadeghi-Kohan S, Masoumi N, Navabi Z. An off-line MDSI interconnect BIST incorporated in BS 1149.1. In: <i>2014 19th IEEE European Test Symposium (ETS)</i>. IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/ets.2014.6847847\">10.1109/ets.2014.6847847</a>","mla":"Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” <i>2014 19th IEEE European Test Symposium (ETS)</i>, IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/ets.2014.6847847\">10.1109/ets.2014.6847847</a>."},"publication":"2014 19th IEEE European Test Symposium (ETS)","user_id":"78614","doi":"10.1109/ets.2014.6847847","publisher":"IEEE","_id":"46268","language":[{"iso":"eng"}],"publication_status":"published","date_updated":"2023-08-02T11:32:48Z","author":[{"last_name":"Mohammadi","first_name":"Marzieh","full_name":"Mohammadi, Marzieh"},{"first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","id":"78614"},{"full_name":"Masoumi, Nasser","last_name":"Masoumi","first_name":"Nasser"},{"first_name":"Zainalabedin","last_name":"Navabi","full_name":"Navabi, Zainalabedin"}],"status":"public","year":"2014","title":"An off-line MDSI interconnect BIST incorporated in BS 1149.1"},{"_id":"46267","publisher":"IEEE","language":[{"iso":"eng"}],"user_id":"78614","doi":"10.1109/ets.2014.6847797","year":"2014","title":"Improving polynomial datapath debugging with HEDs","status":"public","author":[{"id":"78614","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh","last_name":"Sadeghi-Kohan"},{"full_name":"Behnam, Payman","last_name":"Behnam","first_name":"Payman"},{"first_name":"Bijan","last_name":"Alizadeh","full_name":"Alizadeh, Bijan"},{"full_name":"Fujita, Masahiro","last_name":"Fujita","first_name":"Masahiro"},{"full_name":"Navabi, Zainalabedin","first_name":"Zainalabedin","last_name":"Navabi"}],"publication_status":"published","date_updated":"2023-08-02T11:34:10Z","date_created":"2023-08-02T11:17:08Z","type":"conference","department":[{"_id":"48"}],"publication":"2014 19th IEEE European Test Symposium (ETS)","citation":{"apa":"Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., &#38; Navabi, Z. (2014). Improving polynomial datapath debugging with HEDs. <i>2014 19th IEEE European Test Symposium (ETS)</i>. <a href=\"https://doi.org/10.1109/ets.2014.6847797\">https://doi.org/10.1109/ets.2014.6847797</a>","mla":"Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with HEDs.” <i>2014 19th IEEE European Test Symposium (ETS)</i>, IEEE, 2014, doi:<a href=\"https://doi.org/10.1109/ets.2014.6847797\">10.1109/ets.2014.6847797</a>.","ieee":"S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving polynomial datapath debugging with HEDs,” 2014, doi: <a href=\"https://doi.org/10.1109/ets.2014.6847797\">10.1109/ets.2014.6847797</a>.","chicago":"Sadeghi-Kohan, Somayeh, Payman Behnam, Bijan Alizadeh, Masahiro Fujita, and Zainalabedin Navabi. “Improving Polynomial Datapath Debugging with HEDs.” In <i>2014 19th IEEE European Test Symposium (ETS)</i>. IEEE, 2014. <a href=\"https://doi.org/10.1109/ets.2014.6847797\">https://doi.org/10.1109/ets.2014.6847797</a>.","short":"S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014.","ama":"Sadeghi-Kohan S, Behnam P, Alizadeh B, Fujita M, Navabi Z. Improving polynomial datapath debugging with HEDs. In: <i>2014 19th IEEE European Test Symposium (ETS)</i>. IEEE; 2014. doi:<a href=\"https://doi.org/10.1109/ets.2014.6847797\">10.1109/ets.2014.6847797</a>","bibtex":"@inproceedings{Sadeghi-Kohan_Behnam_Alizadeh_Fujita_Navabi_2014, title={Improving polynomial datapath debugging with HEDs}, DOI={<a href=\"https://doi.org/10.1109/ets.2014.6847797\">10.1109/ets.2014.6847797</a>}, booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Sadeghi-Kohan, Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi, Zainalabedin}, year={2014} }"},"extern":"1"},{"file_date_updated":"2018-03-20T07:29:58Z","citation":{"ieee":"M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware und Software,” in <i>Logiken strukturbildender Prozesse: Automatismen</i>, J. Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink, 2014, pp. 123–144.","apa":"Platzner, M., &#38; Plessl, C. (2014). Verschiebungen an der Grenze zwischen Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, &#38; T. Kaerlein (Eds.), <i>Logiken strukturbildender Prozesse: Automatismen</i> (pp. 123–144). Wilhelm Fink.","mla":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.","bibtex":"@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen}, publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller, Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144}, collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }","short":"M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein (Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn, 2014, pp. 123–144.","ama":"Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software. In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. <i>Logiken strukturbildender Prozesse: Automatismen</i>. Schriftenreihe des Graduiertenkollegs “Automatismen.” Wilhelm Fink; 2014:123-144.","chicago":"Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen Hardware und Software.” In <i>Logiken strukturbildender Prozesse: Automatismen</i>, edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44. Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink, 2014."},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"}],"place":"Paderborn","status":"public","has_accepted_license":"1","page":"123-144","_id":"335","publisher":"Wilhelm Fink","user_id":"15278","ddc":["040"],"editor":[{"first_name":"Jörn","last_name":"Künsemöller","full_name":"Künsemöller, Jörn"},{"first_name":"Norber Otto","last_name":"Eke","full_name":"Eke, Norber Otto"},{"full_name":"Foit, Lioba","first_name":"Lioba","last_name":"Foit"},{"full_name":"Kaerlein, Timo","last_name":"Kaerlein","first_name":"Timo"}],"publication":"Logiken strukturbildender Prozesse: Automatismen","abstract":[{"lang":"eng","text":"Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung von neuen Forschungsrichtungen gef{\\\"u}hrt. In diesem Beitrag besch{\\\"a}ftigen wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\\\"a}ndige Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem Computersystem besser in Hardware und welche besser in Software realisiert werden sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\\\"u}hrt hat. Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze zwischen Hardware und Software w{\\\"a}hrend der Entwicklung eines Produktes statt, um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten Produkt hingegen k{\\\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption, dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware und Software autonom w{\\\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware eines Computers w{\\\"a}hrend der Laufzeit ver{\\\"a}ndert werden kann. Diese Technologie f{\\\"u}hrt zu einer durchl{\\\"a}ssigen Grenze zwischen Hardware und Software bzw. l{\\\"o}st sie die herk{\\\"o}mmliche Vorstellung einer festen Hardware und einer flexiblen Software damit auf."}],"file":[{"success":1,"content_type":"application/pdf","file_id":"1424","date_updated":"2018-03-20T07:29:58Z","relation":"main_file","file_size":2848154,"access_level":"closed","file_name":"335-2014_plessl_automatismen.pdf","date_created":"2018-03-20T07:29:58Z","creator":"florida"}],"date_created":"2017-10-17T12:41:57Z","type":"book_chapter","department":[{"_id":"518"},{"_id":"27"},{"_id":"78"}],"year":"2014","title":"Verschiebungen an der Grenze zwischen Hardware und Software","author":[{"id":"398","first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco"},{"id":"16153","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian"}],"publication_identifier":{"isbn":["978-3-7705-5730-1"]},"publication_status":"published","date_updated":"2023-09-26T13:32:49Z","language":[{"iso":"ger"}],"series_title":"Schriftenreihe des Graduiertenkollegs \"Automatismen\""},{"language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science (LNCS)","doi":"10.1007/978-3-319-05960-0_13","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","year":"2014","author":[{"id":"3145","first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias"},{"id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","last_name":"Vaz"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"}],"date_updated":"2023-09-26T13:34:08Z","intvolume":"      8405","file":[{"relation":"main_file","date_updated":"2018-03-20T07:02:02Z","file_name":"388-plessl14_arc.pdf","file_size":330193,"access_level":"closed","file_id":"1387","success":1,"content_type":"application/pdf","creator":"florida","date_created":"2018-03-20T07:02:02Z"}],"date_created":"2017-10-17T12:42:07Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"page":"144-155","publisher":"Springer International Publishing","_id":"388","ddc":["040"],"user_id":"15278","volume":8405,"status":"public","has_accepted_license":"1","place":"Cham","file_date_updated":"2018-03-20T07:02:02Z","citation":{"chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>."},"quality_controlled":"1","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}]},{"date_updated":"2023-09-26T13:33:06Z","intvolume":"        38","title":"Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators","year":"2014","author":[{"full_name":"Agne, Andreas","last_name":"Agne","first_name":"Andreas"},{"first_name":"Hendrik","last_name":"Hangmann","full_name":"Hangmann, Hendrik"},{"last_name":"Happe","first_name":"Markus","full_name":"Happe, Markus"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"}],"doi":"10.1016/j.micpro.2013.12.001","language":[{"iso":"eng"}],"abstract":[{"lang":"eng","text":"Due to the continuously shrinking device structures and increasing densities of FPGAs, thermal aspects have become the new focus for many research projects over the last years. Most researchers rely on temperature simulations to evaluate their novel thermal management techniques. However, these temperature simulations require a high computational effort if a detailed thermal model is used and their accuracies are often unclear. In contrast to simulations, the use of synthetic heat sources allows for experimental evaluation of temperature management methods. In this paper we investigate the creation of significant rises in temperature on modern FPGAs to enable future evaluation of thermal management techniques based on experiments. To that end, we have developed seven different heat-generating cores that use different subsets of FPGA resources. Our experimental results show that, according to external temperature probes connected to the FPGA’s heat sink, we can increase the temperature by an average of 81 !C. This corresponds to an average increase of 156.3 !C as measured by the built-in thermal diodes of our Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices."}],"publication":"Microprocessors and Microsystems","issue":"8, Part B","type":"journal_article","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"access_level":"closed","file_size":1499996,"file_name":"363-plessl13_micpro.pdf","date_updated":"2018-03-20T07:20:31Z","relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1408","creator":"florida","date_created":"2018-03-20T07:20:31Z"}],"date_created":"2017-10-17T12:42:02Z","has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","volume":38,"page":"911-919","publisher":"Elsevier","_id":"363","quality_controlled":"1","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"257906","_id":"31","name":"Engineering Proprioception in Computing Systems"}],"file_date_updated":"2018-03-20T07:20:31Z","citation":{"mla":"Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, Elsevier, 2014, pp. 911–19, doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","bibtex":"@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>}, number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco and Plessl, Christian}, year={2014}, pages={911–919} }","ama":"Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>. 2014;38(8, Part B):911-919. doi:<a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>","ieee":"A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” <i>Microprocessors and Microsystems</i>, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">10.1016/j.micpro.2013.12.001</a>.","apa":"Agne, A., Hangmann, H., Happe, M., Platzner, M., &#38; Plessl, C. (2014). Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. <i>Microprocessors and Microsystems</i>, <i>38</i>(8, Part B), 911–919. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>","short":"A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and Microsystems 38 (2014) 911–919.","chicago":"Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.” <i>Microprocessors and Microsystems</i> 38, no. 8, Part B (2014): 911–19. <a href=\"https://doi.org/10.1016/j.micpro.2013.12.001\">https://doi.org/10.1016/j.micpro.2013.12.001</a>."}},{"file_date_updated":"2018-03-20T07:14:20Z","citation":{"bibtex":"@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing AES Key Schedules from Decayed Memory with FPGAs}, DOI={<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>}, booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)}, publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian and Sorge, Christoph}, year={2014}, pages={222–229} }","ama":"Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from Decayed Memory with FPGAs. In: <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>. IEEE; 2014:222-229. doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>","mla":"Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, IEEE, 2014, pp. 222–29, doi:<a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","short":"H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.","chicago":"Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge. “Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–29. IEEE, 2014. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>.","ieee":"H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules from Decayed Memory with FPGAs,” in <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 2014, pp. 222–229, doi: <a href=\"https://doi.org/10.1109/FCCM.2014.67\">10.1109/FCCM.2014.67</a>.","apa":"Riebler, H., Kenter, T., Plessl, C., &#38; Sorge, C. (2014). Reconstructing AES Key Schedules from Decayed Memory with FPGAs. <i>Proceedings of Field-Programmable Custom Computing Machines (FCCM)</i>, 222–229. <a href=\"https://doi.org/10.1109/FCCM.2014.67\">https://doi.org/10.1109/FCCM.2014.67</a>"},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"page":"222-229","publisher":"IEEE","_id":"377","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1","file":[{"date_updated":"2018-03-20T07:14:20Z","relation":"main_file","file_size":1003907,"access_level":"closed","file_name":"377-FCCM14.pdf","content_type":"application/pdf","success":1,"file_id":"1397","creator":"florida","date_created":"2018-03-20T07:14:20Z"}],"date_created":"2017-10-17T12:42:05Z","type":"conference","keyword":["coldboot"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proceedings of Field-Programmable Custom Computing Machines (FCCM)","abstract":[{"text":"In this paper, we study how AES key schedules can be reconstructed from decayed memory. This operation is a crucial and time consuming operation when trying to break encryption systems with cold-boot attacks. In software, the reconstruction of the AES master key can be performed using a recursive, branch-and-bound tree-search algorithm that exploits redundancies in the key schedule for constraining the search space. In this work, we investigate how this branch-and-bound algorithm can be accelerated with FPGAs. We translated the recursive search procedure to a state machine with an explicit stack for each recursion level and create optimized datapaths to accelerate in particular the processing of the most frequently accessed tree levels. We support two different decay models, of which especially the more realistic non-idealized asymmetric decay model causes very high runtimes in software. Our implementation on a Maxeler dataflow computing system outperforms a software implementation for this model by up to 27x, which makes cold-boot attacks against AES practical even for high error rates.","lang":"eng"}],"language":[{"iso":"eng"}],"doi":"10.1109/FCCM.2014.67","year":"2014","title":"Reconstructing AES Key Schedules from Decayed Memory with FPGAs","author":[{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"id":"3145","first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian","id":"16153"},{"full_name":"Sorge, Christoph","last_name":"Sorge","first_name":"Christoph"}],"date_updated":"2023-09-26T13:33:50Z"},{"intvolume":"         7","date_updated":"2023-09-26T13:33:31Z","author":[{"full_name":"Agne, Andreas","first_name":"Andreas","last_name":"Agne"},{"first_name":"Markus","last_name":"Happe","full_name":"Happe, Markus"},{"last_name":"Lösch","first_name":"Achim","full_name":"Lösch, Achim","id":"43646"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"year":"2014","title":"Self-awareness as a Model for Designing and Operating Heterogeneous Multicores","doi":"10.1145/2617596","language":[{"iso":"eng"}],"article_number":"13","abstract":[{"text":"Self-aware computing is a paradigm for structuring and simplifying the design and operation of computing systems that face unprecedented levels of system dynamics and thus require novel forms of adaptivity. The generality of the paradigm makes it applicable to many types of computing systems and, previously, researchers started to introduce concepts of self-awareness to multicore architectures. In our work we build on a recent reference architectural framework as a model for self-aware computing and instantiate it for an FPGA-based heterogeneous multicore running the ReconOS reconfigurable architecture and operating system. After presenting the model for self-aware computing and ReconOS, we demonstrate with a case study how a multicore application built on the principle of self-awareness, autonomously adapts to changes in the workload and system state. Our work shows that the reference architectural framework as a model for self-aware computing can be practically applied and allows us to structure and simplify the design process, which is essential for designing complex future computing systems.","lang":"eng"}],"issue":"2","publication":"ACM Transactions on Reconfigurable Technology and Systems (TRETS)","department":[{"_id":"27"},{"_id":"78"},{"_id":"518"}],"type":"journal_article","date_created":"2017-10-17T12:42:03Z","file":[{"date_updated":"2018-03-20T07:19:19Z","relation":"main_file","file_size":916052,"access_level":"closed","file_name":"365-plessl14_trets_01.pdf","success":1,"content_type":"application/pdf","file_id":"1406","creator":"florida","date_created":"2018-03-20T07:19:19Z"}],"has_accepted_license":"1","status":"public","volume":7,"user_id":"15278","ddc":["040"],"_id":"365","publisher":"ACM","project":[{"name":"SFB 901","grant_number":"160364472","_id":"1"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1","citation":{"mla":"Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, 13, ACM, 2014, doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","ama":"Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>. 2014;7(2). doi:<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>","bibtex":"@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={<a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>}, number={213}, journal={ACM Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM}, author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian and Platzner, Marco}, year={2014} }","apa":"Agne, A., Happe, M., Lösch, A., Plessl, C., &#38; Platzner, M. (2014). Self-awareness as a Model for Designing and Operating Heterogeneous Multicores. <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, <i>7</i>(2), Article 13. <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>","ieee":"A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness as a Model for Designing and Operating Heterogeneous Multicores,” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i>, vol. 7, no. 2, Art. no. 13, 2014, doi: <a href=\"https://doi.org/10.1145/2617596\">10.1145/2617596</a>.","chicago":"Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner. “Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.” <i>ACM Transactions on Reconfigurable Technology and Systems (TRETS)</i> 7, no. 2 (2014). <a href=\"https://doi.org/10.1145/2617596\">https://doi.org/10.1145/2617596</a>.","short":"A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2014)."},"file_date_updated":"2018-03-20T07:19:19Z"},{"project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"quality_controlled":"1","citation":{"ama":"Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>. 2014;34(1):60-71. doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>","bibtex":"@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS - An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>}, number={1}, journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco and Plessl, Christian}, year={2014}, pages={60–71} }","mla":"Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i>, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:<a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>.","short":"A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl, IEEE Micro 34 (2014) 60–71.","chicago":"Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner, Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach for Reconfigurable Computing.” <i>IEEE Micro</i> 34, no. 1 (2014): 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>.","apa":"Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &#38; Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing. <i>IEEE Micro</i>, <i>34</i>(1), 60–71. <a href=\"https://doi.org/10.1109/MM.2013.110\">https://doi.org/10.1109/MM.2013.110</a>","ieee":"A. Agne <i>et al.</i>, “ReconOS - An Operating System Approach for Reconfigurable Computing,” <i>IEEE Micro</i>, vol. 34, no. 1, pp. 60–71, 2014, doi: <a href=\"https://doi.org/10.1109/MM.2013.110\">10.1109/MM.2013.110</a>."},"file_date_updated":"2018-03-20T07:31:40Z","has_accepted_license":"1","status":"public","volume":34,"ddc":["040"],"user_id":"15278","_id":"328","publisher":"IEEE","page":"60-71","abstract":[{"lang":"eng","text":"The ReconOS operating system for reconfigurable computing offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. The operating system interface allows hardware threads to interact with software threads using well-known mechanisms such as semaphores, mutexes, condition variables, and message queues. By semantically integrating hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications"}],"publication":"IEEE Micro","issue":"1","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"type":"journal_article","date_created":"2017-10-17T12:41:55Z","file":[{"content_type":"application/pdf","success":1,"file_id":"1426","date_updated":"2018-03-20T07:31:40Z","relation":"main_file","file_size":1877185,"access_level":"closed","file_name":"328-plessl14_micro_01.pdf","date_created":"2018-03-20T07:31:40Z","creator":"florida"}],"intvolume":"        34","date_updated":"2023-09-26T13:32:31Z","author":[{"first_name":"Andreas","last_name":"Agne","full_name":"Agne, Andreas"},{"full_name":"Happe, Markus","last_name":"Happe","first_name":"Markus"},{"last_name":"Keller","first_name":"Ariane","full_name":"Keller, Ariane"},{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"first_name":"Bernhard","last_name":"Plattner","full_name":"Plattner, Bernhard"},{"id":"398","last_name":"Platzner","first_name":"Marco","full_name":"Platzner, Marco"},{"full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","id":"16153"}],"year":"2014","title":"ReconOS - An Operating System Approach for Reconfigurable Computing","doi":"10.1109/MM.2013.110","language":[{"iso":"eng"}]},{"publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>"},"quality_controlled":"1","project":[{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"date_created":"2018-03-26T13:40:14Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","year":"2014","status":"public","author":[{"last_name":"C. Durelli","first_name":"Gianluca","full_name":"C. Durelli, Gianluca"},{"last_name":"Pogliani","first_name":"Marcello","full_name":"Pogliani, Marcello"},{"first_name":"Antonio","last_name":"Miele","full_name":"Miele, Antonio"},{"id":"16153","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","full_name":"Plessl, Christian"},{"id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler"},{"id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis","last_name":"Vaz"},{"full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio","first_name":"Marco"},{"full_name":"Bolchini, Cristiana","last_name":"Bolchini","first_name":"Cristiana"}],"date_updated":"2023-09-26T13:35:40Z","page":"142-149","publisher":"IEEE","_id":"1778","language":[{"iso":"eng"}],"doi":"10.1109/ISPA.2014.27","user_id":"15278"},{"page":"1-8","publisher":"IEEE","_id":"439","user_id":"15278","ddc":["040"],"status":"public","has_accepted_license":"1","file_date_updated":"2018-03-16T11:29:52Z","citation":{"mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8."},"quality_controlled":"1","project":[{"_id":"1","grant_number":"160364472","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","grant_number":"160364472","_id":"14"},{"name":"SFB 901 - Project Area C","_id":"4"},{"grant_number":"610996","_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures"}],"language":[{"iso":"eng"}],"doi":"10.1109/ReConFig.2014.7032509","title":"Deferring Accelerator Offloading Decisions to Application Runtime","year":"2014","author":[{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:37:02Z","file":[{"creator":"florida","date_created":"2018-03-16T11:29:52Z","file_size":557362,"access_level":"closed","file_name":"439-plessl14a_reconfig.pdf","date_updated":"2018-03-16T11:29:52Z","relation":"main_file","success":1,"content_type":"application/pdf","file_id":"1353"}],"date_created":"2017-10-17T12:42:17Z","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}]},{"quality_controlled":"1","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"_id":"14","grant_number":"160364472","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"file_date_updated":"2018-03-16T11:37:42Z","citation":{"chicago":"Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>.","short":"T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","ama":"Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy Stereo-Matching. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>","bibtex":"@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration of High Accuracy Stereo-Matching}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning and Plessl, Christian}, year={2014}, pages={1–8} }","mla":"Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>.","apa":"Kenter, T., Schmitz, H., &#38; Plessl, C. (2014). Kernel-Centric Acceleration of High Accuracy Stereo-Matching. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">https://doi.org/10.1109/ReConFig.2014.7032535</a>","ieee":"T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High Accuracy Stereo-Matching,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032535\">10.1109/ReConFig.2014.7032535</a>."},"has_accepted_license":"1","status":"public","ddc":["040"],"user_id":"15278","page":"1-8","publisher":"IEEE","_id":"406","abstract":[{"text":"Stereo-matching algorithms recently received a lot of attention from the FPGA acceleration community. Presented solutions range from simple, very resource efficient systems with modest matching quality for small embedded systems to sophisticated algorithms with several processing steps, implemented on big FPGAs. In order to achieve high throughput, most implementations strongly focus on pipelining and data reuse between different computation steps. This approach leads to high efficiency, but limits the supported computation patterns and due the high integration of the implementation, adaptions to the algorithm are difficult. In this work, we present a stereo-matching implementation, that starts by offloading individual kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA, data is stored off-chip in on-board memory of the FPGA accelerator card. This enables us to accelerate the AD-census algorithm with cross-based aggregation and scanline optimization for the first time without algorithmic changes and for up to full HD image dimensions. Analyzing throughput and bandwidth requirements, we outline some trade-offs that are involved with this approach, compared to tighter integration of more kernel loops into one design.","lang":"eng"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","type":"conference","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"file":[{"date_created":"2018-03-16T11:37:42Z","creator":"florida","file_id":"1366","success":1,"content_type":"application/pdf","relation":"main_file","date_updated":"2018-03-16T11:37:42Z","file_name":"406-ReConFig14.pdf","access_level":"closed","file_size":932852}],"date_created":"2017-10-17T12:42:11Z","date_updated":"2023-09-26T13:36:40Z","title":"Kernel-Centric Acceleration of High Accuracy Stereo-Matching","year":"2014","author":[{"full_name":"Kenter, Tobias","first_name":"Tobias","last_name":"Kenter","id":"3145"},{"first_name":"Henning","last_name":"Schmitz","full_name":"Schmitz, Henning"},{"id":"16153","full_name":"Plessl, Christian","first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"doi":"10.1109/ReConFig.2014.7032535","language":[{"iso":"eng"}]}]