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Sie führt die Anschlüsse über weitere Leiterbahnen zum Rand des Chips und wird dort zu Kontaktflecken (“Pads”) aufgeweitet, die als Anschluss für die Verbindungsdrähte zwischen Chip und Gehäuse oder zum Aufsetzen von Messsonden für die Parametererfassung zum Schaltungstest auf ungesägten Scheiben dienen."}],"doi":"10.1007/978-3-322-94119-0_8","title":"Metallisierung und Kontakte","author":[{"id":"20179","last_name":"Hilleringmann","full_name":"Hilleringmann, Ulrich","first_name":"Ulrich"}],"department":[{"_id":"59"}],"citation":{"chicago":"Hilleringmann, Ulrich. “Metallisierung Und Kontakte.” In <i>Silizium-Halbleitertechnologie</i>, 131–151. Wiesbaden: Vieweg+Teubner Verlag, 2002. <a href=\"https://doi.org/10.1007/978-3-322-94119-0_8\">https://doi.org/10.1007/978-3-322-94119-0_8</a>.","short":"U. Hilleringmann, in: Silizium-Halbleitertechnologie, Vieweg+Teubner Verlag, Wiesbaden, 2002, pp. 131–151.","ieee":"U. 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Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn, 2001.","bibtex":"@book{Schröder_2001, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, title={Balls into Bins: A Paradigm for Job Allocation, Data Distribution Processes, and Routing}, volume={89}, publisher={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn}, author={Schröder, Klaus}, year={2001}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn} }"},"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts, Paderborn","user_id":"5786","intvolume":"        89","supervisor":[{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","id":"15523"}],"title":"Balls into Bins: A Paradigm for Job Allocation, Data Distribution Processes, and Routing","author":[{"last_name":"Schröder","first_name":"Klaus","full_name":"Schröder, Klaus"}]},{"citation":{"apa":"Salzwedel, K., Hartmann, G., Wolff, C., &#38; Preis, R. (2001). Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN). In <i>Proceedings of the PDPTA 2001</i> (Vol. 1, pp. 463–470).","ama":"Salzwedel K, Hartmann G, Wolff C, Preis R. Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN). In: <i>Proceedings of the PDPTA 2001</i>. Vol 1. ; 2001:463-470.","chicago":"Salzwedel, Kay, Georg Hartmann, Carsten Wolff, and Robert Preis. “Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN).” In <i>Proceedings of the PDPTA 2001</i>, 1:463–70, 2001.","ieee":"K. Salzwedel, G. Hartmann, C. Wolff, and R. Preis, “Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN),” in <i>Proceedings of the PDPTA 2001</i>, 2001, vol. 1, pp. 463–470.","mla":"Salzwedel, Kay, et al. “Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN).” <i>Proceedings of the PDPTA 2001</i>, vol. 1, 2001, pp. 463–70.","bibtex":"@inproceedings{Salzwedel_Hartmann_Wolff_Preis_2001, title={Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN)}, volume={1}, booktitle={Proceedings of the PDPTA 2001}, author={Salzwedel, Kay and Hartmann, Georg and Wolff, Carsten and Preis, Robert}, year={2001}, pages={463–470} }","short":"K. Salzwedel, G. Hartmann, C. Wolff, R. Preis, in: Proceedings of the PDPTA 2001, 2001, pp. 463–470."},"user_id":"15415","department":[{"_id":"63"},{"_id":"70"}],"title":"Efficient Parallel Simulations of Pulse-Coded Neural Networks (PCNN)","author":[{"last_name":"Salzwedel","full_name":"Salzwedel, Kay","first_name":"Kay"},{"full_name":"Hartmann, Georg","first_name":"Georg","last_name":"Hartmann"},{"full_name":"Wolff, Carsten","first_name":"Carsten","last_name":"Wolff"},{"full_name":"Preis, Robert","first_name":"Robert","last_name":"Preis"}],"intvolume":"         1","_id":"19797","page":"463-470","volume":1,"date_updated":"2022-01-06T06:54:12Z","publication":"Proceedings of the PDPTA 2001","date_created":"2020-09-30T12:34:44Z","year":"2001","type":"conference","language":[{"iso":"eng"}],"status":"public"},{"page":"85-91","_id":"2428","date_updated":"2022-01-06T06:56:17Z","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","date_created":"2018-04-17T15:39:17Z","publisher":"CSREA Press","year":"2001","type":"conference","status":"public","citation":{"apa":"Plessl, C., &#38; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 85–91). CSREA Press.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2001:85-91.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2001, pp. 85–91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 85–91. CSREA Press, 2001.","bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2001, pp. 85–91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91."},"user_id":"24135","keyword":["minimum covering","accelerator","funding-sundance"],"department":[{"_id":"518"},{"_id":"78"}],"title":"Instance-Specific Accelerators for Minimum Covering","author":[{"orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian","last_name":"Plessl","id":"16153"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"abstract":[{"text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. ","lang":"eng"}]}]