Silicon Nanoparticles contacted by metal nanogaps for FET applications - Wolff, K; Hilleringmann, Ulrich

Nanometer Scale Electronic Device Integration Using Side-Wall Deposition and Etch-Back Technology - Hilleringmann, Ulrich; Assion, F.; Vidor, F. F.; Wirth, G. I. (Journal of Machine to Machine Communications)
Keywords: General Medicine

Application of side-wall deposition and etch-back technology for nanometer scale device integration - Hilleringmann, Ulrich; Vidor, F.F.; Assion, F. (Proceedings of the 2nd Pan African International Conference on Science, Computing and Telecommunications (PACT 2014))

Extended event-driven modeling of a ΣΔ-fractional-N PLL including non-ideal effects - Hangmann, Christian; Hedayat, Christian; Hilleringmann, Ulrich (2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS))

Fast and accurate event-driven simulation of a mixed-signal system using the example of a PLL - Hangmann, C; Hedayat, C; Hilleringmann, Ulrich (Proc. Int. Conf. Exhib. Integr. Issues Miniatured Syst.)

Vector bundles on plane cubic curves and the classical Yang-Baxter equation - Burban, Igor; Henrich, T. (Journal of the European Math. Society)

Mathematikbezogene Kompetenzentwicklung elementarpädagogischer Fachpersonen in Intensiv-Fortbildungen - Bruns, Julia; Eichen, L. (Beiträge zum Mathematikunterricht 2015)

Entwicklung eines videobasierten Instruments zur Erhebung von Handlungsfähigkeiten elementarpädagogischer Fachpersonen im mathematischen Bereich (VimaH) - Bruns, Julia; Eichen, L. (Entwicklung mathematischer Fähigkeiten von Kindern im Grundschulalter – Tagungsband des AK Grundschule in der GDM 2015)

Entwicklung eines videobasierten Instruments zur Erhebung mathematikdidaktischer Handlungskompetenzen elementarpädagogischer Fachpersonen - Bruns, Julia; Eichen, L. (Beiträge zum Mathematikunterricht 2015)

Adaptive Förderung zur Vorbereitung auf den Übergang vom Elementar- in den Primarbereich am Beispiel des Bereichs Mathematik - Bruns, Julia; Eichen, Lars (Frühe Bildung)
Die vorliegende quasi-experimentelle Querschnittsuntersuchung verfolgt das Ziel, adaptive Förderleistungen elementarpädagogischer Fachpersonen zu erfassen und Zusammenhänge mit anderen Komponenten elementarpädagogischer Arbeit aufzudecken. Im Zentrum steht die Frage: Welcher Zusammenhang zeigt sich zwischen der Beobachtungsintensität, den diagnostischen Fähigkeiten und der Qualität der adaptiven Förderpraxis im Elementarbereich? Fokussiert wird die adaptive Förderleistung einer Teilstichprobe mit n = 31 Fachpersonen in Bezug auf die Teilstichprobe von n = 62 Kinder. Dazu werden verschiedene Methoden auf Kinder- und Fachpersonenebene im Sinne eines mixed-methods Designs miteinander verknüpft (Mathematiktest ‚zahlenstark‘, standardisierte Beobachtung, standardisiertes Interview). Die Ergebnisse zeigen, dass keiner Fachperson eine optimale Förderung zweier Kinder gelingt. Im Hinblick auf den Übergang zwischen Elementar- und Primarbereich kann gefolgert werden, dass die Kinder unzureichend in ihren individuellen Bildungsprozessen begleitet werden.
Keywords: General Earth and Planetary Sciences; General Environmental Science

Aging in digital circuits and age monitoring: Object-oriented modeling and evaluation - Sadeghi-Kohan, Somayeh; Kamran, Arezoo; Forooghifar, Farnaz; Navabi, Zainalabedin (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling resulting in timing variations and consequently reliability challenges in digital circuits. Age monitoring methods can be used to predict and deal with the aging problem. Selecting appropriate locations for placement of hardware aging monitors is an important issue. In this work we propose a procedure for selection of appropriate internal nodes in combinational clouds between pipeline stages or combinational parts of a sequential circuit to place hardware monitors that can effectively provide aging information of various components of a modern digital system. In order to implement the node selection procedure, we propose an object-oriented model. Object-oriented model of a circuit along with a probabilistic and logical simulation engine that we have developed can effectively be used for implementation and also fast evaluation of the proposed node selection mechanism. The proposed object-oriented C+ + models can be integrated into a SystemC RTL model making it possible to perform mixed-level simulation, and integrated evaluation of a complete system. We have applied our proposed scheme to several processors including MIPS, ARM, ALPHA and MiniRISC and have looked at its effectiveness for these processors.

Online self adjusting progressive age monitoring of timing variations - Sadeghi-Kohan, Somayeh; Kamal, Mehdi; McNeil, John; Prinetto, Paolo; Navabi, Zain (2015 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS))
Transistor and interconnect wearout is accelerated with transistor scaling that results in timing variations. Progressive age measurement of a circuit can help a better prevention mechanism for reducing more aging. This requires age monitors that collect progressive age information of the circuit. This paper focuses on monitor structures for implementation of progressive age detection. The monitors are self-adjusting that they adjust themselves to detect progressive changes in the timing of a circuit. Furthermore, the monitors are designed for low hardware overhead, and certainty in reported timing changes.

Exploring Tradeoffs between Specialized Kernels and a Reusable Overlay in a Stereo-Matching Case Study - Kenter, Tobias; Schmitz, Henning; Plessl, Christian (International Journal of Reconfigurable Computing (IJRC))
FPGAs are known to permit huge gains in performance and efficiency for suitable applications but still require reduced design efforts and shorter development cycles for wider adoption. In this work, we compare the resulting performance of two design concepts that in different ways promise such increased productivity. As common starting point, we employ a kernel-centric design approach, where computational hotspots in an application are identified and individually accelerated on FPGA. By means of a complex stereo matching application, we evaluate two fundamentally different design philosophies and approaches for implementing the required kernels on FPGAs. In the first implementation approach, we designed individually specialized data flow kernels in a spatial programming language for a Maxeler FPGA platform; in the alternative design approach, we target a vector coprocessor with large vector lengths, which is implemented as a form of programmable overlay on the application FPGAs of a Convey HC-1. We assess both approaches in terms of overall system performance, raw kernel performance, and performance relative to invested resources. After compensating for the effects of the underlying hardware platforms, the specialized dataflow kernels on the Maxeler platform are around 3x faster than kernels executing on the Convey vector coprocessor. In our concrete scenario, due to trade-offs between reconfiguration overheads and exposed parallelism, the advantage of specialized dataflow kernels is reduced to around 2.5x.

Easy-to-Use On-The-Fly Binary Program Acceleration on Many-Cores - Damschen, Marvin; Plessl, Christian (Proceedings of the 5th International Workshop on Adaptive Self-tuning Computing Systems (ADAPT))
This paper introduces Binary Acceleration At Runtime(BAAR), an easy-to-use on-the-fly binary acceleration mechanismwhich aims to tackle the problem of enabling existentsoftware to automatically utilize accelerators at runtime. BAARis based on the LLVM Compiler Infrastructure and has aclient-server architecture. The client runs the program to beaccelerated in an environment which allows program analysisand profiling. Program parts which are identified as suitable forthe available accelerator are exported and sent to the server.The server optimizes these program parts for the acceleratorand provides RPC execution for the client. The client transformsits program to utilize accelerated execution on the server foroffloaded program parts. We evaluate our work with a proofof-concept implementation of BAAR that uses an Intel XeonPhi 5110P as the acceleration target and performs automaticoffloading, parallelization and vectorization of suitable programparts. The practicality of BAAR for real-world examples is shownbased on a study of stencil codes. Our results show a speedup ofup to 4 without any developer-provided hints and 5.77 withhints over the same code compiled with the Intel Compiler atoptimization level O2 and running on an Intel Xeon E5-2670machine. Based on our insights gained during implementationand evaluation we outline future directions of research, e.g.,offloading more fine-granular program parts than functions, amore sophisticated communication mechanism or introducing onstack-replacement.

Improving Packet Processing Performance in the ATLAS FELIX Project – Analysis and Optimization of a Memory-Bounded Algorithm - Schumacher, Jörn; T. Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann-Miotto, Giovanna; Levinson, L.; et al. (Proc. Int. Conf. on Distributed Event-Based Systems (DEBS))

Aktuelles Schlagwort: Approximate Computing - Plessl, Christian; Platzner, Marco; Schreier, Peter J. (Informatik Spektrum)
Keywords: approximate computing; survey

Transparent offloading of computational hotspots from binary code to Xeon Phi - Damschen, Marvin; Riebler, Heinrich; Vaz, Gavin Francis; Plessl, Christian (Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE))
In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades - Anderson, J; Borga, A; Boterenbrood, H; Chen, H; Chen, K; Drake, G; Francis, D; Gorini, B; Lanni, F; Lehmann Miotto, G; Levinson, L; Narevicius, J; et al. (Journal of Physics: Conference Series)
The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed.

MiLeNa – ein überregionales Programm zur MINT-Lehrernachwuchsförderung - Salinga, Christian; Heinke, Heidrun; Jonas-Ahrend, Gabriela; Theyßen, Heike; Bahr, Ursula; Erb, Roger

Aligning training models with smartphone properties in WiFi fingerprinting based indoor localization - Hoang, Manh Kha; Schmalenstroeer, Joerg; Haeb-Umbach, Reinhold (40th International Conference on Acoustics, Speech and Signal Processing (ICASSP 2015))