A Comparison of Alternative Ways to Identify Singular Matrices - Walther, Andrea; Bause, Fabian; Henning, Bernd

Adaptive Test and Diagnosis of Intermittent Faults - Cook, Alejandro; Rodriguez Gomez, Laura; Hellebrand, Sybille; Indlekofer, Thomas; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Learning to rank lexical substitutions - Szarvas, G.; Busa-Fekete, Robert; Hüllermeier, Eyke (In Proceedings EMNLP-2013 Conference on Empirical Methods in Natural Language Processing, Seattle, USA)

Optimizing the F-measure in multi-label classification: Plug-in rule approach versus structured loss minimization - Dembczynski, K.; Jachnik, A.; Kotlowski, W.; Waegeman, W.; Hüllermeier, Eyke (in Proceedings ICML-2013, 30th International Conference on Machine Learning, Atlanta, USA)

Top-k selection based on adaptive sampling of noisy preferences - Busa-Fekete, Robert; Szoreny, B.; Weng, P.; Cheng, W.; Hüllermeier, Eyke (in Proceedings ICML-2013, 30th International Conference on Machine Learning, Atlanta, USA)

Preference-based CBR: General ideas and basic principles - Hüllermeier, Eyke; Cheng, W. (in Proceedings IJCAI-13, 23rd international Joint Conference on Artificial Intelligence, Beijing, China)

Rule chains for visualizing evolving fuzzy rule-based systems - Henzgen, Sascha; Strickert, M.; Hüllermeier, Eyke (in Proceedings CORES 2013, 8th International Conference on Computer Recognition Systems, Wroclaw, Poland)

Recovery analysis for adaptive learning from non-stationary data streams - Shaker, Ammar; Hüllermeier, Eyke (in Proceedings CORES 2013, 8th International Conference on Computer Recognition Systems, Wroclaw, Poland)

On Semeai Detection in Monte-Carlo Go. - Graf, Tobias; Schäfers, Lars; Platzner, Marco (Proceedings of the International Conference on Computers and Games (CG))

A fully integrated 120-GHz six-port receiver front-end in a 130-nm SiGe BiCMOS technology - Laemmle, Benjamin; Schmalz, Klaus; Borngräber, Johannes; Scheytt, Christoph; Weigel, Robert; Koelpin, Alexander; Kissinger, Dietmar (Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on)
A fully integrated six-port receiver front-end at 120 GHz center frequency including a low-noise-amplifier, a passive six-port network, a VCO, and four direct converters is presented in this publication. The overall architecture of the designed six-port receiver is analyzed and fundamental theory of the receiver given. The design of the six-port building blocks is described and measurement results are presented. All circuits have been fabricated in a 0.13μm 300-GHz f T SiGe BiCMOS technology. The fully integrated receiver consumes 85.9 rnA from a 3.3-V supply and occupies an area of 1.03mm 2 . The receiver includes a VCO with a center frequency of 117.15 GHz, a tuning range of 2.7 GHz, and a phase noise of -86 dBc/Hz at 1 MHz offset. The LNA shows a gain of 12 dB, a 3-dB bandwidth of 30 GHz at a power consumption of 9.2 rnA. The six-port core has a conversion gain of 3.6 dB, a P 1dB of -12 dBm, and a power consumption of 28 rnA. The overall receiver shows a conversion gain of 2.4 dB at 120 GHz and P 1dB of -17 dBm.

Integrator and digitizer for a non-coherent IR-UWB receiver - Digel, Johannes; Masini, Michelangelo; Grözing, Markus; Berroth, Manfred; Fischer, Gunter; Olonbayar, Sonom; Gustat, Hans; Scheytt, Christoph (Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on)
Impulse-radio ultra-wideband systems (IR-UWB) provide short-range wireless communication and precise localization simultaneously. Especially non-coherent IR-UWB reduces the system complexity which enables the design of low-power receivers. This paper presents an integrating digitizer which integrates rectified baseband pulses of an IR-UWB signal and provides the digitized data to the digital baseband of the receiver. The integrator is composed of two time-interleaved (TI) operational amplifiers with capacitive feedback. With this structure, the integrator can be periodically reset without introducing a dead time between two integration periods. The analog-to-digital conversion is performed by a 6 bit 62.4 MS/s successive approximation register analog-to-digital converter (SAR ADC). The integrating digitizer chip is realized in a 250 nm SiGe:C BiCMOS technology from IHP.

A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization - Sun, Yaoming; Marinkovic, Miroslav; Fischer, Gunter; Winkler, Wolfgang; Debski, Wojciech; Beer, Stefan; Zwick, Thomas; Girma, Mekdes Gebresilassie; Hasch, Jürgen; Scheytt, Christoph (Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013 IEEE International)
This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption.

Towards mm-wave System-On-Chip with integrated antennas for low-cost 122 and 245 GHz radar sensors - Scheytt, Christoph; Sun, Yaoming; Schmalz, Klaus; Mao, Yanfei; Wang, Ruoyu; Debski, Wojciech; Winkler, Wolfgang (Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on)
Complex integrated 122 and 245 GHz SiGe BiCMOS transceiver ICs as well as an efficient broadband on-chip antenna are presented. The ICs target radar and sensing applications for the ISM bands at 122 and 245 GHz. Due to high level of integration and basic mm-wave self-testing production as well as test cost are dramatically reduced. Furthermore a compact and efficient on-chip antenna allows for chip-on-board mounting without RF interfaces.

49 GHz 6-bit programmable divider in SiGe BiCMOS - Ergintav, Arzu; Sun, Yaoming; Scheytt, Christoph; Gürbüz, Yasar (Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on)
In this paper, a 6-bit true modular programmable frequency divider with division ratios ranging from 64 to 127 is reported. It is composed of a divider chain of 6 divide-by-2/3 cells, and ECL stages that are introduced as synchronization circuits for programming inputs. The synchronization circuits have CMOS input for compatibility with programming circuits. The stand-alone divider chain is functional up to an input clock frequency of 49 GHz. The combination of the divider chain with synchronization circuits is functional up to 44 GHz. The 6 stage divider draws 34 mA current from a 2.7 V supply. The synchronization circuits draw 30 mA from a 3 V supply. The circuit is fabricated in a 0.13 μm SiGe BiCMOS technology, and is well suited for millimeter-wave phase-locked loop (PLL) circuits which require fine frequency resolution.

245 GHz subharmonic receivers in SiGe - Mao, Yanfei; Schmalz, Klaus; Borngräber, Johannes; Scheytt, Christoph (2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium)
Two subharmonic receivers for 245 GHz spectroscopy sensor applications in the 245 GHz ISM band have been proposed. One receiver consists of an 2nd APDP (antiparallel diode pair) passive SHM (subharmonic mixer), a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA (power amplifier). The other consists of a single-ended four-stage CB (common base) LNA, an 2 nd APDP passive SHM, an IF amplifier, a 120 GHz push-push VCO with 1/64 divider, and a 120 GHz PA. The receivers are fabricated in a SiGe:C BiCMOS technology with f T /f max =300/500 GHz. The measured conversion gain are -17 dB rsp. 10.6 dB at 245 GHz with 3-dB bandwidths of 13 GHz rsp. 14 GHz, and the single-side band noise figure are 17 dB rsp. 20 dB; the two receivers dissipates a power of 213 mW and 312 mW, respectively.

A 240 GHz Direct Conversion IQ Receiver in 0.13 µm SiGe BiCMOS technology - Elkhouly, Mohamed; Mao, Yanfei; Meliani, Chafik; Ellinger, Frank; Scheytt, Christoph (2013 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium,)
A 240 GHz direct conversion IQ receiver manufactured in 0.13 SiGe BiCMOS technology with f T /f max of 300/500 GHz is presented. The receiver consists of a four stage LNA, an active power divider, an LO IQ generation network, and direct down-conversion fundamental mixers. The integrated IQ receiver yields a conversion gain of 18 dB, an 18 dB simulated DSB NF, and a 3 dB bandwidth of 25 GHz. The required 245 GHz LO power is in the order of -10 dBm. The receiver exhibits an IQ amplitude and phase imbalance of 1 dB and 3° respectively. It draws 135 mA from the 3.5 V supply and 20 mA from 2 V.

245 GHz Subharmonic Receiver in SiGe - Mao, Yanfei; Schmalz, Klaus; Borngräber, Johannes; Scheytt, Christoph; Meliani, Chafik (IEEE International Microwave Symposium, Advances in Low Noise Amplifiers and Receivers)
A subharmonic receiver for 245 GHz spectroscopy sensor applications have been proposed. The receiver consists of a CB (common base) LNA, 2 nd transconductance SHM (subharmonic mixer) and a 120 GHz push-push VCO with 1/64 divider. The receiver is fabricated in f T /f max =300/500 GHz SiGe: C BiCMOS technology. Its measured single-ended gain is 14.3 dB at 245 GHz with tuning range of 15 GHz, and the single-side band noise figure is 19 dB. The input 1-dB compression point is at -24 dBm. The receiver dissipates a power of 200 mW.

Wireless 100Gb/s Using A Powerand - Scheytt, Christoph (IEEE International Conference on Communications)

Hardware-Effizientes Mixed-Signal Entzerrfilter - Scheytt, Christoph

Selbstoptimierung in der Anwendung - Böcker, Joachim; Buchholz, Oleg; Romaus, Christoph; Schulte, Christoph; Stille, Karl Stephan Christian (Wissenschaftsforum Intelligente Technische Systeme, 9. Paderborner Workshop Entwurf mechatronischer Systeme)
Die absehbare Entwicklung der Informations- und Kommunikationstechnik wird mechatronische Systeme mit inhärenter Teilintelligenz ermöglichen. Hierfür verwenden wir den Begriff Selbstoptimierung (S.O.). Selbstoptimierende (s.o.) Systeme reagieren autonom und flexibel auf sich ändernde Umfeldbedingungen [ADG+09]. Die Entwicklung derartiger Systeme erfordert eine enge Zusammenarbeit der Entwickler der beteiligten Domänen Mechanik, Elektrik/Elektronik, Regelungstechnik und Softwaretechnik. In diesem Beitrag wird erklärt, wie die Steigerung der Verlässlichkeit durch S.O. bei der Konzipierung eines s.o. Systems adäquat berücksichtigt wird. Die Konzipierung des hybriden Energiespeichersystems des innovativen Schienenfahrzeugs RailCab wird retrospektive durchgeführt. Dies erfolgt von der ersten Funktionsdefinition über die Lösungsauswahl und die dazugehörige Nutzwertanalyse bis hin zur Produktkonzeption des Energiespeichersystems. Es wird gezeigt, wie die Schwachstellen und Widersprüche eines technischen Systems identifiziert sowie mit Hilfe geeigneter Gegenmaßnahmen behoben werden können. Hierbei soll insbesondere die Integration der S.O. als Möglichkeit zur Behebung der Schwachstellen betrachtet werden. Somit wird gezeigt wann und wie die Entscheidung über die s.o. Auslegung des Systems getroffen und die Steigerung der Verlässlichkeit dabei ins Kalkül gezogen wird.
Keywords: Konzipierung; Selbstoptimierung; Verlässlichkeit; Mechatronik; Hybrider Energiespeicher; LEA-Publikation; Eigene