---
_id: '39518'
author:
- first_name: Ulrich
full_name: Hilleringmann, Ulrich
id: '20179'
last_name: Hilleringmann
- first_name: M.
full_name: Schonhoff, M.
last_name: Schonhoff
- first_name: F.
full_name: Assion, F.
last_name: Assion
citation:
ama: 'Hilleringmann U, Schonhoff M, Assion F. Titanium disilicide as hot side metallization
layer for thermoelectric generators. In: 2013 Africon. IEEE; 2014. doi:10.1109/afrcon.2013.6757616'
apa: Hilleringmann, U., Schonhoff, M., & Assion, F. (2014). Titanium disilicide
as hot side metallization layer for thermoelectric generators. 2013 Africon.
https://doi.org/10.1109/afrcon.2013.6757616
bibtex: '@inproceedings{Hilleringmann_Schonhoff_Assion_2014, title={Titanium disilicide
as hot side metallization layer for thermoelectric generators}, DOI={10.1109/afrcon.2013.6757616},
booktitle={2013 Africon}, publisher={IEEE}, author={Hilleringmann, Ulrich and
Schonhoff, M. and Assion, F.}, year={2014} }'
chicago: Hilleringmann, Ulrich, M. Schonhoff, and F. Assion. “Titanium Disilicide
as Hot Side Metallization Layer for Thermoelectric Generators.” In 2013 Africon.
IEEE, 2014. https://doi.org/10.1109/afrcon.2013.6757616.
ieee: 'U. Hilleringmann, M. Schonhoff, and F. Assion, “Titanium disilicide as hot
side metallization layer for thermoelectric generators,” 2014, doi: 10.1109/afrcon.2013.6757616.'
mla: Hilleringmann, Ulrich, et al. “Titanium Disilicide as Hot Side Metallization
Layer for Thermoelectric Generators.” 2013 Africon, IEEE, 2014, doi:10.1109/afrcon.2013.6757616.
short: 'U. Hilleringmann, M. Schonhoff, F. Assion, in: 2013 Africon, IEEE, 2014.'
date_created: 2023-01-24T11:53:18Z
date_updated: 2023-03-22T10:18:06Z
department:
- _id: '59'
doi: 10.1109/afrcon.2013.6757616
language:
- iso: eng
publication: 2013 Africon
publication_status: published
publisher: IEEE
status: public
title: Titanium disilicide as hot side metallization layer for thermoelectric generators
type: conference
user_id: '20179'
year: '2014'
...
---
_id: '42801'
abstract:
- lang: eng
text: We exhibit a practical algorithm for solving the constructive membership problem
for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together
with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R)
is discrete and free, have been implemented in Magma for groups defined over real
algebraic number fields.
author:
- first_name: Markus
full_name: Kirschmer, Markus
id: '82258'
last_name: Kirschmer
- first_name: CHARLES
full_name: LEEDHAM-GREEN, CHARLES
last_name: LEEDHAM-GREEN
citation:
ama: Kirschmer M, LEEDHAM-GREEN C. Computing with subgroups of the modular group
. Glasgow Mathematical Journal. 2014;57(1):173-180. doi:10.1017/s0017089514000202
apa: Kirschmer, M., & LEEDHAM-GREEN, C. (2014). Computing with subgroups of
the modular group . Glasgow Mathematical Journal, 57(1), 173–180.
https://doi.org/10.1017/s0017089514000202
bibtex: '@article{Kirschmer_LEEDHAM-GREEN_2014, title={Computing with subgroups
of the modular group }, volume={57}, DOI={10.1017/s0017089514000202},
number={1}, journal={Glasgow Mathematical Journal}, publisher={Cambridge University
Press (CUP)}, author={Kirschmer, Markus and LEEDHAM-GREEN, CHARLES}, year={2014},
pages={173–180} }'
chicago: 'Kirschmer, Markus, and CHARLES LEEDHAM-GREEN. “Computing with Subgroups
of the Modular Group .” Glasgow Mathematical Journal 57, no. 1 (2014):
173–80. https://doi.org/10.1017/s0017089514000202.'
ieee: 'M. Kirschmer and C. LEEDHAM-GREEN, “Computing with subgroups of the modular
group ,” Glasgow Mathematical Journal, vol. 57, no. 1, pp. 173–180, 2014,
doi: 10.1017/s0017089514000202.'
mla: Kirschmer, Markus, and CHARLES LEEDHAM-GREEN. “Computing with Subgroups of
the Modular Group .” Glasgow Mathematical Journal, vol. 57, no. 1, Cambridge
University Press (CUP), 2014, pp. 173–80, doi:10.1017/s0017089514000202.
short: M. Kirschmer, C. LEEDHAM-GREEN, Glasgow Mathematical Journal 57 (2014) 173–180.
date_created: 2023-03-07T08:47:42Z
date_updated: 2023-04-04T07:55:16Z
department:
- _id: '102'
doi: 10.1017/s0017089514000202
extern: '1'
intvolume: ' 57'
issue: '1'
keyword:
- General Mathematics
language:
- iso: eng
page: 173-180
publication: Glasgow Mathematical Journal
publication_identifier:
issn:
- 0017-0895
- 1469-509X
publication_status: published
publisher: Cambridge University Press (CUP)
status: public
title: 'Computing with subgroups of the modular group '
type: journal_article
user_id: '93826'
volume: 57
year: '2014'
...
---
_id: '42794'
abstract:
- lang: eng
text: We exhibit a practical algorithm for solving the constructive membership problem
for discrete free subgroups of rank 2 in PSL₂(R) or SL₂(R). This algorithm, together
with methods for checking whether a two-generator subgroup of PSL₂(R) or SL₂(R)
is discrete and free, have been implemented in Magma for groups defined over real
algebraic number fields.
author:
- first_name: B.
full_name: Eick, B.
last_name: Eick
- first_name: Markus
full_name: Kirschmer, Markus
id: '82258'
last_name: Kirschmer
- first_name: C.
full_name: Leedham-Green, C.
last_name: Leedham-Green
citation:
ama: Eick B, Kirschmer M, Leedham-Green C. The constructive membership problem for
discrete free subgroups of rank 2 of SL₂(R). LMS Journal of Computation and
Mathematics. 2014;17(1):345-359. doi:10.1112/s1461157014000047
apa: Eick, B., Kirschmer, M., & Leedham-Green, C. (2014). The constructive membership
problem for discrete free subgroups of rank 2 of SL₂(R). LMS Journal of Computation
and Mathematics, 17(1), 345–359. https://doi.org/10.1112/s1461157014000047
bibtex: '@article{Eick_Kirschmer_Leedham-Green_2014, title={The constructive membership
problem for discrete free subgroups of rank 2 of SL₂(R)}, volume={17}, DOI={10.1112/s1461157014000047},
number={1}, journal={LMS Journal of Computation and Mathematics}, publisher={Wiley},
author={Eick, B. and Kirschmer, Markus and Leedham-Green, C.}, year={2014}, pages={345–359}
}'
chicago: 'Eick, B., Markus Kirschmer, and C. Leedham-Green. “The Constructive Membership
Problem for Discrete Free Subgroups of Rank 2 of SL₂(R).” LMS Journal of Computation
and Mathematics 17, no. 1 (2014): 345–59. https://doi.org/10.1112/s1461157014000047.'
ieee: 'B. Eick, M. Kirschmer, and C. Leedham-Green, “The constructive membership
problem for discrete free subgroups of rank 2 of SL₂(R),” LMS Journal of Computation
and Mathematics, vol. 17, no. 1, pp. 345–359, 2014, doi: 10.1112/s1461157014000047.'
mla: Eick, B., et al. “The Constructive Membership Problem for Discrete Free Subgroups
of Rank 2 of SL₂(R).” LMS Journal of Computation and Mathematics, vol.
17, no. 1, Wiley, 2014, pp. 345–59, doi:10.1112/s1461157014000047.
short: B. Eick, M. Kirschmer, C. Leedham-Green, LMS Journal of Computation and Mathematics
17 (2014) 345–359.
date_created: 2023-03-07T08:30:15Z
date_updated: 2023-04-04T09:31:17Z
department:
- _id: '102'
doi: 10.1112/s1461157014000047
extern: '1'
intvolume: ' 17'
issue: '1'
keyword:
- Computational Theory and Mathematics
- General Mathematics
language:
- iso: eng
page: 345-359
publication: LMS Journal of Computation and Mathematics
publication_identifier:
issn:
- 1461-1570
publication_status: published
publisher: Wiley
status: public
title: The constructive membership problem for discrete free subgroups of rank 2 of
SL₂(R)
type: journal_article
user_id: '93826'
volume: 17
year: '2014'
...
---
_id: '3939'
abstract:
- lang: eng
text: "Optical and infrared antennas provide a promising way to couple photons in
and out of nanoscale structures. As\r\ncounterpart to conventional radio antennas,
they are able to increase optical felds in sub-wavelength volumes,\r\nto enhance
excitation and emission of quantum emitters or to direct light, radiated by quantum
emitters. The\r\ndirected emission of these antennas has been mainly pursued by
surface plasmon based devices, e.g. Yagi-Uda\r\nlike antennas, which are rather
complicated due to the coupling of several metallic particles. Also, like all
metallic\r\nstructures in optical or infrared regime, these devices are very sensitive
to fabrication tolerances and are affected\r\nby strong losses. It has been shown
recently, that such directed emission can be accomplished by dielectric\r\nmaterials
as well.\r\nIn this paper we present an optimization of nanoscopic antennas in
the near infrared regime starting from a\r\nmetallic Yagi-Uda structure. The optimization
is done via a particle-swarm algorithm, using full time domain\r\nfinite integration
simulations to obtain the characteristics of the investigated structure, also
taking into account\r\nsubstrates. Furthermore we present a dielectric antenna,
which performs even better, due to the lack of losses\r\nby an appropriate choice
of the dielectric material. These antennas are robust concerning fabrication tolerances\r\nand
can be realized with different materials for both the antenna and the substrate,
without using high index\r\nmaterials."
author:
- first_name: Andre
full_name: Hildebrandt, Andre
last_name: Hildebrandt
- first_name: Matthias
full_name: Reichelt, Matthias
id: '138'
last_name: Reichelt
- first_name: Torsten
full_name: Meier, Torsten
id: '344'
last_name: Meier
orcid: 0000-0001-8864-2072
- first_name: Jens
full_name: Förstner, Jens
id: '158'
last_name: Förstner
orcid: 0000-0001-7059-9862
citation:
ama: 'Hildebrandt A, Reichelt M, Meier T, Förstner J. Engineering plasmonic and
dielectric directional nanoantennas. In: Betz M, Elezzabi AY, Song J-J, Tsen K-T,
eds. Ultrafast Phenomena and Nanophotonics XVIII. Vol 8984. SPIE Proceedings.
SPIE; 2014:89841G-8941G - 6. doi:10.1117/12.2036588'
apa: Hildebrandt, A., Reichelt, M., Meier, T., & Förstner, J. (2014). Engineering
plasmonic and dielectric directional nanoantennas. In M. Betz, A. Y. Elezzabi,
J.-J. Song, & K.-T. Tsen (Eds.), Ultrafast Phenomena and Nanophotonics
XVIII (Vol. 8984, pp. 89841G-8941G – 6). SPIE. https://doi.org/10.1117/12.2036588
bibtex: '@inproceedings{Hildebrandt_Reichelt_Meier_Förstner_2014, series={SPIE Proceedings},
title={Engineering plasmonic and dielectric directional nanoantennas}, volume={8984},
DOI={10.1117/12.2036588}, booktitle={Ultrafast
Phenomena and Nanophotonics XVIII}, publisher={SPIE}, author={Hildebrandt, Andre
and Reichelt, Matthias and Meier, Torsten and Förstner, Jens}, editor={Betz, Markus
and Elezzabi, Abdulhakem Y. and Song, Jin-Joo and Tsen, Kong-Thon}, year={2014},
pages={89841G-8941G–6}, collection={SPIE Proceedings} }'
chicago: Hildebrandt, Andre, Matthias Reichelt, Torsten Meier, and Jens Förstner.
“Engineering Plasmonic and Dielectric Directional Nanoantennas.” In Ultrafast
Phenomena and Nanophotonics XVIII, edited by Markus Betz, Abdulhakem Y. Elezzabi,
Jin-Joo Song, and Kong-Thon Tsen, 8984:89841G-8941G – 6. SPIE Proceedings. SPIE,
2014. https://doi.org/10.1117/12.2036588.
ieee: 'A. Hildebrandt, M. Reichelt, T. Meier, and J. Förstner, “Engineering plasmonic
and dielectric directional nanoantennas,” in Ultrafast Phenomena and Nanophotonics
XVIII, 2014, vol. 8984, pp. 89841G-8941G–6, doi: 10.1117/12.2036588.'
mla: Hildebrandt, Andre, et al. “Engineering Plasmonic and Dielectric Directional
Nanoantennas.” Ultrafast Phenomena and Nanophotonics XVIII, edited by Markus
Betz et al., vol. 8984, SPIE, 2014, pp. 89841G-8941G – 6, doi:10.1117/12.2036588.
short: 'A. Hildebrandt, M. Reichelt, T. Meier, J. Förstner, in: M. Betz, A.Y. Elezzabi,
J.-J. Song, K.-T. Tsen (Eds.), Ultrafast Phenomena and Nanophotonics XVIII, SPIE,
2014, pp. 89841G-8941G–6.'
date_created: 2018-08-20T10:04:52Z
date_updated: 2023-04-16T22:09:25Z
ddc:
- '530'
department:
- _id: '61'
- _id: '15'
- _id: '293'
- _id: '230'
- _id: '170'
doi: 10.1117/12.2036588
editor:
- first_name: Markus
full_name: Betz, Markus
last_name: Betz
- first_name: Abdulhakem Y.
full_name: Elezzabi, Abdulhakem Y.
last_name: Elezzabi
- first_name: Jin-Joo
full_name: Song, Jin-Joo
last_name: Song
- first_name: Kong-Thon
full_name: Tsen, Kong-Thon
last_name: Tsen
file:
- access_level: closed
content_type: application/pdf
creator: hclaudia
date_created: 2018-08-20T10:10:25Z
date_updated: 2018-08-20T10:10:25Z
file_id: '3940'
file_name: 2014 Hildebrandt,Reichelt,Meier,Förstner_Engineering plasmonic and dielectric
directional nanoantennas_SPIE OPTO.pdf
file_size: 1744539
relation: main_file
success: 1
file_date_updated: 2018-08-20T10:10:25Z
has_accepted_license: '1'
intvolume: ' 8984'
keyword:
- tet_topic_opticalantenna
language:
- iso: eng
page: 89841G-8941G-6
publication: Ultrafast Phenomena and Nanophotonics XVIII
publication_status: published
publisher: SPIE
series_title: SPIE Proceedings
status: public
title: Engineering plasmonic and dielectric directional nanoantennas
type: conference
user_id: '49063'
volume: 8984
year: '2014'
...
---
_id: '44341'
author:
- first_name: Igor
full_name: Burban, Igor
id: '72064'
last_name: Burban
- first_name: B.
full_name: Kreußler, B.
last_name: Kreußler
citation:
ama: Burban I, Kreußler B. Analytic moduli spaces of simple sheaves on families
of integral curves. Mathematische Nachrichten. 2014;287(2–3):173–183.
apa: Burban, I., & Kreußler, B. (2014). Analytic moduli spaces of simple sheaves
on families of integral curves. Mathematische Nachrichten, 287(2–3),
173–183.
bibtex: '@article{Burban_Kreußler_2014, title={Analytic moduli spaces of simple
sheaves on families of integral curves}, volume={287}, number={2–3}, journal={Mathematische
Nachrichten}, author={Burban, Igor and Kreußler, B.}, year={2014}, pages={173–183}
}'
chicago: 'Burban, Igor, and B. Kreußler. “Analytic Moduli Spaces of Simple Sheaves
on Families of Integral Curves.” Mathematische Nachrichten 287, no. 2–3
(2014): 173–183.'
ieee: I. Burban and B. Kreußler, “Analytic moduli spaces of simple sheaves on families
of integral curves,” Mathematische Nachrichten, vol. 287, no. 2–3, pp.
173–183, 2014.
mla: Burban, Igor, and B. Kreußler. “Analytic Moduli Spaces of Simple Sheaves on
Families of Integral Curves.” Mathematische Nachrichten, vol. 287, no.
2–3, 2014, pp. 173–183.
short: I. Burban, B. Kreußler, Mathematische Nachrichten 287 (2014) 173–183.
date_created: 2023-05-03T00:24:25Z
date_updated: 2023-05-07T01:42:01Z
department:
- _id: '602'
extern: '1'
intvolume: ' 287'
issue: 2–3
language:
- iso: eng
page: 173–183
publication: Mathematische Nachrichten
publication_status: published
status: public
title: Analytic moduli spaces of simple sheaves on families of integral curves
type: journal_article
user_id: '49063'
volume: 287
year: '2014'
...
---
_id: '45686'
author:
- first_name: Julia
full_name: Bruns, Julia
id: '72183'
last_name: Bruns
orcid: https://orcid.org/0000-0002-6604-5864
- first_name: C.
full_name: Walter-Laager, C.
last_name: Walter-Laager
- first_name: M.
full_name: Pfiffner, M.
last_name: Pfiffner
- first_name: J.
full_name: Schwarz, J.
last_name: Schwarz
citation:
ama: 'Bruns J, Walter-Laager C, Pfiffner M, Schwarz J. Beobachten und Dokumentieren.
Basis zur chancengerechten Gestaltung des pädagogischen Alltags. In: Walter-Laager
C, Pfiffner M, Fasseing-Heim K, eds. Vorsprung für alle! Erhöhung der Chancengerechtigkeit
durch Projekte der Frühpädagogik. hep Verlag; 2014:132–168.'
apa: Bruns, J., Walter-Laager, C., Pfiffner, M., & Schwarz, J. (2014). Beobachten
und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags.
In C. Walter-Laager, M. Pfiffner, & K. Fasseing-Heim (Eds.), Vorsprung
für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik
(pp. 132–168). hep Verlag.
bibtex: '@inproceedings{Bruns_Walter-Laager_Pfiffner_Schwarz_2014, place={Bern},
title={Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des
pädagogischen Alltags}, booktitle={Vorsprung für alle! Erhöhung der Chancengerechtigkeit
durch Projekte der Frühpädagogik}, publisher={hep Verlag}, author={Bruns, Julia
and Walter-Laager, C. and Pfiffner, M. and Schwarz, J.}, editor={Walter-Laager,
C. and Pfiffner, M. and Fasseing-Heim, K.}, year={2014}, pages={132–168} }'
chicago: 'Bruns, Julia, C. Walter-Laager, M. Pfiffner, and J. Schwarz. “Beobachten
und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen Alltags.”
In Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte der
Frühpädagogik, edited by C. Walter-Laager, M. Pfiffner, and K. Fasseing-Heim,
132–168. Bern: hep Verlag, 2014.'
ieee: J. Bruns, C. Walter-Laager, M. Pfiffner, and J. Schwarz, “Beobachten und Dokumentieren.
Basis zur chancengerechten Gestaltung des pädagogischen Alltags,” in Vorsprung
für alle! Erhöhung der Chancengerechtigkeit durch Projekte der Frühpädagogik,
2014, pp. 132–168.
mla: Bruns, Julia, et al. “Beobachten und Dokumentieren. Basis zur chancengerechten
Gestaltung des pädagogischen Alltags.” Vorsprung für alle! Erhöhung der Chancengerechtigkeit
durch Projekte der Frühpädagogik, edited by C. Walter-Laager et al., hep Verlag,
2014, pp. 132–168.
short: 'J. Bruns, C. Walter-Laager, M. Pfiffner, J. Schwarz, in: C. Walter-Laager,
M. Pfiffner, K. Fasseing-Heim (Eds.), Vorsprung für alle! Erhöhung der Chancengerechtigkeit
durch Projekte der Frühpädagogik, hep Verlag, Bern, 2014, pp. 132–168.'
date_created: 2023-06-20T18:45:01Z
date_updated: 2023-06-20T18:45:06Z
department:
- _id: '97'
- _id: '611'
editor:
- first_name: C.
full_name: Walter-Laager, C.
last_name: Walter-Laager
- first_name: M.
full_name: Pfiffner, M.
last_name: Pfiffner
- first_name: K.
full_name: Fasseing-Heim, K.
last_name: Fasseing-Heim
extern: '1'
language:
- iso: ger
page: 132–168
place: Bern
publication: Vorsprung für alle! Erhöhung der Chancengerechtigkeit durch Projekte
der Frühpädagogik
publication_status: published
publisher: hep Verlag
status: public
title: Beobachten und Dokumentieren. Basis zur chancengerechten Gestaltung des pädagogischen
Alltags
type: conference
user_id: '49063'
year: '2014'
...
---
_id: '36474'
author:
- first_name: Julia
full_name: Bruns, Julia
id: '72183'
last_name: Bruns
orcid: https://orcid.org/0000-0002-6604-5864
citation:
ama: Bruns J. Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische
Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik.
Vol 21. Waxmann; 2014.
apa: Bruns, J. (2014). Adaptive Förderung in der elementarpädagogischen Praxis.
Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern
im Bereich Mathematik (Vol. 21). Waxmann.
bibtex: '@book{Bruns_2014, place={Münster}, series={Empirische Studien zur Didaktik
der Mathematik}, title={Adaptive Förderung in der elementarpädagogischen Praxis.
Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern
im Bereich Mathematik}, volume={21}, publisher={Waxmann}, author={Bruns, Julia},
year={2014}, collection={Empirische Studien zur Didaktik der Mathematik} }'
chicago: 'Bruns, Julia. Adaptive Förderung in der elementarpädagogischen Praxis.
Eine empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern
im Bereich Mathematik. Vol. 21. Empirische Studien zur Didaktik der Mathematik.
Münster: Waxmann, 2014.'
ieee: 'J. Bruns, Adaptive Förderung in der elementarpädagogischen Praxis. Eine
empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im
Bereich Mathematik, vol. 21. Münster: Waxmann, 2014.'
mla: Bruns, Julia. Adaptive Förderung in der elementarpädagogischen Praxis. Eine
empirische Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im
Bereich Mathematik. Waxmann, 2014.
short: J. Bruns, Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische
Studie zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik,
Waxmann, Münster, 2014.
date_created: 2023-01-12T15:10:14Z
date_updated: 2023-06-20T19:18:57Z
department:
- _id: '611'
- _id: '97'
extern: '1'
intvolume: ' 21'
language:
- iso: ger
place: Münster
publication_status: published
publisher: Waxmann
series_title: Empirische Studien zur Didaktik der Mathematik
status: public
title: Adaptive Förderung in der elementarpädagogischen Praxis. Eine empirische Studie
zum di-daktischen Handeln von Erzieherinnen und Erziehern im Bereich Mathematik
type: book
user_id: '49063'
volume: 21
year: '2014'
...
---
_id: '36533'
author:
- first_name: Julia
full_name: Bruns, Julia
id: '72183'
last_name: Bruns
orcid: https://orcid.org/0000-0002-6604-5864
- first_name: Lars
full_name: Eichen, Lars
last_name: Eichen
citation:
ama: 'Bruns J, Eichen L. Adaptive mathematische Förderung im Elementarbereich -
Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen. In: Roth J,
Ames J, eds. Beiträge Zum Mathematikunterricht 2014. WTM-Verlag; 2014:277-280.
doi:10.17877/DE290R-5105'
apa: Bruns, J., & Eichen, L. (2014). Adaptive mathematische Förderung im Elementarbereich
- Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen. In J. Roth
& J. Ames (Eds.), Beiträge zum Mathematikunterricht 2014 (pp. 277–280).
WTM-Verlag. https://doi.org/10.17877/DE290R-5105
bibtex: '@inproceedings{Bruns_Eichen_2014, place={Münster}, title={Adaptive mathematische
Förderung im Elementarbereich - Empirische Ergebnisse zum didaktischen Handeln
von Erzieherinnen}, DOI={10.17877/DE290R-5105},
booktitle={Beiträge zum Mathematikunterricht 2014}, publisher={WTM-Verlag}, author={Bruns,
Julia and Eichen, Lars}, editor={Roth, Jürgen and Ames, Judith}, year={2014},
pages={277–280} }'
chicago: 'Bruns, Julia, and Lars Eichen. “Adaptive Mathematische Förderung Im Elementarbereich
- Empirische Ergebnisse Zum Didaktischen Handeln von Erzieherinnen.” In Beiträge
Zum Mathematikunterricht 2014, edited by Jürgen Roth and Judith Ames, 277–80.
Münster: WTM-Verlag, 2014. https://doi.org/10.17877/DE290R-5105.'
ieee: 'J. Bruns and L. Eichen, “Adaptive mathematische Förderung im Elementarbereich
- Empirische Ergebnisse zum didaktischen Handeln von Erzieherinnen,” in Beiträge
zum Mathematikunterricht 2014, Koblenz, 2014, pp. 277–280, doi: 10.17877/DE290R-5105.'
mla: Bruns, Julia, and Lars Eichen. “Adaptive Mathematische Förderung Im Elementarbereich
- Empirische Ergebnisse Zum Didaktischen Handeln von Erzieherinnen.” Beiträge
Zum Mathematikunterricht 2014, edited by Jürgen Roth and Judith Ames, WTM-Verlag,
2014, pp. 277–80, doi:10.17877/DE290R-5105.
short: 'J. Bruns, L. Eichen, in: J. Roth, J. Ames (Eds.), Beiträge Zum Mathematikunterricht
2014, WTM-Verlag, Münster, 2014, pp. 277–280.'
conference:
end_date: 14.03.2014
location: Koblenz
name: 48. Jahrestagung der Gesellschaft für Didaktik der Mathematik
start_date: 10.03.2014
date_created: 2023-01-13T09:00:17Z
date_updated: 2023-06-28T08:27:21Z
ddc:
- '510'
department:
- _id: '97'
- _id: '611'
doi: 10.17877/DE290R-5105
editor:
- first_name: Jürgen
full_name: Roth, Jürgen
last_name: Roth
- first_name: Judith
full_name: Ames, Judith
last_name: Ames
file:
- access_level: open_access
content_type: application/pdf
creator: brunsj
date_created: 2023-01-13T09:00:12Z
date_updated: 2023-01-13T09:00:12Z
file_id: '36534'
file_name: BzMU14-4ES-Bruns-90.pdf
file_size: 1216795
relation: main_file
file_date_updated: 2023-01-13T09:00:12Z
has_accepted_license: '1'
language:
- iso: eng
oa: '1'
page: 277-280
place: Münster
publication: Beiträge zum Mathematikunterricht 2014
publisher: WTM-Verlag
status: public
title: Adaptive mathematische Förderung im Elementarbereich - Empirische Ergebnisse
zum didaktischen Handeln von Erzieherinnen
type: conference
user_id: '14931'
year: '2014'
...
---
_id: '46266'
author:
- first_name: Bijan
full_name: Alizadeh, Bijan
last_name: Alizadeh
- first_name: Payman
full_name: Behnam, Payman
last_name: Behnam
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
citation:
ama: Alizadeh B, Behnam P, Sadeghi-Kohan S. A Scalable Formal Debugging Approach
with Auto-Correction Capability based on Static Slicing and Dynamic Ranking for
RTL Datapath Designs. IEEE Transactions on Computers. Published online
2014:1-1. doi:10.1109/tc.2014.2329687
apa: Alizadeh, B., Behnam, P., & Sadeghi-Kohan, S. (2014). A Scalable Formal
Debugging Approach with Auto-Correction Capability based on Static Slicing and
Dynamic Ranking for RTL Datapath Designs. IEEE Transactions on Computers,
1–1. https://doi.org/10.1109/tc.2014.2329687
bibtex: '@article{Alizadeh_Behnam_Sadeghi-Kohan_2014, title={A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs}, DOI={10.1109/tc.2014.2329687},
journal={IEEE Transactions on Computers}, publisher={Institute of Electrical and
Electronics Engineers (IEEE)}, author={Alizadeh, Bijan and Behnam, Payman and
Sadeghi-Kohan, Somayeh}, year={2014}, pages={1–1} }'
chicago: Alizadeh, Bijan, Payman Behnam, and Somayeh Sadeghi-Kohan. “A Scalable
Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing
and Dynamic Ranking for RTL Datapath Designs.” IEEE Transactions on Computers,
2014, 1–1. https://doi.org/10.1109/tc.2014.2329687.
ieee: 'B. Alizadeh, P. Behnam, and S. Sadeghi-Kohan, “A Scalable Formal Debugging
Approach with Auto-Correction Capability based on Static Slicing and Dynamic Ranking
for RTL Datapath Designs,” IEEE Transactions on Computers, pp. 1–1, 2014,
doi: 10.1109/tc.2014.2329687.'
mla: Alizadeh, Bijan, et al. “A Scalable Formal Debugging Approach with Auto-Correction
Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.”
IEEE Transactions on Computers, Institute of Electrical and Electronics
Engineers (IEEE), 2014, pp. 1–1, doi:10.1109/tc.2014.2329687.
short: B. Alizadeh, P. Behnam, S. Sadeghi-Kohan, IEEE Transactions on Computers
(2014) 1–1.
date_created: 2023-08-02T11:15:22Z
date_updated: 2023-08-02T11:32:37Z
department:
- _id: '48'
doi: 10.1109/tc.2014.2329687
extern: '1'
keyword:
- Computational Theory and Mathematics
- Hardware and Architecture
- Theoretical Computer Science
- Software
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computers
publication_identifier:
issn:
- 0018-9340
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
status: public
title: A Scalable Formal Debugging Approach with Auto-Correction Capability based
on Static Slicing and Dynamic Ranking for RTL Datapath Designs
type: journal_article
user_id: '78614'
year: '2014'
...
---
_id: '46268'
author:
- first_name: Marzieh
full_name: Mohammadi, Marzieh
last_name: Mohammadi
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Nasser
full_name: Masoumi, Nasser
last_name: Masoumi
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Mohammadi M, Sadeghi-Kohan S, Masoumi N, Navabi Z. An off-line MDSI interconnect
BIST incorporated in BS 1149.1. In: 2014 19th IEEE European Test Symposium
(ETS). IEEE; 2014. doi:10.1109/ets.2014.6847847'
apa: Mohammadi, M., Sadeghi-Kohan, S., Masoumi, N., & Navabi, Z. (2014). An
off-line MDSI interconnect BIST incorporated in BS 1149.1. 2014 19th IEEE European
Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847847
bibtex: '@inproceedings{Mohammadi_Sadeghi-Kohan_Masoumi_Navabi_2014, title={An off-line
MDSI interconnect BIST incorporated in BS 1149.1}, DOI={10.1109/ets.2014.6847847},
booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Mohammadi,
Marzieh and Sadeghi-Kohan, Somayeh and Masoumi, Nasser and Navabi, Zainalabedin},
year={2014} }'
chicago: Mohammadi, Marzieh, Somayeh Sadeghi-Kohan, Nasser Masoumi, and Zainalabedin
Navabi. “An Off-Line MDSI Interconnect BIST Incorporated in BS 1149.1.” In 2014
19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847847.
ieee: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, and Z. Navabi, “An off-line MDSI
interconnect BIST incorporated in BS 1149.1,” 2014, doi: 10.1109/ets.2014.6847847.'
mla: Mohammadi, Marzieh, et al. “An Off-Line MDSI Interconnect BIST Incorporated
in BS 1149.1.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014,
doi:10.1109/ets.2014.6847847.
short: 'M. Mohammadi, S. Sadeghi-Kohan, N. Masoumi, Z. Navabi, in: 2014 19th IEEE
European Test Symposium (ETS), IEEE, 2014.'
date_created: 2023-08-02T11:18:26Z
date_updated: 2023-08-02T11:32:48Z
department:
- _id: '48'
doi: 10.1109/ets.2014.6847847
extern: '1'
language:
- iso: eng
publication: 2014 19th IEEE European Test Symposium (ETS)
publication_status: published
publisher: IEEE
status: public
title: An off-line MDSI interconnect BIST incorporated in BS 1149.1
type: conference
user_id: '78614'
year: '2014'
...
---
_id: '46267'
author:
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
orcid: https://orcid.org/0000-0001-7246-0610
- first_name: Payman
full_name: Behnam, Payman
last_name: Behnam
- first_name: Bijan
full_name: Alizadeh, Bijan
last_name: Alizadeh
- first_name: Masahiro
full_name: Fujita, Masahiro
last_name: Fujita
- first_name: Zainalabedin
full_name: Navabi, Zainalabedin
last_name: Navabi
citation:
ama: 'Sadeghi-Kohan S, Behnam P, Alizadeh B, Fujita M, Navabi Z. Improving polynomial
datapath debugging with HEDs. In: 2014 19th IEEE European Test Symposium (ETS).
IEEE; 2014. doi:10.1109/ets.2014.6847797'
apa: Sadeghi-Kohan, S., Behnam, P., Alizadeh, B., Fujita, M., & Navabi, Z. (2014).
Improving polynomial datapath debugging with HEDs. 2014 19th IEEE European
Test Symposium (ETS). https://doi.org/10.1109/ets.2014.6847797
bibtex: '@inproceedings{Sadeghi-Kohan_Behnam_Alizadeh_Fujita_Navabi_2014, title={Improving
polynomial datapath debugging with HEDs}, DOI={10.1109/ets.2014.6847797},
booktitle={2014 19th IEEE European Test Symposium (ETS)}, publisher={IEEE}, author={Sadeghi-Kohan,
Somayeh and Behnam, Payman and Alizadeh, Bijan and Fujita, Masahiro and Navabi,
Zainalabedin}, year={2014} }'
chicago: Sadeghi-Kohan, Somayeh, Payman Behnam, Bijan Alizadeh, Masahiro Fujita,
and Zainalabedin Navabi. “Improving Polynomial Datapath Debugging with HEDs.”
In 2014 19th IEEE European Test Symposium (ETS). IEEE, 2014. https://doi.org/10.1109/ets.2014.6847797.
ieee: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, and Z. Navabi, “Improving
polynomial datapath debugging with HEDs,” 2014, doi: 10.1109/ets.2014.6847797.'
mla: Sadeghi-Kohan, Somayeh, et al. “Improving Polynomial Datapath Debugging with
HEDs.” 2014 19th IEEE European Test Symposium (ETS), IEEE, 2014, doi:10.1109/ets.2014.6847797.
short: 'S. Sadeghi-Kohan, P. Behnam, B. Alizadeh, M. Fujita, Z. Navabi, in: 2014
19th IEEE European Test Symposium (ETS), IEEE, 2014.'
date_created: 2023-08-02T11:17:08Z
date_updated: 2023-08-02T11:34:10Z
department:
- _id: '48'
doi: 10.1109/ets.2014.6847797
extern: '1'
language:
- iso: eng
publication: 2014 19th IEEE European Test Symposium (ETS)
publication_status: published
publisher: IEEE
status: public
title: Improving polynomial datapath debugging with HEDs
type: conference
user_id: '78614'
year: '2014'
...
---
_id: '335'
abstract:
- lang: eng
text: Im Bereich der Computersysteme ist die Festlegung der Grenze zwischen Hardware
und Software eine zentrale Problemstellung. Diese Grenze hat in den letzten Jahrzehnten
nicht nur die Entwicklung von Computersystemen bestimmt, sondern auch die Strukturierung
der Ausbildung in den Computerwissenschaften beeinflusst und sogar zur Entstehung
von neuen Forschungsrichtungen gef{\"u}hrt. In diesem Beitrag besch{\"a}ftigen
wir uns mit Verschiebungen an der Grenze zwischen Hardware und Software und diskutieren
insgesamt drei qualitativ unterschiedliche Formen solcher Verschiebungen. Wir
beginnen mit der Entwicklung von Computersystemen im letzten Jahrhundert und der
Entstehung dieser Grenze, die Hardware und Software erst als eigenst{\"a}ndige
Produkte differenziert. Dann widmen wir uns der Frage, welche Funktionen in einem
Computersystem besser in Hardware und welche besser in Software realisiert werden
sollten, eine Fragestellung die zu Beginn der 90er-Jahre zur Bildung einer eigenen
Forschungsrichtung, dem sogenannten Hardware/Software Co-design, gef{\"u}hrt hat.
Im Hardware/Software Co-design findet eine Verschiebung von Funktionen an der Grenze
zwischen Hardware und Software w{\"a}hrend der Entwicklung eines Produktes statt,
um Produkteigenschaften zu optimieren. Im fertig entwickelten und eingesetzten
Produkt hingegen k{\"o}nnen wir dann eine feste Grenze zwischen Hardware und Software
beobachten. Im dritten Teil dieses Beitrags stellen wir mit selbst-adaptiven Systemen
eine hochaktuelle Forschungsrichtung vor. In unserem Kontext bedeutet Selbstadaption,
dass ein System Verschiebungen von Funktionen an der Grenze zwischen Hardware
und Software autonom w{\"a}hrend der Betriebszeit vornimmt. Solche Systeme beruhen
auf rekonfigurierbarer Hardware, einer relativ neuen Technologie mit der die Hardware
eines Computers w{\"a}hrend der Laufzeit ver{\"a}ndert werden kann. Diese Technologie
f{\"u}hrt zu einer durchl{\"a}ssigen Grenze zwischen Hardware und Software bzw.
l{\"o}st sie die herk{\"o}mmliche Vorstellung einer festen Hardware und einer
flexiblen Software damit auf.
author:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Platzner M, Plessl C. Verschiebungen an der Grenze zwischen Hardware und Software.
In: Künsemöller J, Eke NO, Foit L, Kaerlein T, eds. Logiken strukturbildender
Prozesse: Automatismen. Schriftenreihe des Graduiertenkollegs “Automatismen.”
Wilhelm Fink; 2014:123-144.'
apa: 'Platzner, M., & Plessl, C. (2014). Verschiebungen an der Grenze zwischen
Hardware und Software. In J. Künsemöller, N. O. Eke, L. Foit, & T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen (pp. 123–144).
Wilhelm Fink.'
bibtex: '@inbook{Platzner_Plessl_2014, place={Paderborn}, series={Schriftenreihe
des Graduiertenkollegs “Automatismen”}, title={Verschiebungen an der Grenze zwischen
Hardware und Software}, booktitle={Logiken strukturbildender Prozesse: Automatismen},
publisher={Wilhelm Fink}, author={Platzner, Marco and Plessl, Christian}, editor={Künsemöller,
Jörn and Eke, Norber Otto and Foit, Lioba and Kaerlein, Timo}, year={2014}, pages={123–144},
collection={Schriftenreihe des Graduiertenkollegs “Automatismen”} }'
chicago: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” In Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller, Norber Otto Eke, Lioba Foit, and Timo Kaerlein, 123–44.
Schriftenreihe des Graduiertenkollegs “Automatismen.” Paderborn: Wilhelm Fink,
2014.'
ieee: 'M. Platzner and C. Plessl, “Verschiebungen an der Grenze zwischen Hardware
und Software,” in Logiken strukturbildender Prozesse: Automatismen, J.
Künsemöller, N. O. Eke, L. Foit, and T. Kaerlein, Eds. Paderborn: Wilhelm Fink,
2014, pp. 123–144.'
mla: 'Platzner, Marco, and Christian Plessl. “Verschiebungen an der Grenze zwischen
Hardware und Software.” Logiken strukturbildender Prozesse: Automatismen,
edited by Jörn Künsemöller et al., Wilhelm Fink, 2014, pp. 123–44.'
short: 'M. Platzner, C. Plessl, in: J. Künsemöller, N.O. Eke, L. Foit, T. Kaerlein
(Eds.), Logiken strukturbildender Prozesse: Automatismen, Wilhelm Fink, Paderborn,
2014, pp. 123–144.'
date_created: 2017-10-17T12:41:57Z
date_updated: 2023-09-26T13:32:49Z
ddc:
- '040'
department:
- _id: '518'
- _id: '27'
- _id: '78'
editor:
- first_name: Jörn
full_name: Künsemöller, Jörn
last_name: Künsemöller
- first_name: Norber Otto
full_name: Eke, Norber Otto
last_name: Eke
- first_name: Lioba
full_name: Foit, Lioba
last_name: Foit
- first_name: Timo
full_name: Kaerlein, Timo
last_name: Kaerlein
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:29:58Z
date_updated: 2018-03-20T07:29:58Z
file_id: '1424'
file_name: 335-2014_plessl_automatismen.pdf
file_size: 2848154
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:29:58Z
has_accepted_license: '1'
language:
- iso: ger
page: 123-144
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
publication: 'Logiken strukturbildender Prozesse: Automatismen'
publication_identifier:
isbn:
- 978-3-7705-5730-1
publication_status: published
publisher: Wilhelm Fink
quality_controlled: '1'
series_title: Schriftenreihe des Graduiertenkollegs "Automatismen"
status: public
title: Verschiebungen an der Grenze zwischen Hardware und Software
type: book_chapter
user_id: '15278'
year: '2014'
...
---
_id: '388'
abstract:
- lang: eng
text: In order to leverage the use of reconfigurable architectures in general-purpose
computing, quick and automated methods to find suitable accelerator designs are
required. We tackle this challenge in both regards. In order to avoid long synthesis
times, we target a vector copro- cessor, implemented on the FPGAs of a Convey
HC-1. Previous studies showed that existing tools were not able to accelerate
a real-world application with low effort. We present a toolflow to automatically
identify suitable loops for vectorization, generate a corresponding hardware/software
bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop
vectorization. We evaluate our tools with a set of characteristic loops, systematically
analyzing different dependency and data layout properties.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer. In: Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC). Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International
Publishing; 2014:144-155. doi:10.1007/978-3-319-05960-0_13'
apa: 'Kenter, T., Vaz, G. F., & Plessl, C. (2014). Partitioning and Vectorizing
Binary Applications for a Reconfigurable Vector Computer. Proceedings of the
International Symposium on Reconfigurable Computing: Architectures, Tools, and
Applications (ARC), 8405, 144–155. https://doi.org/10.1007/978-3-319-05960-0_13'
bibtex: '@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes
in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications
for a Reconfigurable Vector Computer}, volume={8405}, DOI={10.1007/978-3-319-05960-0_13},
booktitle={Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)}, publisher={Springer International
Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian},
year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)}
}'
chicago: 'Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning
and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In
Proceedings of the International Symposium on Reconfigurable Computing: Architectures,
Tools, and Applications (ARC), 8405:144–55. Lecture Notes in Computer Science
(LNCS). Cham: Springer International Publishing, 2014. https://doi.org/10.1007/978-3-319-05960-0_13.'
ieee: 'T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary
Applications for a Reconfigurable Vector Computer,” in Proceedings of the International
Symposium on Reconfigurable Computing: Architectures, Tools, and Applications
(ARC), 2014, vol. 8405, pp. 144–155, doi: 10.1007/978-3-319-05960-0_13.'
mla: 'Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for
a Reconfigurable Vector Computer.” Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC),
vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:10.1007/978-3-319-05960-0_13.'
short: 'T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium
on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer
International Publishing, Cham, 2014, pp. 144–155.'
date_created: 2017-10-17T12:42:07Z
date_updated: 2023-09-26T13:34:08Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1007/978-3-319-05960-0_13
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:02:02Z
date_updated: 2018-03-20T07:02:02Z
file_id: '1387'
file_name: 388-plessl14_arc.pdf
file_size: 330193
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:02:02Z
has_accepted_license: '1'
intvolume: ' 8405'
language:
- iso: eng
page: 144-155
place: Cham
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: 'Proceedings of the International Symposium on Reconfigurable Computing:
Architectures, Tools, and Applications (ARC)'
publisher: Springer International Publishing
quality_controlled: '1'
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector
Computer
type: conference
user_id: '15278'
volume: 8405
year: '2014'
...
---
_id: '363'
abstract:
- lang: eng
text: Due to the continuously shrinking device structures and increasing densities
of FPGAs, thermal aspects have become the new focus for many research projects
over the last years. Most researchers rely on temperature simulations to evaluate
their novel thermal management techniques. However, these temperature simulations
require a high computational effort if a detailed thermal model is used and their
accuracies are often unclear. In contrast to simulations, the use of synthetic
heat sources allows for experimental evaluation of temperature management methods.
In this paper we investigate the creation of significant rises in temperature
on modern FPGAs to enable future evaluation of thermal management techniques based
on experiments. To that end, we have developed seven different heat-generating
cores that use different subsets of FPGA resources. Our experimental results show
that, according to external temperature probes connected to the FPGA’s heat sink,
we can increase the temperature by an average of 81 !C. This corresponds to an
average increase of 156.3 !C as measured by the built-in thermal diodes of our
Virtex-5 FPGAs in less than 30 min by only utilizing about 21 percent of the slices.
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Hendrik
full_name: Hangmann, Hendrik
last_name: Hangmann
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Hangmann H, Happe M, Platzner M, Plessl C. Seven Recipes for Setting
Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors and Microsystems.
2014;38(8, Part B):911-919. doi:10.1016/j.micpro.2013.12.001
apa: Agne, A., Hangmann, H., Happe, M., Platzner, M., & Plessl, C. (2014). Seven
Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators. Microprocessors
and Microsystems, 38(8, Part B), 911–919. https://doi.org/10.1016/j.micpro.2013.12.001
bibtex: '@article{Agne_Hangmann_Happe_Platzner_Plessl_2014, title={Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators}, volume={38}, DOI={10.1016/j.micpro.2013.12.001},
number={8, Part B}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Agne, Andreas and Hangmann, Hendrik and Happe, Markus and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={911–919} }'
chicago: 'Agne, Andreas, Hendrik Hangmann, Markus Happe, Marco Platzner, and Christian
Plessl. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators.”
Microprocessors and Microsystems 38, no. 8, Part B (2014): 911–19. https://doi.org/10.1016/j.micpro.2013.12.001.'
ieee: 'A. Agne, H. Hangmann, M. Happe, M. Platzner, and C. Plessl, “Seven Recipes
for Setting Your FPGA on Fire – A Cookbook on Heat Generators,” Microprocessors
and Microsystems, vol. 38, no. 8, Part B, pp. 911–919, 2014, doi: 10.1016/j.micpro.2013.12.001.'
mla: Agne, Andreas, et al. “Seven Recipes for Setting Your FPGA on Fire – A Cookbook
on Heat Generators.” Microprocessors and Microsystems, vol. 38, no. 8,
Part B, Elsevier, 2014, pp. 911–19, doi:10.1016/j.micpro.2013.12.001.
short: A. Agne, H. Hangmann, M. Happe, M. Platzner, C. Plessl, Microprocessors and
Microsystems 38 (2014) 911–919.
date_created: 2017-10-17T12:42:02Z
date_updated: 2023-09-26T13:33:06Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2013.12.001
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:20:31Z
date_updated: 2018-03-20T07:20:31Z
file_id: '1408'
file_name: 363-plessl13_micpro.pdf
file_size: 1499996
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:20:31Z
has_accepted_license: '1'
intvolume: ' 38'
issue: 8, Part B
language:
- iso: eng
page: 911-919
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Microprocessors and Microsystems
publisher: Elsevier
quality_controlled: '1'
status: public
title: Seven Recipes for Setting Your FPGA on Fire – A Cookbook on Heat Generators
type: journal_article
user_id: '15278'
volume: 38
year: '2014'
...
---
_id: '377'
abstract:
- lang: eng
text: In this paper, we study how AES key schedules can be reconstructed from decayed
memory. This operation is a crucial and time consuming operation when trying to
break encryption systems with cold-boot attacks. In software, the reconstruction
of the AES master key can be performed using a recursive, branch-and-bound tree-search
algorithm that exploits redundancies in the key schedule for constraining the
search space. In this work, we investigate how this branch-and-bound algorithm
can be accelerated with FPGAs. We translated the recursive search procedure to
a state machine with an explicit stack for each recursion level and create optimized
datapaths to accelerate in particular the processing of the most frequently accessed
tree levels. We support two different decay models, of which especially the more
realistic non-idealized asymmetric decay model causes very high runtimes in software.
Our implementation on a Maxeler dataflow computing system outperforms a software
implementation for this model by up to 27x, which makes cold-boot attacks against
AES practical even for high error rates.
author:
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Christoph
full_name: Sorge, Christoph
last_name: Sorge
citation:
ama: 'Riebler H, Kenter T, Plessl C, Sorge C. Reconstructing AES Key Schedules from
Decayed Memory with FPGAs. In: Proceedings of Field-Programmable Custom Computing
Machines (FCCM). IEEE; 2014:222-229. doi:10.1109/FCCM.2014.67'
apa: Riebler, H., Kenter, T., Plessl, C., & Sorge, C. (2014). Reconstructing
AES Key Schedules from Decayed Memory with FPGAs. Proceedings of Field-Programmable
Custom Computing Machines (FCCM), 222–229. https://doi.org/10.1109/FCCM.2014.67
bibtex: '@inproceedings{Riebler_Kenter_Plessl_Sorge_2014, title={Reconstructing
AES Key Schedules from Decayed Memory with FPGAs}, DOI={10.1109/FCCM.2014.67},
booktitle={Proceedings of Field-Programmable Custom Computing Machines (FCCM)},
publisher={IEEE}, author={Riebler, Heinrich and Kenter, Tobias and Plessl, Christian
and Sorge, Christoph}, year={2014}, pages={222–229} }'
chicago: Riebler, Heinrich, Tobias Kenter, Christian Plessl, and Christoph Sorge.
“Reconstructing AES Key Schedules from Decayed Memory with FPGAs.” In Proceedings
of Field-Programmable Custom Computing Machines (FCCM), 222–29. IEEE, 2014.
https://doi.org/10.1109/FCCM.2014.67.
ieee: 'H. Riebler, T. Kenter, C. Plessl, and C. Sorge, “Reconstructing AES Key Schedules
from Decayed Memory with FPGAs,” in Proceedings of Field-Programmable Custom
Computing Machines (FCCM), 2014, pp. 222–229, doi: 10.1109/FCCM.2014.67.'
mla: Riebler, Heinrich, et al. “Reconstructing AES Key Schedules from Decayed Memory
with FPGAs.” Proceedings of Field-Programmable Custom Computing Machines (FCCM),
IEEE, 2014, pp. 222–29, doi:10.1109/FCCM.2014.67.
short: 'H. Riebler, T. Kenter, C. Plessl, C. Sorge, in: Proceedings of Field-Programmable
Custom Computing Machines (FCCM), IEEE, 2014, pp. 222–229.'
date_created: 2017-10-17T12:42:05Z
date_updated: 2023-09-26T13:33:50Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/FCCM.2014.67
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:14:20Z
date_updated: 2018-03-20T07:14:20Z
file_id: '1397'
file_name: 377-FCCM14.pdf
file_size: 1003907
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:14:20Z
has_accepted_license: '1'
keyword:
- coldboot
language:
- iso: eng
page: 222-229
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of Field-Programmable Custom Computing Machines (FCCM)
publisher: IEEE
quality_controlled: '1'
status: public
title: Reconstructing AES Key Schedules from Decayed Memory with FPGAs
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '365'
abstract:
- lang: eng
text: Self-aware computing is a paradigm for structuring and simplifying the design
and operation of computing systems that face unprecedented levels of system dynamics
and thus require novel forms of adaptivity. The generality of the paradigm makes
it applicable to many types of computing systems and, previously, researchers
started to introduce concepts of self-awareness to multicore architectures. In
our work we build on a recent reference architectural framework as a model for
self-aware computing and instantiate it for an FPGA-based heterogeneous multicore
running the ReconOS reconfigurable architecture and operating system. After presenting
the model for self-aware computing and ReconOS, we demonstrate with a case study
how a multicore application built on the principle of self-awareness, autonomously
adapts to changes in the workload and system state. Our work shows that the reference
architectural framework as a model for self-aware computing can be practically
applied and allows us to structure and simplify the design process, which is essential
for designing complex future computing systems.
article_number: '13'
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Achim
full_name: Lösch, Achim
id: '43646'
last_name: Lösch
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Agne A, Happe M, Lösch A, Plessl C, Platzner M. Self-awareness as a Model for
Designing and Operating Heterogeneous Multicores. ACM Transactions on Reconfigurable
Technology and Systems (TRETS). 2014;7(2). doi:10.1145/2617596
apa: Agne, A., Happe, M., Lösch, A., Plessl, C., & Platzner, M. (2014). Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores. ACM Transactions
on Reconfigurable Technology and Systems (TRETS), 7(2), Article 13.
https://doi.org/10.1145/2617596
bibtex: '@article{Agne_Happe_Lösch_Plessl_Platzner_2014, title={Self-awareness as
a Model for Designing and Operating Heterogeneous Multicores}, volume={7}, DOI={10.1145/2617596}, number={213}, journal={ACM
Transactions on Reconfigurable Technology and Systems (TRETS)}, publisher={ACM},
author={Agne, Andreas and Happe, Markus and Lösch, Achim and Plessl, Christian
and Platzner, Marco}, year={2014} }'
chicago: Agne, Andreas, Markus Happe, Achim Lösch, Christian Plessl, and Marco Platzner.
“Self-Awareness as a Model for Designing and Operating Heterogeneous Multicores.”
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7, no.
2 (2014). https://doi.org/10.1145/2617596.
ieee: 'A. Agne, M. Happe, A. Lösch, C. Plessl, and M. Platzner, “Self-awareness
as a Model for Designing and Operating Heterogeneous Multicores,” ACM Transactions
on Reconfigurable Technology and Systems (TRETS), vol. 7, no. 2, Art. no.
13, 2014, doi: 10.1145/2617596.'
mla: Agne, Andreas, et al. “Self-Awareness as a Model for Designing and Operating
Heterogeneous Multicores.” ACM Transactions on Reconfigurable Technology and
Systems (TRETS), vol. 7, no. 2, 13, ACM, 2014, doi:10.1145/2617596.
short: A. Agne, M. Happe, A. Lösch, C. Plessl, M. Platzner, ACM Transactions on
Reconfigurable Technology and Systems (TRETS) 7 (2014).
date_created: 2017-10-17T12:42:03Z
date_updated: 2023-09-26T13:33:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '78'
- _id: '518'
doi: 10.1145/2617596
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:19:19Z
date_updated: 2018-03-20T07:19:19Z
file_id: '1406'
file_name: 365-plessl14_trets_01.pdf
file_size: 916052
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:19:19Z
has_accepted_license: '1'
intvolume: ' 7'
issue: '2'
language:
- iso: eng
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: ACM Transactions on Reconfigurable Technology and Systems (TRETS)
publisher: ACM
quality_controlled: '1'
status: public
title: Self-awareness as a Model for Designing and Operating Heterogeneous Multicores
type: journal_article
user_id: '15278'
volume: 7
year: '2014'
...
---
_id: '328'
abstract:
- lang: eng
text: The ReconOS operating system for reconfigurable computing offers a unified
multi-threaded programming model and operating system services for threads executing
in software and threads mapped to reconfigurable hardware. The operating system
interface allows hardware threads to interact with software threads using well-known
mechanisms such as semaphores, mutexes, condition variables, and message queues.
By semantically integrating hardware accelerators into a standard operating system
environment, ReconOS allows for rapid design space exploration, supports a structured
application development process and improves the portability of applications
author:
- first_name: Andreas
full_name: Agne, Andreas
last_name: Agne
- first_name: Markus
full_name: Happe, Markus
last_name: Happe
- first_name: Ariane
full_name: Keller, Ariane
last_name: Keller
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Bernhard
full_name: Plattner, Bernhard
last_name: Plattner
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: Agne A, Happe M, Keller A, et al. ReconOS - An Operating System Approach for
Reconfigurable Computing. IEEE Micro. 2014;34(1):60-71. doi:10.1109/MM.2013.110
apa: Agne, A., Happe, M., Keller, A., Lübbers, E., Plattner, B., Platzner, M., &
Plessl, C. (2014). ReconOS - An Operating System Approach for Reconfigurable Computing.
IEEE Micro, 34(1), 60–71. https://doi.org/10.1109/MM.2013.110
bibtex: '@article{Agne_Happe_Keller_Lübbers_Plattner_Platzner_Plessl_2014, title={ReconOS
- An Operating System Approach for Reconfigurable Computing}, volume={34}, DOI={10.1109/MM.2013.110}, number={1},
journal={IEEE Micro}, publisher={IEEE}, author={Agne, Andreas and Happe, Markus
and Keller, Ariane and Lübbers, Enno and Plattner, Bernhard and Platzner, Marco
and Plessl, Christian}, year={2014}, pages={60–71} }'
chicago: 'Agne, Andreas, Markus Happe, Ariane Keller, Enno Lübbers, Bernhard Plattner,
Marco Platzner, and Christian Plessl. “ReconOS - An Operating System Approach
for Reconfigurable Computing.” IEEE Micro 34, no. 1 (2014): 60–71. https://doi.org/10.1109/MM.2013.110.'
ieee: 'A. Agne et al., “ReconOS - An Operating System Approach for Reconfigurable
Computing,” IEEE Micro, vol. 34, no. 1, pp. 60–71, 2014, doi: 10.1109/MM.2013.110.'
mla: Agne, Andreas, et al. “ReconOS - An Operating System Approach for Reconfigurable
Computing.” IEEE Micro, vol. 34, no. 1, IEEE, 2014, pp. 60–71, doi:10.1109/MM.2013.110.
short: A. Agne, M. Happe, A. Keller, E. Lübbers, B. Plattner, M. Platzner, C. Plessl,
IEEE Micro 34 (2014) 60–71.
date_created: 2017-10-17T12:41:55Z
date_updated: 2023-09-26T13:32:31Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/MM.2013.110
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-20T07:31:40Z
date_updated: 2018-03-20T07:31:40Z
file_id: '1426'
file_name: 328-plessl14_micro_01.pdf
file_size: 1877185
relation: main_file
success: 1
file_date_updated: 2018-03-20T07:31:40Z
has_accepted_license: '1'
intvolume: ' 34'
issue: '1'
language:
- iso: eng
page: 60-71
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: IEEE Micro
publisher: IEEE
quality_controlled: '1'
status: public
title: ReconOS - An Operating System Approach for Reconfigurable Computing
type: journal_article
user_id: '15278'
volume: 34
year: '2014'
...
---
_id: '1778'
author:
- first_name: Gianluca
full_name: C. Durelli, Gianluca
last_name: C. Durelli
- first_name: Marcello
full_name: Pogliani, Marcello
last_name: Pogliani
- first_name: Antonio
full_name: Miele, Antonio
last_name: Miele
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Marco
full_name: D. Santambrogio, Marco
last_name: D. Santambrogio
- first_name: Cristiana
full_name: Bolchini, Cristiana
last_name: Bolchini
citation:
ama: 'C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach. In: Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA). IEEE; 2014:142-149. doi:10.1109/ISPA.2014.27'
apa: 'C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G.
F., D. Santambrogio, M., & Bolchini, C. (2014). Runtime Resource Management
in Heterogeneous System Architectures: The SAVE Approach. Proc. Int. Symp.
on Parallel and Distributed Processing with Applications (ISPA), 142–149.
https://doi.org/10.1109/ISPA.2014.27'
bibtex: '@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014,
title={Runtime Resource Management in Heterogeneous System Architectures: The
SAVE Approach}, DOI={10.1109/ISPA.2014.27},
booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello
and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin
Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149}
}'
chicago: 'C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl,
Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini.
“Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.”
In Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA), 142–49. IEEE, 2014. https://doi.org/10.1109/ISPA.2014.27.'
ieee: 'G. C. Durelli et al., “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach,” in Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), 2014, pp. 142–149, doi: 10.1109/ISPA.2014.27.'
mla: 'C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous
System Architectures: The SAVE Approach.” Proc. Int. Symp. on Parallel and
Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–49, doi:10.1109/ISPA.2014.27.'
short: 'G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M.
D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed
Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.'
date_created: 2018-03-26T13:40:14Z
date_updated: 2023-09-26T13:35:40Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ISPA.2014.27
language:
- iso: eng
page: 142-149
project:
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proc. Int. Symp. on Parallel and Distributed Processing with Applications
(ISPA)
publisher: IEEE
quality_controlled: '1'
status: public
title: 'Runtime Resource Management in Heterogeneous System Architectures: The SAVE
Approach'
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '439'
abstract:
- lang: eng
text: Reconfigurable architectures provide an opportunityto accelerate a wide range
of applications, frequentlyby exploiting data-parallelism, where the same operations
arehomogeneously executed on a (large) set of data. However, whenthe sequential
code is executed on a host CPU and only dataparallelloops are executed on an FPGA
coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required,
such thatthe control- and data-transfer overheads to the coprocessor canbe amortized.
However, the trip count of large data-parallel loopsis frequently not known at
compile time, but only at runtime justbefore entering a loop. Therefore, we propose
to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere
to execute the appropriate code to the runtime of theapplication when the trip
count of the loop can be determinedjust at runtime. We demonstrate how an LLVM
compiler basedtoolflow can automatically insert appropriate decision blocks intothe
application code. Analyzing popular benchmark suites, weshow that this kind of
runtime decisions is often applicable. Thepractical feasibility of our approach
is demonstrated by a toolflowthat automatically identifies loops suitable for
vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow
adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds
for specific loops and alsoincludes support to move just the required data to
the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted
on different input data sizes.
author:
- first_name: Gavin Francis
full_name: Vaz, Gavin Francis
id: '30332'
last_name: Vaz
- first_name: Heinrich
full_name: Riebler, Heinrich
id: '8961'
last_name: Riebler
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions
to Application Runtime. In: Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032509'
apa: Vaz, G. F., Riebler, H., Kenter, T., & Plessl, C. (2014). Deferring Accelerator
Offloading Decisions to Application Runtime. Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032509
bibtex: '@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator
Offloading Decisions to Application Runtime}, DOI={10.1109/ReConFig.2014.7032509},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler,
Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl.
“Deferring Accelerator Offloading Decisions to Application Runtime.” In Proceedings
of the International Conference on ReConFigurable Computing and FPGAs (ReConFig),
1–8. IEEE, 2014. https://doi.org/10.1109/ReConFig.2014.7032509.
ieee: 'G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading
Decisions to Application Runtime,” in Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032509.'
mla: Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application
Runtime.” Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032509.
short: 'G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:17Z
date_updated: 2023-09-26T13:37:02Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032509
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:29:52Z
date_updated: 2018-03-16T11:29:52Z
file_id: '1353'
file_name: 439-plessl14a_reconfig.pdf
file_size: 557362
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:29:52Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Deferring Accelerator Offloading Decisions to Application Runtime
type: conference
user_id: '15278'
year: '2014'
...
---
_id: '406'
abstract:
- lang: eng
text: Stereo-matching algorithms recently received a lot of attention from the FPGA
acceleration community. Presented solutions range from simple, very resource efficient
systems with modest matching quality for small embedded systems to sophisticated
algorithms with several processing steps, implemented on big FPGAs. In order to
achieve high throughput, most implementations strongly focus on pipelining and
data reuse between different computation steps. This approach leads to high efficiency,
but limits the supported computation patterns and due the high integration of
the implementation, adaptions to the algorithm are difficult. In this work, we
present a stereo-matching implementation, that starts by offloading individual
kernels from the CPU to the FPGA. Between subsequent compute steps on the FPGA,
data is stored off-chip in on-board memory of the FPGA accelerator card. This
enables us to accelerate the AD-census algorithm with cross-based aggregation
and scanline optimization for the first time without algorithmic changes and for
up to full HD image dimensions. Analyzing throughput and bandwidth requirements,
we outline some trade-offs that are involved with this approach, compared to tighter
integration of more kernel loops into one design.
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Henning
full_name: Schmitz, Henning
last_name: Schmitz
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
citation:
ama: 'Kenter T, Schmitz H, Plessl C. Kernel-Centric Acceleration of High Accuracy
Stereo-Matching. In: Proceedings of the International Conference on ReConFigurable
Computing and FPGAs (ReConFig). IEEE; 2014:1-8. doi:10.1109/ReConFig.2014.7032535'
apa: Kenter, T., Schmitz, H., & Plessl, C. (2014). Kernel-Centric Acceleration
of High Accuracy Stereo-Matching. Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), 1–8. https://doi.org/10.1109/ReConFig.2014.7032535
bibtex: '@inproceedings{Kenter_Schmitz_Plessl_2014, title={Kernel-Centric Acceleration
of High Accuracy Stereo-Matching}, DOI={10.1109/ReConFig.2014.7032535},
booktitle={Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)}, publisher={IEEE}, author={Kenter, Tobias and Schmitz, Henning
and Plessl, Christian}, year={2014}, pages={1–8} }'
chicago: Kenter, Tobias, Henning Schmitz, and Christian Plessl. “Kernel-Centric
Acceleration of High Accuracy Stereo-Matching.” In Proceedings of the International
Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–8. IEEE, 2014.
https://doi.org/10.1109/ReConFig.2014.7032535.
ieee: 'T. Kenter, H. Schmitz, and C. Plessl, “Kernel-Centric Acceleration of High
Accuracy Stereo-Matching,” in Proceedings of the International Conference on
ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–8, doi: 10.1109/ReConFig.2014.7032535.'
mla: Kenter, Tobias, et al. “Kernel-Centric Acceleration of High Accuracy Stereo-Matching.”
Proceedings of the International Conference on ReConFigurable Computing and
FPGAs (ReConFig), IEEE, 2014, pp. 1–8, doi:10.1109/ReConFig.2014.7032535.
short: 'T. Kenter, H. Schmitz, C. Plessl, in: Proceedings of the International Conference
on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.'
date_created: 2017-10-17T12:42:11Z
date_updated: 2023-09-26T13:36:40Z
ddc:
- '040'
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1109/ReConFig.2014.7032535
file:
- access_level: closed
content_type: application/pdf
creator: florida
date_created: 2018-03-16T11:37:42Z
date_updated: 2018-03-16T11:37:42Z
file_id: '1366'
file_name: 406-ReConFig14.pdf
file_size: 932852
relation: main_file
success: 1
file_date_updated: 2018-03-16T11:37:42Z
has_accepted_license: '1'
language:
- iso: eng
page: 1-8
project:
- _id: '1'
grant_number: '160364472'
name: SFB 901
- _id: '14'
grant_number: '160364472'
name: SFB 901 - Subprojekt C2
- _id: '4'
name: SFB 901 - Project Area C
- _id: '34'
grant_number: '610996'
name: Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous
System Architectures
publication: Proceedings of the International Conference on ReConFigurable Computing
and FPGAs (ReConFig)
publisher: IEEE
quality_controlled: '1'
status: public
title: Kernel-Centric Acceleration of High Accuracy Stereo-Matching
type: conference
user_id: '15278'
year: '2014'
...