@inproceedings{52744, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{European Test Symposium, The Hague, Netherlands, May 20-24, 2024}}, location = {{The Hague, NL}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations}}}, year = {{2024}}, } @inproceedings{52742, author = {{Jafarzadeh, Hanieh and Klemme, Florian and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024}}, location = {{Maceió}}, pages = {{6}}, publisher = {{IEEE}}, title = {{{Vmin Testing under Variations: Defect vs. Fault Coverage}}}, year = {{2024}}, } @inproceedings{52743, author = {{Hellebrand, Sybille and Sadeghi-Kohan, Somayeh and Wunderlich, Hans-Joachim}}, booktitle = {{International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024}}, location = {{Xi'an, China}}, pages = {{1}}, title = {{{Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle}}}, year = {{2024}}, } @inproceedings{52745, author = {{Wunderlich, Hans-Joachim and Jafarzadeh, Hanieh and Hellebrand, Sybille}}, booktitle = {{International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024}}, location = {{Xi’an, China}}, pages = {{1}}, title = {{{Robust Test of Small Delay Faults under PVT-Variations}}}, year = {{2024}}, } @misc{50284, author = {{Stiballe, Alisa and Reimer, Jan Dennis and Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}}, publisher = {{37. ITG / GMM / GI -Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'24), Feb. 2024}}, title = {{{Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression}}}, year = {{2024}}, } @misc{35204, author = {{Ghazal, Abdulkarim and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}}, keywords = {{WORKSHOP}}, pages = {{2}}, publisher = {{35. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'23), Feb. 2023}}, title = {{{On Cryptography Effects on Interconnect Reliability}}}, year = {{2023}}, } @phdthesis{46482, abstract = {{Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem. With modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates. To deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.}}, author = {{Sprenger, Alexander}}, keywords = {{Testantwortkompaktierung, Prozessvariation, Silicon Lifecycle Management}}, pages = {{xi, 160}}, publisher = {{Universität Paderborn}}, title = {{{Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}}}, doi = {{10.17619/UNIPB/1-1787}}, year = {{2023}}, } @inproceedings{46739, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)}}, publisher = {{IEEE}}, title = {{{Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication}}}, doi = {{10.1109/dsn-w58399.2023.00056}}, year = {{2023}}, } @inproceedings{46738, author = {{Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, booktitle = {{IEEE Asian Test Symposium (ATS'23), October 2023}}, title = {{{Optimizing the Streaming of Sensor Data with Approximate Communication}}}, year = {{2023}}, } @article{46264, abstract = {{System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations. }}, author = {{Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}}, issn = {{2168-2356}}, journal = {{IEEE Design &Test}}, keywords = {{Electrical and Electronic Engineering, Hardware and Architecture, Software}}, pages = {{1--1}}, publisher = {{Institute of Electrical and Electronics Engineers (IEEE)}}, title = {{{Workload-Aware Periodic Interconnect BIST}}}, doi = {{10.1109/mdat.2023.3298849}}, year = {{2023}}, }